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Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85960/comment/50cd8aed_142b6b02?us… :
PS5, Line 16:
> can you please add smbios data w/o and w/ this patch for easy review ?
did you also compare the same socket type information on other SoC platforms like MTL / RPL ?
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Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85960/comment/7431739e_a89e7118?us… :
PS5, Line 16:
can you please add smbios data w/o and w/ this patch for easy review ?
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Change subject: soc/mediatek/mt8196: Remove tvdpll3 disable/enable
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86343/comment/ce742632_ffbd541d?us… :
PS1, Line 9: The enable operation cause tvdpll3 cannot be disabled during suspend,
: so we remove it.
: tvdpll3 can be enabled/disabled according to its downstream clock
: demand automatically.
> ``` […]
Done
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Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek/mt8196: Remove tvdpll3 disable/enable
......................................................................
soc/mediatek/mt8196: Remove tvdpll3 disable/enable
The tvdpll3 cannot be disabled during suspend because of the enable
operation, so we remove the enable operation. Hardware can now
automatically enable and disable tvdpll3 based on the clock demand of
its downstream.
BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK, Suspend/Resume OK and FW screen shown OK, with MMinfra
kernel/vcp patch, mminfra can be turned off to reduce power consumption.
Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.com>
Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b
---
M src/soc/mediatek/mt8196/pll.c
1 file changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86343/5
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Change subject: amdfwtool: Set entry address mode based on current table header
......................................................................
Patch Set 14:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/84530/comment/db884d44_8e85ff1b?us… :
PS13, Line 385: is mode 2 or 3.
> This doesn't match with the macro below. […]
Done
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I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: amdfwtool: Set entry address mode based on current table header
......................................................................
amdfwtool: Set entry address mode based on current table header
The address field of each PSP or BIOS entry defines the location of
the entry.
For the family newer than Cezanne, the upper 2 bits define the address
mode. In table header, the address mode of the table is set. They have
the same definition.
Address Mode 0: Physical Address
Address Mode 1: Relative Address to entire BIOS image
Address Mode 2: Relative Address to PSP/BIOS directory
Address Mode 3: Relative Address to slot N
In common case, the address mode of entry should be the same as its
table. In spec, it says, "attribute is ignored if the directory
address mode is not 2 or 3",
In the old code, if the header defines address mode as relative BIOS(1),
the entry address mode is not set. That meets the spec. PSP doesn't
use, but amdfwtool can use it to record the address mode and transfer
it to table. That can reduce the code complexity.
Identidal binary test passes on platforms which are not based on
Cezanne, V2000A, Genoa. Booting test passes on Majolica/Cezanne.
Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
1 file changed, 8 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/84530/14
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Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86349?usp=email )
Change subject: device/pci_rom.c: Remove pci_ram_image_start
......................................................................
device/pci_rom.c: Remove pci_ram_image_start
The variable is modified, but the modified value is never used. So we
might as well stick to the the definition directly. It also fits the
other code with the PCI_VGA_RAM_IMAGE_START definition a little better.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I525143d017c68086f101a638d1472bc607c48cc2
---
M src/device/pci_rom.c
1 file changed, 3 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/86349/1
diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index d60720e..d0e9104 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -129,8 +129,6 @@
return rom_header;
}
-static void *pci_ram_image_start = (void *)PCI_RAM_IMAGE_START;
-
struct rom_header *pci_rom_load(struct device *dev,
struct rom_header *rom_header)
{
@@ -173,11 +171,10 @@
}
printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x bytes\n",
- rom_header, pci_ram_image_start, rom_size);
+ rom_header, (void *)PCI_RAM_IMAGE_START, rom_size);
- memcpy(pci_ram_image_start, rom_header, rom_size);
- pci_ram_image_start += rom_size;
- return (struct rom_header *)(pci_ram_image_start-rom_size);
+ memcpy((void *)PCI_RAM_IMAGE_START, rom_header, rom_size);
+ return (struct rom_header *)PCI_RAM_IMAGE_START;
}
/* ACPI */
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Change subject: security: Allow vboot when INTEL_TXT enabled
......................................................................
Patch Set 15: Code-Review+2
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