coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/nissa/var/dirks: Update GPIO table
by Ivy Jian (Code Review) 11 Feb '25

11 Feb '25

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86351?usp=email ) Change subject: mb/google/nissa/var/dirks: Update GPIO table ...................................................................... mb/google/nissa/var/dirks: Update GPIO table Configure buzzer to GPP_D2 based on schematic change. BUG=b:389391653 TEST=emerge-nissa coreboot Change-Id: Iefc6aefeae0a3a05ba04fb2718c6c3a3058de5f8 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/dirks/Makefile.mk M src/mainboard/google/brya/variants/dirks/gpio.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/86351/1 diff --git a/src/mainboard/google/brya/variants/dirks/Makefile.mk b/src/mainboard/google/brya/variants/dirks/Makefile.mk index d38141c..bc39984 100644 --- a/src/mainboard/google/brya/variants/dirks/Makefile.mk +++ b/src/mainboard/google/brya/variants/dirks/Makefile.mk @@ -4,3 +4,4 @@ romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/dirks/gpio.c b/src/mainboard/google/brya/variants/dirks/gpio.c index 94eaff5..209ca04 100644 --- a/src/mainboard/google/brya/variants/dirks/gpio.c +++ b/src/mainboard/google/brya/variants/dirks/gpio.c @@ -19,8 +19,6 @@ /* B4 : LAN_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, PLTRST), - /* B14 : SPKR ==> PWM_PP3300_BUZZER */ - PAD_CFG_GPO_LOCK(GPP_B14, 0, LOCK_CONFIG), /* B16 : I2C5_SDA ==> NC */ PAD_NC(GPP_B16, NONE), /* B17 : I2C5_SCL ==> NC */ @@ -37,6 +35,8 @@ /* C7 : SML1DATA ==> NC */ PAD_NC(GPP_C7, NONE), + /* D2 : PWM_PP3300_BUZZER */ + PAD_CFG_GPO(GPP_D2, 0, DEEP), /* D3 : ISH_GP3 ==> NC */ PAD_NC(GPP_D3, NONE), /* D6 : SRCCLKREQ1# ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86351?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iefc6aefeae0a3a05ba04fb2718c6c3a3058de5f8 Gerrit-Change-Number: 86351 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
by Subrata Banik (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Bora Guvendik, Zhixing Ma. Subrata Banik has posted comments on this change by Zhixing Ma. ( https://review.coreboot.org/c/coreboot/+/85960?usp=email ) Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85960/comment/50cd8aed_142b6b02?us… : PS5, Line 16: > can you please add smbios data w/o and w/ this patch for easy review ? did you also compare the same socket type information on other SoC platforms like MTL / RPL ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d Gerrit-Change-Number: 85960 Gerrit-PatchSet: 5 Gerrit-Owner: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Zhixing Ma <zhixing.ma(a)intel.corp-partner.google.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Comment-Date: Tue, 11 Feb 2025 06:04:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
by Subrata Banik (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Bora Guvendik, Zhixing Ma. Subrata Banik has posted comments on this change by Zhixing Ma. ( https://review.coreboot.org/c/coreboot/+/85960?usp=email ) Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85960/comment/7431739e_a89e7118?us… : PS5, Line 16: can you please add smbios data w/o and w/ this patch for easy review ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d Gerrit-Change-Number: 85960 Gerrit-PatchSet: 5 Gerrit-Owner: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Zhixing Ma <zhixing.ma(a)intel.corp-partner.google.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Comment-Date: Tue, 11 Feb 2025 06:02:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/fatcat: Add power limits for additional PTL-H variants
by Subrata Banik (Code Review) 10 Feb '25

10 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86339?usp=email ) Change subject: mb/google/fatcat: Add power limits for additional PTL-H variants ...................................................................... mb/google/fatcat: Add power limits for additional PTL-H variants This commit adds power limit configurations for additional variants of the Intel PTL-H platform found on Fatcat. Specifically, it adds entries for PCI Device IDs 2, 3, and 4. These configurations define the PL1, PL2, and PL4 power limits, as well as the associated CPU TDP and power limits index. The PL4 values are currently placeholders and marked for future fine-tuning. BUG=b:395130929 TEST=Able to boot google/fatcat with 65W USB-C PD charger. Change-Id: I86befb07f39a5e292365ea40ea08d0f93f38a7a6 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86339 Reviewed-by: Jayvik Desai <jayvik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c 1 file changed, 30 insertions(+), 0 deletions(-) Approvals: Jayvik Desai: Looks good to me, approved build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c index 4b9cfd2..969cd4a 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c @@ -18,6 +18,36 @@ .pl2_max_power = 50000, .pl4_power = 50000 /* TODO: needs fine tuning */ }, + { + .mch_id = PCI_DID_INTEL_PTL_H_ID_2, + .cpu_tdp = 25, + .power_limits_index = PTL_H_1_CORE, + .pl1_min_power = 10000, + .pl1_max_power = 25000, + .pl2_min_power = 50000, + .pl2_max_power = 50000, + .pl4_power = 50000 /* TODO: needs fine tuning */ + }, + { + .mch_id = PCI_DID_INTEL_PTL_H_ID_3, + .cpu_tdp = 25, + .power_limits_index = PTL_H_2_CORE, + .pl1_min_power = 10000, + .pl1_max_power = 25000, + .pl2_min_power = 50000, + .pl2_max_power = 50000, + .pl4_power = 50000 /* TODO: needs fine tuning */ + }, + { + .mch_id = PCI_DID_INTEL_PTL_H_ID_4, + .cpu_tdp = 25, + .power_limits_index = PTL_H_2_CORE, + .pl1_min_power = 10000, + .pl1_max_power = 25000, + .pl2_min_power = 50000, + .pl2_max_power = 50000, + .pl4_power = 50000 /* TODO: needs fine tuning */ + }, }; void baseboard_devtree_update(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/86339?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86befb07f39a5e292365ea40ea08d0f93f38a7a6 Gerrit-Change-Number: 86339 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Remove tvdpll3 disable/enable
by Jarried Lin (Code Review) 10 Feb '25

10 Feb '25

Attention is currently required from: Guangjie Song, Hung-Te Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86343?usp=email ) Change subject: soc/mediatek/mt8196: Remove tvdpll3 disable/enable ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86343/comment/ce742632_ffbd541d?us… : PS1, Line 9: The enable operation cause tvdpll3 cannot be disabled during suspend, : so we remove it. : tvdpll3 can be enabled/disabled according to its downstream clock : demand automatically. > ``` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b Gerrit-Change-Number: 86343 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 11 Feb 2025 03:50:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Remove tvdpll3 disable/enable
by Jarried Lin (Code Review) 10 Feb '25

10 Feb '25

Attention is currently required from: Guangjie Song, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86343?usp=email to look at the new patch set (#5). Change subject: soc/mediatek/mt8196: Remove tvdpll3 disable/enable ...................................................................... soc/mediatek/mt8196: Remove tvdpll3 disable/enable The tvdpll3 cannot be disabled during suspend because of the enable operation, so we remove the enable operation. Hardware can now automatically enable and disable tvdpll3 based on the clock demand of its downstream. BRANCH=rauru BUG=b:377628718 TEST=Bootup OK, Suspend/Resume OK and FW screen shown OK, with MMinfra kernel/vcp patch, mminfra can be turned off to reduce power consumption. Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.com> Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b --- M src/soc/mediatek/mt8196/pll.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86343/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b Gerrit-Change-Number: 86343 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: amdfwtool: Set entry address mode based on current table header
by Bao Zheng (Code Review) 10 Feb '25

10 Feb '25

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Maximilian Brune, Zheng Bao, ritul guru. Bao Zheng has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84530?usp=email ) Change subject: amdfwtool: Set entry address mode based on current table header ...................................................................... Patch Set 14: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/84530/comment/db884d44_8e85ff1b?us… : PS13, Line 385: is mode 2 or 3. > This doesn't match with the macro below. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84530?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095 Gerrit-Change-Number: 84530 Gerrit-PatchSet: 14 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 11 Feb 2025 03:33:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: amdfwtool: Set entry address mode based on current table header
by Bao Zheng (Code Review) 10 Feb '25

10 Feb '25

Attention is currently required from: Bao Zheng, Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Hello Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84530?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Set entry address mode based on current table header ...................................................................... amdfwtool: Set entry address mode based on current table header The address field of each PSP or BIOS entry defines the location of the entry. For the family newer than Cezanne, the upper 2 bits define the address mode. In table header, the address mode of the table is set. They have the same definition. Address Mode 0: Physical Address Address Mode 1: Relative Address to entire BIOS image Address Mode 2: Relative Address to PSP/BIOS directory Address Mode 3: Relative Address to slot N In common case, the address mode of entry should be the same as its table. In spec, it says, "attribute is ignored if the directory address mode is not 2 or 3", In the old code, if the header defines address mode as relative BIOS(1), the entry address mode is not set. That meets the spec. PSP doesn't use, but amdfwtool can use it to record the address mode and transfer it to table. That can reduce the code complexity. Identidal binary test passes on platforms which are not based on Cezanne, V2000A, Genoa. Booting test passes on Majolica/Cezanne. Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/84530/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/84530?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095 Gerrit-Change-Number: 84530 Gerrit-PatchSet: 14 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: device/pci_rom.c: Remove pci_ram_image_start
by Maximilian Brune (Code Review) 10 Feb '25

10 Feb '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86349?usp=email ) Change subject: device/pci_rom.c: Remove pci_ram_image_start ...................................................................... device/pci_rom.c: Remove pci_ram_image_start The variable is modified, but the modified value is never used. So we might as well stick to the the definition directly. It also fits the other code with the PCI_VGA_RAM_IMAGE_START definition a little better. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I525143d017c68086f101a638d1472bc607c48cc2 --- M src/device/pci_rom.c 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/86349/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index d60720e..d0e9104 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -129,8 +129,6 @@ return rom_header; } -static void *pci_ram_image_start = (void *)PCI_RAM_IMAGE_START; - struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header) { @@ -173,11 +171,10 @@ } printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x bytes\n", - rom_header, pci_ram_image_start, rom_size); + rom_header, (void *)PCI_RAM_IMAGE_START, rom_size); - memcpy(pci_ram_image_start, rom_header, rom_size); - pci_ram_image_start += rom_size; - return (struct rom_header *)(pci_ram_image_start-rom_size); + memcpy((void *)PCI_RAM_IMAGE_START, rom_header, rom_size); + return (struct rom_header *)PCI_RAM_IMAGE_START; } /* ACPI */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I525143d017c68086f101a638d1472bc607c48cc2 Gerrit-Change-Number: 86349 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: security: Allow vboot when INTEL_TXT enabled
by Julius Werner (Code Review) 10 Feb '25

10 Feb '25

Attention is currently required from: Christian Walter, Filip Lewiński, Michał Żygowski. Julius Werner has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82695?usp=email ) Change subject: security: Allow vboot when INTEL_TXT enabled ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82695?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19dc3d910c23fcfd8732465c488f47dd86a96781 Gerrit-Change-Number: 82695 Gerrit-PatchSet: 15 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Tue, 11 Feb 2025 01:51:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit February 2025