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Change subject: mb/google/fatcat: Use TDP macros for CPU TDP values
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/mediatek/mt8196: Remove tvdpll3 disable/enable
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86343/comment/84d0831f_b0c4354e?us… :
PS1, Line 9: The enable operation cause tvdpll3 cannot be disabled during suspend,
: so we remove it.
: tvdpll3 can be enabled/disabled according to its downstream clock
: demand automatically.
> fixed
```
The tvdpll3 cannot be disabled during suspend because of the enable operation, so
we remove the enable operation. Hardware can now automatically enable and disable
tvdpll3 based on the clock demand of its downstream.
```
Please adjust the commit message to 72 characters per line and resolve the comment.
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Change subject: soc/mediatek/mt8196: Remove tvdpll3 disable/enable
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86343/comment/2da6a4ea_b08fcfe3?us… :
PS1, Line 9: The enable operation cause tvdpll3 cannot be disabled during suspend,
: so we remove it.
: tvdpll3 can be enabled/disabled according to its downstream clock
: demand automatically.
> 1. Add `by hardware` after `automatically` to make that clear […]
fixed
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Guangjie Song has uploaded a new patch set (#4) to the change originally created by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86343?usp=email )
Change subject: soc/mediatek/mt8196: Remove tvdpll3 disable/enable
......................................................................
soc/mediatek/mt8196: Remove tvdpll3 disable/enable
The enable operation cause tvdpll3 cannot be disabled during suspend, so we remove it.
tvdpll3 can be enabled/disabled according to its downstream clock demand automatically by hardware.
BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK, Suspend/Resume OK and FW screen shown OK, with MMinfra
kernel/vcp patch, mminfra can be turned off to reduce power consumption.
Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.com>
Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b
---
M src/soc/mediatek/mt8196/pll.c
1 file changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86343/4
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Change subject: vc/google/chromeos: Implement platform callback for critical shutdown
......................................................................
Patch Set 9:
(1 comment)
File src/vendorcode/google/chromeos/battery.c:
https://review.coreboot.org/c/coreboot/+/86228/comment/eff080ef_769eef83?us… :
PS9, Line 49: void platform_issue_low_battery_shutdown(void)
Due to CB:86336 we can move this into common code somewhere, it doesn't need to be in `vendorcode/chromeos` and be called `platform_...` anymore.
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Change subject: soc/intel/cmn/pmc: Add support for early power off
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/86336/comment/1f4aeb54_786935af?us… :
PS3, Line 635: __weak void platform_do_early_poweroff(void)
> I appreciate your suggestion @th3fanbus@gmail. […]
I agree with Jérémy on the first item: the whole point of making this function `__weak` is that `google/chromeec/ec.c` could directly override it, so that we don't need to add code that calls a Google-specific function directly to this common Intel PMC driver. I think it's fine if the Google ChromeEC code implements a function called `platform_do_early_poweroff()`. That name doesn't say anything about Intel, it's generic enough that if other platforms would have a need for the same functionality they could use the same function.
(I don't know about whether it makes sense to call the PMC function in the fallback case or just do `halt()` directly, I'll let you guys argue about that.)
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Change subject: drivers/intel/fsp2_0: Add low battery indicator screen
......................................................................
Patch Set 10: Code-Review+2
(1 comment)
File src/vendorcode/google/chromeos/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/86225/comment/7256a5e5_65c9cb18?us… :
PS8, Line 45: low_battery.bmp,CONFIG_PLATFORM_LOW_BATTERY_INDICATOR_LOGO_PATH))
> > This should go either in `fsp2_0/Makefile.mk` or in `src/lib/Makefile.mk` (because `bmp_logo. […]
Oh, okay, so we have it there. I didn't see that. It is kinda weird though that the code that uses it is in `src/lib`, but the code adding that logo is in `src/drivers/intel/fsp2_0` (so if you used the splash screen on a non-Intel board you wouldn't actually get the logo in your CBFS).
Not really related to this patch but it would probably make sense to move that part into `src/lib/Makefile.mk` at some point.
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Change subject: lib: Refactor ux_locales_get_text API
......................................................................
Patch Set 12:
(4 comments)
File src/include/ux_locales.h:
https://review.coreboot.org/c/coreboot/+/86283/comment/b16b0dbe_68d97dd6?us… :
PS12, Line 22: * Otherwise NULL (for unit-tests).
No longer applicable
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PS12, Line 207: const char *ux_locales_get_text(enum ux_locale_msg msg_id)
nit: not really clear why this part is an extra function rather than inlined into the other one?
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https://review.coreboot.org/c/coreboot/+/86283/comment/495886dc_fb4edf28?us… :
PS12, Line 213: "Please do not turn off your device_0"),
There should also be at least one test that successfully finds a lang_id which is not 0 (because 0 is the default anyway).
https://review.coreboot.org/c/coreboot/+/86283/comment/4b0dbe98_4333702a?us… :
PS12, Line 215: 7
Maybe make this a `3`, then you also include the "check the whole string of lang_id" part here (because `3` is a prefix of `30` which does exist).
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Change subject: lib: Add low battery UX locale message
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
Please expand ux_locales-test.c here so that we have at least two messages in the test data there.
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Hello Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85960?usp=email
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Verified-1 by build bot (Jenkins)
Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
......................................................................
mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
The current SMBIOS for fatcat is missing processor upgrade info,
This patch adds the missing value by enabling a kconfig flag.
Refer to SMBIOS spec sheet for documentation on cpu socket values:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/defau…
BUG=NONE
TEST=Boot and verified that SMBIOS processor upgrade value is correct.
Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d
Signed-off-by: Zhixing Ma <zhixing.ma(a)intel.com>
---
M src/mainboard/google/fatcat/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85960/5
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