coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: util/intelmetool: Add Ice Lake support
by Name of user not set (Code Review) 06 Jan '25

06 Jan '25

openrc(a)posteo.de has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/85867?usp=email ) Change subject: util/intelmetool: Add Ice Lake support ...................................................................... Abandoned I was not aware Ice lake was removed on purpose. -- To view, visit https://review.coreboot.org/c/coreboot/+/85867?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11045c6456e73057719a9811f5bb4e4ca4fb4543 Gerrit-Change-Number: 85867 Gerrit-PatchSet: 1 Gerrit-Owner: openrc(a)posteo.de Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>

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[XS] Change in coreboot[main]: drivers/usb/acpi: Don't add GPIOs to _CRS for Intel Bluetooth
by Sean Rhodes (Code Review) 06 Jan '25

06 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85866?usp=email ) Change subject: drivers/usb/acpi: Don't add GPIOs to _CRS for Intel Bluetooth ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8502d03db3d43385ac19bc3c17a79232bde1aa94 Gerrit-Change-Number: 85866 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 06 Jan 2025 16:36:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: Documentation: Fix invalid Wikipedia link
by Name of user not set (Code Review) 06 Jan '25

06 Jan '25

openrc(a)posteo.de has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/85868?usp=email ) Change subject: Documentation: Fix invalid Wikipedia link ...................................................................... Documentation: Fix invalid Wikipedia link Previous redirect to the Wikipedia page for GPIO led to nowhere. Change-Id: I22dc606623dbc32af463e4501f1f21c119453792 Signed-off-by: libreandre <openrc(a)posteo.de> --- M Documentation/acronyms.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/85868/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85868?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22dc606623dbc32af463e4501f1f21c119453792 Gerrit-Change-Number: 85868 Gerrit-PatchSet: 2 Gerrit-Owner: openrc(a)posteo.de

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[XS] Change in coreboot[main]: Documentation: Fix invalid Wikipedia link
by Name of user not set (Code Review) 06 Jan '25

06 Jan '25

openrc(a)posteo.de has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85868?usp=email ) Change subject: Documentation: Fix invalid Wikipedia link ...................................................................... Documentation: Fix invalid Wikipedia link Change-Id: I22dc606623dbc32af463e4501f1f21c119453792 Signed-off-by: libreandre <openrc(a)posteo.de> --- M Documentation/acronyms.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/85868/1 diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md index 1bdfe87..199a7da 100644 --- a/Documentation/acronyms.md +++ b/Documentation/acronyms.md @@ -409,7 +409,7 @@ * GPD - PCH GPIO in Deep Sleep well (D5 power) * GPE - ACPI: General Purpose Event * GPI - GPIOs: GPIO Input -* GPIO - [**General Purpose Input/Output**](https://en.wikipedia.org/wiki/General-purpose_Input/Output) (Pin) +* GPIO - [**General Purpose Input/Output**](https://en.wikipedia.org/wiki/General-purpose_input/output) (Pin) * GPMR - Intel: General Purpose Memory Range * GPO - GPIOs: GPIO Output * GPP - AMD: General Purpose (PCI/PCIe) port -- To view, visit https://review.coreboot.org/c/coreboot/+/85868?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22dc606623dbc32af463e4501f1f21c119453792 Gerrit-Change-Number: 85868 Gerrit-PatchSet: 1 Gerrit-Owner: openrc(a)posteo.de

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[XS] Change in coreboot[main]: util/intelmetool: Add Ice Lake support
by Name of user not set (Code Review) 06 Jan '25

06 Jan '25

openrc(a)posteo.de has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85867?usp=email ) Change subject: util/intelmetool: Add Ice Lake support ...................................................................... util/intelmetool: Add Ice Lake support Change-Id: I11045c6456e73057719a9811f5bb4e4ca4fb4543 Signed-off-by: libreandre <openrc(a)posteo.de> --- M util/intelmetool/intelmetool.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/85867/1 diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h index 3946f95..e4d012a 100644 --- a/util/intelmetool/intelmetool.h +++ b/util/intelmetool/intelmetool.h @@ -457,6 +457,7 @@ #define PCI_DEVICE_ID_INTEL_UNIONPOINT_MEI1 0xA2BA /* Union Point MEI #1 */ #define PCI_DEVICE_ID_INTEL_UNIONPOINT_MEI2 0xA2BB /* Union Point MEI #2 */ #define PCI_DEVICE_ID_INTEL_UNIONPOINT_MEI3 0xA2BE /* Union Point MEI #3 */ +#define PCI_DEVICE_ID_INTEL_ICELAKE 0x34E0 /* Ice Lake */ #define PCI_DEV_HAS_SUPPORTED_ME(x) ( \ ((x) == PCI_DEVICE_ID_INTEL_COUGARPOINT_1) || \ @@ -515,4 +516,5 @@ ((x) == PCI_DEVICE_ID_INTEL_UNIONPOINT_MEI1) || \ ((x) == PCI_DEVICE_ID_INTEL_UNIONPOINT_MEI2) || \ ((x) == PCI_DEVICE_ID_INTEL_UNIONPOINT_MEI3) || \ + ((x) == PCI_DEVICE_ID_INTEL_ICELAKE) || \ 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/85867?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11045c6456e73057719a9811f5bb4e4ca4fb4543 Gerrit-Change-Number: 85867 Gerrit-PatchSet: 1 Gerrit-Owner: openrc(a)posteo.de

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[XS] Change in coreboot[main]: qualcomm/common: Remove dead code
by Jonathon Hall (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Ariel Otilibili. Jonathon Hall has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85778?usp=email ) Change subject: qualcomm/common: Remove dead code ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85778?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40cffcf3714decfc54f2bbce9d4a867a9313d72e Gerrit-Change-Number: 85778 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Mon, 06 Jan 2025 16:12:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_hal_common.c
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85861?usp=email ) Change subject: soc/mediatek/common/dp: Move common functions to dptx_hal_common.c ...................................................................... Patch Set 4: (10 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85861/comment/409d4d85_914a6255?us… : PS3, Line 11: Adding Add https://review.coreboot.org/c/coreboot/+/85861/comment/3c0396c1_41db22c5?us… : PS3, Line 12: underly underlying? File src/soc/mediatek/common/dp/dptx_hal.c: https://review.coreboot.org/c/coreboot/+/85861/comment/354f4011_5c3fe37d?us… : PS3, Line 339: 0xfff Not related to this patch, but this looks like a bug. The value 0x2020 bits should be contained in the mask 0xfff. See the TODO comment in `mtk_dp_mask()`. MT8196's code has the same problem. https://review.coreboot.org/c/coreboot/+/85861/comment/ee38a5ab_ed2aefe5?us… : PS3, Line 64: 0 (Just to keep track of the difference) This is `hbp` for mt8196. https://review.coreboot.org/c/coreboot/+/85861/comment/43584ad4_7f653545?us… : PS3, Line 72: mtk_dp_mask(mtk_dp, REG_302C_DP_ENCODER0_P0, : 0 << VSP_SW_DP_ENCODER0_P0_FLDMASK_POS, : VSP_SW_DP_ENCODER0_P0_FLDMASK); (Just to keep track of the difference) mt8196 does NOT have this. https://review.coreboot.org/c/coreboot/+/85861/comment/dbda4b34_bab0e9ce?us… : PS3, Line 80: hsync + hbp This is `hsync + hbp + hfp` for mt8196. https://review.coreboot.org/c/coreboot/+/85861/comment/1496deaa_a67059a6?us… : PS3, Line 85: vsync + vbp This is `vsync + vbp + vfp` for mt8196. File src/soc/mediatek/common/dp/dptx_hal_common.c: https://review.coreboot.org/c/coreboot/+/85861/comment/4af02de0_37a08be7?us… : PS3, Line 56: u32 Unrelated to this patch, but this should be `u8`. https://review.coreboot.org/c/coreboot/+/85861/comment/4e61c93d_d8664dc0?us… : PS3, Line 115: DP_CLRSETBITS(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, val, 0x7); This would be wrong for mt8196, where its code is `mtk_dp_mask(mtk_dp, REG_303C_DP_ENCODER0_P0, val << 8, 0x7 << 8)`. What would you define `DP_CLRSETBITS` for mt8196? To solve the `mtk_dp_write_byte` vs `mtk_dp_mask` problem, I think we should keep this line as `mtk_dp_write_byte`, and the define mt8196's `mtk_dp_write_byte` as: ``` void mtk_dp_write_byte(...) { if (addr % 2) mtk_dp_mask(mtk_dp, addr - 1, val << 8, mask << 8); else mtk_dp_mask(mtk_dp, addr, val, mask); } ``` That is, mt8196 skips the `DP_TX_TOP_APB_WSTRB` writes. https://review.coreboot.org/c/coreboot/+/85861/comment/8a651815_fb64fff0?us… : PS3, Line 143: DP_CLRSETBITS(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, Same here. -- To view, visit https://review.coreboot.org/c/coreboot/+/85861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e151bc766c312eaf81b4220782775ef1c9d2297 Gerrit-Change-Number: 85861 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 16:06:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_common.c
by Yu-Ping Wu (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85860?usp=email ) Change subject: soc/mediatek/common/dp: Move common functions to dptx_common.c ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/common/dp/dptx_common.c: https://review.coreboot.org/c/coreboot/+/85860/comment/acbae64c_377cfb34?us… : PS4, Line 281: union misc_t dptx_misc; Not related to this patch, but some fields are not initialized. We should write `dptx_misc = { .cmisc = {0} }` here. -- To view, visit https://review.coreboot.org/c/coreboot/+/85860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5074feee9efa62f27c118eaf7adb25875ba4c16 Gerrit-Change-Number: 85860 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 15:47:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Patrick Rudolph (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Paul Menzel, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85806/comment/25437395_d80e936b?us… : PS3, Line 21: > Maybe add the new log messages? ``` MMU: Upper MEM limit is 0x228000000000 MMU: New page tables are required``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 15:20:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Patrick Rudolph (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Paul Menzel, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85806/comment/882190b4_cf8c5725?us… : PS3, Line 9: support > support*s* Done File src/cpu/x86/64bit/mmu.c: https://review.coreboot.org/c/coreboot/+/85806/comment/a761a118_8933c49e?us… : PS3, Line 150: else > unnecessary `else` keyword. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Jan 2025 15:20:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit January 2025