coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
3270 discussions

[XS] Change in coreboot[main]: mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin
by Subrata Banik (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Li1 Feng, Paul Menzel, Pranava Y N. Subrata Banik has posted comments on this change by Li1 Feng. ( https://review.coreboot.org/c/coreboot/+/86005?usp=email ) Change subject: mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a Gerrit-Change-Number: 86005 Gerrit-PatchSet: 5 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 02:37:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin
by Li1 Feng (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik. Li1 Feng has posted comments on this change by Li1 Feng. ( https://review.coreboot.org/c/coreboot/+/86005?usp=email ) Change subject: mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86005/comment/24a01272_f027f20c?us… : PS2, Line 7: fatcat-ish > Please use a longer prefix. `git log --oneline` should show you kind of a template. Done https://review.coreboot.org/c/coreboot/+/86005/comment/4c5d200e_bc3a0174?us… : PS2, Line 11: causing ISH low power mode failure > How is this failure detected? ISH console log shows it hang during boot up; not able to register with cros_ec. File src/mainboard/google/fatcat/variants/fatcat/fw_config.c: https://review.coreboot.org/c/coreboot/+/86005/comment/ab287523_b0bfecee?us… : PS2, Line 432: /* GPP_D05: ISH_UART0_RXD */ : PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2), > > We still have ISH log, just console doesn't accept input. […] Added this to comment. In any case, like for debug purpose, if we want to input to console working, we can revert this change(better be local change) and make sure ISH DIP switch setting is ON. -- To view, visit https://review.coreboot.org/c/coreboot/+/86005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a Gerrit-Change-Number: 86005 Gerrit-PatchSet: 5 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 02:31:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Li1 Feng <li1.feng(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XS] Change in coreboot[main]: mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin
by Li1 Feng (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Li1 Feng, Pranava Y N. Hello Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86005?usp=email to look at the new patch set (#5). Change subject: mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin ...................................................................... mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin On PTL RVP, ISH shares UART with FPS, we can enable either ISH UART or FPS UART, or disable both UART by changing the DIP switch settings. When DIP switch is not set for ISH, ISH RX signal is disconnected, causing ISH low power mode failure. Therefore, NC ISH RX pin mux to minimize the impact on ISH PM. As a result, ISH console won't accept input since this pin is not connected. TEST=PTL RVP H1 DB, DIP SW1317 3-6, 4-5 ON to enable FPS UART, ISH main firmware boots up and runs successfully. SW1317 all switches OFF to disable both FPS and ISH UART, ISH main firmware boots up and runs successfully. Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a Signed-off-by: Li Feng <li1.feng(a)intel.com> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c 2 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/86005/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a Gerrit-Change-Number: 86005 Gerrit-PatchSet: 5 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

1 0

[XS] Change in coreboot[main]: mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin
by Li1 Feng (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Li1 Feng, Pranava Y N. Hello Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86005?usp=email to look at the new patch set (#4). Change subject: mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin ...................................................................... mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin On PTL RVP, ISH shares UART with FPS, we can enable either ISH UART or FPS UART, or disable both UART by changing the DIP switch settings. When DIP switch is not set for ISH, ISH RX signal is disconnected, causing ISH low power mode failure. Therefore, NC ISH RX pin mux to minimize the impact on ISH PM. TEST=PTL RVP H1 DB, DIP SW1317 3-6, 4-5 ON to enable FPS UART, ISH main firmware boots up and runs successfully. SW1317 all switches OFF to disable both FPS and ISH UART, ISH main firmware boots up and runs successfully. Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a Signed-off-by: Li Feng <li1.feng(a)intel.com> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c 2 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/86005/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86005?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a Gerrit-Change-Number: 86005 Gerrit-PatchSet: 4 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

1 0

[XS] Change in coreboot[main]: soc/intel/common/pmc: Change GPE DW duplicate message to warning
by Subrata Banik (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Kapil Porwal, Matt DeVillier. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86174?usp=email ) Change subject: soc/intel/common/pmc: Change GPE DW duplicate message to warning ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: @matt.devillier@gmail.com can you please CR this CL again? lost vote while addressing last review comments -- To view, visit https://review.coreboot.org/c/coreboot/+/86174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7804ddfa6e067014e034364bd8efbf6efe746cd7 Gerrit-Change-Number: 86174 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 02:06:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Update UFS disable sequence
by Subrata Banik (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86170?usp=email ) Change subject: soc/intel/alderlake/romstage: Update UFS disable sequence ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97 Gerrit-Change-Number: 86170 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 02:04:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Subrata Banik (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Karthik Ramasubramanian, Krishna P Bhat D, Sowmya Aralguppe. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86169?usp=email ) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 29 Jan 2025 02:04:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: sb/intel/bd82x6x: Drop xhci_overcurrent_mapping
by Keith Hui (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella. Hello Intel coreboot Reviewers, Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85925?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+2 by Jérémy Compostella, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: sb/intel/bd82x6x: Drop xhci_overcurrent_mapping ...................................................................... sb/intel/bd82x6x: Drop xhci_overcurrent_mapping This is now drawn (indirectly) from main usb_port_config. Also drop it from autoport. Change-Id: I8c5e9b2016cf56538de06575181a0a6b738c6a28 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/bd82x6x/chip.h M util/autoport/bd82x6x.go 2 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/85925/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c5e9b2016cf56538de06575181a0a6b738c6a28 Gerrit-Change-Number: 85925 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[XS] Change in coreboot[main]: util/crossgcc/buildgcc: Add riscv64-elf to targets
by Karthik Ramasubramanian (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Elyes Haouas, Jon Murphy. Karthik Ramasubramanian has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/coreboot/+/86171?usp=email ) Change subject: util/crossgcc/buildgcc: Add riscv64-elf to targets ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9 Gerrit-Change-Number: 86171 Gerrit-PatchSet: 6 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 28 Jan 2025 23:27:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: soc/intel/tigerlake: Change the maximum C state to C8
by Paul Menzel (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Nick Vaccaro, Sean Rhodes, Subrata Banik. Paul Menzel has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86199?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/tigerlake: Change the maximum C state to C8 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86199/comment/2b9c4733_9f092880?us… : PS1, Line 9: Tigerr Tiger -- To view, visit https://review.coreboot.org/c/coreboot/+/86199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fe0f5a8f9b52a44d1951037d74df4a244ba602e Gerrit-Change-Number: 86199 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 28 Jan 2025 22:13:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2025