coreboot-gerrit January 2025

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[S] Change in coreboot[main]: drivers/amd/opensil/acpi.c: Factor common ACPI calls to openSIL driver
by Felix Held (Code Review) 28 Jan '25

28 Jan '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85633?usp=email ) Change subject: drivers/amd/opensil/acpi.c: Factor common ACPI calls to openSIL driver ...................................................................... drivers/amd/opensil/acpi.c: Factor common ACPI calls to openSIL driver Refactor to factor out and route ACPI calls through the openSIL driver interface to separate main SoC code from vendorcode. Change-Id: I9fa4f60164333ec7a268702fa3e94979a1b83594 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85633 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/amd/opensil/Makefile.mk A src/drivers/amd/opensil/acpi.c M src/drivers/amd/opensil/opensil.h M src/soc/amd/genoa_poc/acpi.c M src/soc/amd/phoenix/acpi.c M src/vendorcode/amd/opensil/genoa_poc/acpi.c M src/vendorcode/amd/opensil/opensil.h M src/vendorcode/amd/opensil/stub/ramstage.c 8 files changed, 38 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/drivers/amd/opensil/Makefile.mk b/src/drivers/amd/opensil/Makefile.mk index 1d20936..82e025b 100644 --- a/src/drivers/amd/opensil/Makefile.mk +++ b/src/drivers/amd/opensil/Makefile.mk @@ -4,6 +4,7 @@ subdirs-y += mpio +ramstage-y += acpi.c ramstage-y += ramstage.c endif diff --git a/src/drivers/amd/opensil/acpi.c b/src/drivers/amd/opensil/acpi.c new file mode 100644 index 0000000..042ee67 --- /dev/null +++ b/src/drivers/amd/opensil/acpi.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpi.h> +#include <vendorcode/amd/opensil/opensil.h> + +#include "opensil.h" + +void amd_opensil_fill_fadt_io_ports(acpi_fadt_t *fadt) +{ + opensil_fill_fadt(fadt); +} + +unsigned long acpi_add_opensil_tables(unsigned long current, acpi_rsdp_t *rsdp) +{ + return add_opensil_acpi_table(current, rsdp); +} diff --git a/src/drivers/amd/opensil/opensil.h b/src/drivers/amd/opensil/opensil.h index 0046876..f2bcd6b 100644 --- a/src/drivers/amd/opensil/opensil.h +++ b/src/drivers/amd/opensil/opensil.h @@ -3,9 +3,13 @@ #ifndef OPENSIL_DRIVER_H #define OPENSIL_DRIVER_H +#include <acpi/acpi.h> + /* Set up openSIL env and call TP1 */ void amd_opensil_silicon_init(void); /* Set global and per-device MPIO configurations */ void configure_mpio(void); +/* Fill in FADT from openSIL */ +void amd_opensil_fill_fadt_io_ports(acpi_fadt_t *fadt); #endif /* OPENSIL_DRIVER_H */ diff --git a/src/soc/amd/genoa_poc/acpi.c b/src/soc/amd/genoa_poc/acpi.c index 9b8011d..9091050 100644 --- a/src/soc/amd/genoa_poc/acpi.c +++ b/src/soc/amd/genoa_poc/acpi.c @@ -8,12 +8,12 @@ #include <amdblocks/cpu.h> #include <arch/ioapic.h> #include <device/device.h> -#include <vendorcode/amd/opensil/opensil.h> +#include <drivers/amd/opensil/opensil.h> void acpi_fill_fadt(acpi_fadt_t *fadt) { /* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */ - opensil_fill_fadt_io_ports(fadt); + amd_opensil_fill_fadt_io_ports(fadt); fadt->pm1_evt_len = 4; /* 32 bits */ fadt->pm1_cnt_len = 2; /* 16 bits */ diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index a182dfbb..1475b61 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -17,10 +17,10 @@ #include <console/console.h> #include <cpu/amd/cpuid.h> #include <device/device.h> +#include <drivers/amd/opensil/opensil.h> #include <soc/iomap.h> #include <static.h> #include <types.h> -#include <vendorcode/amd/opensil/opensil.h> #include "chip.h" /* @@ -40,7 +40,7 @@ fadt->gpe0_blk = ACPI_GPE0_BLK; } else { /* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */ - opensil_fill_fadt_io_ports(fadt); + amd_opensil_fill_fadt_io_ports(fadt); } fadt->pm1_evt_len = 4; /* 32 bits */ diff --git a/src/vendorcode/amd/opensil/genoa_poc/acpi.c b/src/vendorcode/amd/opensil/genoa_poc/acpi.c index f539798..fcdf167 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/acpi.c +++ b/src/vendorcode/amd/opensil/genoa_poc/acpi.c @@ -5,9 +5,10 @@ #include <SilCommon.h> #include <xSIM-api.h> #include <FCH/Common/FchCommonCfg.h> + #include "../opensil.h" -void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt) +void opensil_fill_fadt(acpi_fadt_t *fadt) { FCHHWACPI_INPUT_BLK *blk = SilFindStructure(SilId_FchHwAcpiP, 0); @@ -16,3 +17,8 @@ fadt->pm_tmr_blk = blk->AcpiPmTmrBlkAddr; fadt->gpe0_blk = blk->AcpiGpe0BlkAddr; } + +unsigned long add_opensil_acpi_table(unsigned long current, acpi_rsdp_t *rsdp) +{ + return current; +} diff --git a/src/vendorcode/amd/opensil/opensil.h b/src/vendorcode/amd/opensil/opensil.h index 9123125..cd71dfc 100644 --- a/src/vendorcode/amd/opensil/opensil.h +++ b/src/vendorcode/amd/opensil/opensil.h @@ -9,8 +9,9 @@ void SIL_STATUS_report(const char *function, const int status); // Add the memory map to dev, starting at index idx, returns last use idx void add_opensil_memmap(struct device *dev, unsigned long *idx); -// Fill in FADT from openSIL -void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt); + +void opensil_fill_fadt(acpi_fadt_t *fadt); +unsigned long add_opensil_acpi_table(unsigned long current, acpi_rsdp_t *rsdp); void setup_opensil(void); void opensil_xSIM_timepoint_1(void); diff --git a/src/vendorcode/amd/opensil/stub/ramstage.c b/src/vendorcode/amd/opensil/stub/ramstage.c index 0674140..5da6134 100644 --- a/src/vendorcode/amd/opensil/stub/ramstage.c +++ b/src/vendorcode/amd/opensil/stub/ramstage.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <amdblocks/acpi.h> #include <device/device.h> + #include "../opensil.h" void add_opensil_memmap(struct device *dev, unsigned long *idx) @@ -10,12 +10,12 @@ printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); } -void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt) +void opensil_fill_fadt(acpi_fadt_t *fadt) { printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); } -unsigned long acpi_add_opensil_tables(unsigned long current, acpi_rsdp_t *rsdp) +unsigned long add_opensil_acpi_table(unsigned long current, acpi_rsdp_t *rsdp) { printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/85633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9fa4f60164333ec7a268702fa3e94979a1b83594 Gerrit-Change-Number: 85633 Gerrit-PatchSet: 14 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: drivers/amd/opensil/acpi.c: Factor common ACPI calls to openSIL driver
by Felix Held (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin L Roth, Martin Roth, Matt DeVillier, Nick Kochlowski, Varshit Pandya. Felix Held has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85633?usp=email ) Change subject: drivers/amd/opensil/acpi.c: Factor common ACPI calls to openSIL driver ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9fa4f60164333ec7a268702fa3e94979a1b83594 Gerrit-Change-Number: 85633 Gerrit-PatchSet: 13 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 20:17:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver
by Felix Held (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Martin Roth, Nick Kochlowski. Felix Held has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85635?usp=email ) Change subject: drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc79456b0429cdd3d8e3fa5c224799a05add8359 Gerrit-Change-Number: 85635 Gerrit-PatchSet: 13 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 20:14:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel: Allow zero values for PMC GPE0 DW registers
by Dinesh Gehlot (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Eran Mitrani, Eric Lai, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Sean Rhodes, Subrata Banik, Tarun, Werner Zeh. Dinesh Gehlot has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86164?usp=email ) Change subject: soc/intel: Allow zero values for PMC GPE0 DW registers ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Gerrit-Change-Number: 86164 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 20:10:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Karthik Ramasubramanian (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86169?usp=email ) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/86169/comment/4a852fea_c8e84d56?us… : PS3, Line 301: #define ME_HFSTS2_CUR_PM_EVENT_SHIFT 24 > > There are 16 events listed in the doc. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 19:55:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Update UFS disable sequence
by Karthik Ramasubramanian (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86170?usp=email ) Change subject: soc/intel/alderlake/romstage: Update UFS disable sequence ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/86170/comment/c8ddeb29_61574d1d?us… : PS3, Line 202: if ((ps->prev_sleep_state == ACPI_S5 || : cse_match_current_pm_event(PWR_CYCLE_RESET_CMOFF)) && : !mainboard_expects_another_reset()) { > > Sure, I can take it out of the stack. CB:86111 is not strictly required. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97 Gerrit-Change-Number: 86170 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 28 Jan 2025 19:54:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Karthik Ramasubramanian (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Karthik Ramasubramanian, Krishna P Bhat D, Sowmya Aralguppe. Hello Intel coreboot Reviewers, Jérémy Compostella, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86169?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Code-Review+1 by Sowmya Aralguppe, Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... soc/intel/common/block/cse: Add API to match current PM event Introduce an API to read the Converged Security and Management Engine (CSME) host firmware status register to obtain the current Power Management event and compare it with a specified input event. BUG=b:391449110 TEST=Build Brox BIOS image and boot to OS. Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/86169/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Update UFS disable sequence
by Karthik Ramasubramanian (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Hello Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86170?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Verified+1 by build bot (Jenkins) Change subject: soc/intel/alderlake/romstage: Update UFS disable sequence ...................................................................... soc/intel/alderlake/romstage: Update UFS disable sequence Currently after UFS is disabled, if the device is coming out of S5 sleep state then a warm reset is triggered such that PMC samples the UFS function disable bit and disables the UFS controller accordingly. Sometimes during the boot flow, an additional kind of reset gets triggered - Power cycle Reset through CMoff. Hence initiate a warm reset when the host comes out of S5 sleep state or Power cycle Reset through CMoff. BUG=b:391449110 TEST=Build Brox BIOS image and boot to OS. Ensure that when the device switches from normal mode to developer mode an extra warm reset is triggered such that the UFS controller is disabled. Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/86170/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97 Gerrit-Change-Number: 86170 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/skylake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 28 Jan '25

28 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86201?usp=email ) Change subject: soc/intel/skylake: Change the maximum C state to C8 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86201?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f0bf7c4d1ccc04b3ceae8b5f1d492dd6faa77e0 Gerrit-Change-Number: 86201 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Jan 2025 19:41:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/cannonlake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 28 Jan '25

28 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86200?usp=email ) Change subject: soc/intel/cannonlake: Change the maximum C state to C8 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia73e5119041616d4b2e0916b3f0d537c30f8568a Gerrit-Change-Number: 86200 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Jan 2025 19:41:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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