coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: ec/starlabs/merlin: Always use ECRD and ECWR when accessing EC memory
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84734?usp=email ) Change subject: ec/starlabs/merlin: Always use ECRD and ECWR when accessing EC memory ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84734/comment/86d5583b_b40cb091?us… : PS6, Line 12: Also, use local variables to cache reads of the same variable. > nit: maybe add 'within a given ACPI method' to the end since to add context Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0bbb538017cc004bff1989a8017ccfcd1ba9ab5c Gerrit-Change-Number: 84734 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Jan 2025 08:55:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Always use ECRD and ECWR when accessing EC memory
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84734?usp=email to look at the new patch set (#7). Change subject: ec/starlabs/merlin: Always use ECRD and ECWR when accessing EC memory ...................................................................... ec/starlabs/merlin: Always use ECRD and ECWR when accessing EC memory Ensure any reads or writes to the EC memory, are performed with ECRD (Read) and ECWR (Write) as these methods use a mutex. Also, use local variables to cache reads of the same variable within a given ACPI method. This solves: Initialized Arguments for Method [ECRD]: (1 arguments defined for method invocation) Arg0: 00000000967261a4 [RefOf] <Node> Name ECPS RegionField 000000007d4b8073 ACPI Error: Aborting method \_SB.PCI0.LPCB.EC.ECRD due to previous error (AE_BAD_PARAMETER) (20230628/psparse-529) ACPI Error: Aborting method \_SB.PCI0.LPCB.EC.ADP1._PSR due to previous error (AE_BAD_PARAMETER) (20230628/psparse-529) Change-Id: I0bbb538017cc004bff1989a8017ccfcd1ba9ab5c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/ec/starlabs/merlin/acpi/battery.asl M src/ec/starlabs/merlin/acpi/ec.asl M src/ec/starlabs/merlin/acpi/suspend.asl M src/ec/starlabs/merlin/variants/apl/events.asl M src/ec/starlabs/merlin/variants/cezanne/events.asl M src/ec/starlabs/merlin/variants/glk/events.asl M src/ec/starlabs/merlin/variants/glkr/events.asl M src/ec/starlabs/merlin/variants/kbl/events.asl M src/ec/starlabs/merlin/variants/merlin/events.asl 9 files changed, 46 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/84734/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/84734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0bbb538017cc004bff1989a8017ccfcd1ba9ab5c Gerrit-Change-Number: 84734 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Add support for setting the charging speed
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Angel Pons, Matt DeVillier, Maxim Polyakov, Maximilian Brune, Paul Menzel. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84633?usp=email ) Change subject: ec/starlabs/merlin: Add support for setting the charging speed ...................................................................... Patch Set 18: (1 comment) Patchset: PS18: Accidentally push PS17, or intentional? -- To view, visit https://review.coreboot.org/c/coreboot/+/84633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46faa540530c5bd7f5473021561380213158152e Gerrit-Change-Number: 84633 Gerrit-PatchSet: 18 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 08:55:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: {ec,mb}/starlabs: Drop remnants of EC mirror flag
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/85870?usp=email ) Change subject: {ec,mb}/starlabs: Drop remnants of EC mirror flag ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85870?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6eb8c9a6ef8f92e2d92081b8451cef8d7246ff7e Gerrit-Change-Number: 85870 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 08:23:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/rauru: Implement mainboard_get_storage_type
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85879?usp=email ) Change subject: mb/google/rauru: Implement mainboard_get_storage_type ...................................................................... mb/google/rauru: Implement mainboard_get_storage_type Replace existing storage_type with mainboard_get_storage_type TEST=emerge-rauru coreboot Change-Id: I28e0e4294c9a44f1eb17147928ef2860227ff7d3 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/rauru/boardid.c M src/mainboard/google/rauru/mainboard.c M src/mainboard/google/rauru/storage.h 3 files changed, 21 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/85879/1 diff --git a/src/mainboard/google/rauru/boardid.c b/src/mainboard/google/rauru/boardid.c index e3e0979..d9f1585 100644 --- a/src/mainboard/google/rauru/boardid.c +++ b/src/mainboard/google/rauru/boardid.c @@ -66,21 +66,6 @@ return cached_storage_id; } -enum ufs_type storage_type(uint32_t index) -{ - switch (index) { - case 0: - return UFS_40; - case 1: - return UFS_31; - case 2: - return UFS_40_HS; - default: - printk(BIOS_DEBUG, "unsupported type %d\n", index); - } - return UFS_UNKNOWN; -} - uint32_t sku_id(void) { static uint32_t cached_sku_code = BOARD_ID_INIT; diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c index a49caf6..34e4330 100644 --- a/src/mainboard/google/rauru/mainboard.c +++ b/src/mainboard/google/rauru/mainboard.c @@ -12,9 +12,11 @@ #include <soc/msdc.h> #include <soc/pcie.h> #include <soc/spm_common.h> +#include <soc/storage.h> #include <soc/usb.h> #include "gpio.h" +#include "storage.h" #define AFE_SE_SECURE_CON1 (AUDIO_BASE + 0x5634) @@ -46,6 +48,25 @@ gpio_output(GPIO_FP_RST_1V8_S3_L, 1); } +enum mtk_storage_type mainboard_get_storage_type(void) +{ + uint32_t index = storage_id(); + + switch (index) { + case 0: + return STORAGE_UFS_40; + case 1: + return STORAGE_UFS_31; + case 2: + return STORAGE_UFS_40_HS; + case 3: + return STORAGE_NVME; + default: + printk(BIOS_DEBUG, "unsupported type %u\n", index); + } + return STORAGE_UNKNOWN; +} + bool mainboard_needs_pcie_init(void) { return true; diff --git a/src/mainboard/google/rauru/storage.h b/src/mainboard/google/rauru/storage.h index a97bbcb..a1b4d63 100644 --- a/src/mainboard/google/rauru/storage.h +++ b/src/mainboard/google/rauru/storage.h @@ -3,14 +3,6 @@ #ifndef __MAINBOARD_GOOGLE_RAURU_STORAGE_H__ #define __MAINBOARD_GOOGLE_RAURU_STORAGE_H__ -enum ufs_type { - UFS_UNKNOWN = 0, - UFS_31 = 0x310, - UFS_40 = 0x400, - UFS_40_HS = 0x401, -}; - uint32_t storage_id(void); -enum ufs_type storage_type(uint32_t index); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/85879?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28e0e4294c9a44f1eb17147928ef2860227ff7d3 Gerrit-Change-Number: 85879 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Get storage type from mainboard
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85878?usp=email ) Change subject: soc/mediatek/common: Get storage type from mainboard ...................................................................... soc/mediatek/common: Get storage type from mainboard Add common definitions and `mainboard_get_storage_type` API for determining the storage type from mainboard. TEST=emerge-rauru coreboot Change-Id: I5dba2b54b29a701b825fb9bfcac74eb45a563d71 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- A src/soc/mediatek/common/include/soc/storage.h 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/85878/1 diff --git a/src/soc/mediatek/common/include/soc/storage.h b/src/soc/mediatek/common/include/soc/storage.h new file mode 100644 index 0000000..d56ef6c --- /dev/null +++ b/src/soc/mediatek/common/include/soc/storage.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef SOC_MEDIATEK_COMMON_STORAGE_H +#define SOC_MEDIATEK_COMMON_STORAGE_H + +/* Bits [31:28] for base type (e.g. UFS, NvME). */ +#define _BASE_TYPE_SHIFT 28 +#define _BASE_TYPE_MASK (0xf << _BASE_TYPE_SHIFT) +#define _BASE_TYPE(x) ((x & 0xf) << _BASE_TYPE_SHIFT) + +#define _BASE_TYPE_UFS _BASE_TYPE(0x0) +#define _BASE_TYPE_NVME _BASE_TYPE(0x1) + +enum mtk_storage_type { + STORAGE_UNKNOWN = 0, + STORAGE_UFS_31 = _BASE_TYPE_UFS | 0x310, + STORAGE_UFS_40 = _BASE_TYPE_UFS | 0x400, + STORAGE_UFS_40_HS = _BASE_TYPE_UFS | 0x401, + STORAGE_NVME = _BASE_TYPE_NVME, +}; + +enum mtk_storage_type mainboard_get_storage_type(void); + +#endif /* SOC_MEDIATEK_COMMON_STORAGE_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dba2b54b29a701b825fb9bfcac74eb45a563d71 Gerrit-Change-Number: 85878 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Determine PCIe init by storage type
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85828?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Determine PCIe init by storage type ...................................................................... mb/google/rauru: Determine PCIe init by storage type BUG=b:368244423 TEST=emerge-rauru coreboot Change-Id: Iaee7c346f4eaf004437aed3554d9275c9b821ad8 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/rauru/mainboard.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/85828/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85828?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee7c346f4eaf004437aed3554d9275c9b821ad8 Gerrit-Change-Number: 85828 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Werner Zeh (Code Review) 07 Jan '25

07 Jan '25

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email ) Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... soc/intel/common/block/power_limit: Disable RAPL via MSR completely Disabling RAPL via Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS does not turn off RAPL completely (i.d. MMIO & MSR). In the past it was assumed disabling RAPL via MCHBAR is sufficient and the corresponding changes are also reflected in the related MSR (0x610-PACKAGE_POWER_LIMIT). This is not the case for Power Limit 2 (PL2) because Bit[47]-PKG_PWR_LIM_2_EN is still set although PL1 and PL2 were disabled through MCHBAR. Thus Bit[10]-POWER_LIMITATION_STATUS flag can be set in MSR 0x19C (THERM_STATUS) when the power limit of the SKU exceeds. This may lead to a throttling of the domain level frequency. Moreover related parameters within the same MSR (0x610-PACKAGE_POWER_LIMIT) like PKG_PWR_LIM_TIME, PKG_CLMP_LIM, PKG_PWR_LIM have to be cleared as well for both Power Limits (PL1 & PL2). This is due to the fact that these parameters stray in to the system and may effect different system settings. With this commit the PACKAGE_POWER_LIMIT MSR is cleared additionally to the MCHBAR setting when build for ElkhartLake. TEST=Verify MSR(0x610-PACKAGE_POWER_LIMIT) is set to zero during OS runtime except Bit[15]-PKG_PWR_LIM_1_EN (it is known as a bug that this bit will be set to 1 anyway). Moreover using a system stress test tool (e.g. Passmark's BurnInTest) and stressing the system hard should not lead to Bit[10]-POWER_LIMITATION_STATUS flag being set. This is the case when MSR (0x610-PACKAGE_POWER_LIMIT) is not cleared completely and the system is stressed intensively. Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Signed-off-by: Johannes Hahn <johannes-hahn(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85606 Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/power_limit/power_limit.c 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: Mario Scheithauer: Looks good to me, approved Werner Zeh: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index b5fbe89..5f71d2e 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -91,6 +91,14 @@ MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = value & ~(PKG_POWER_LIMIT_EN); value = MCHBAR32(MCH_PKG_POWER_LIMIT_HI); MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = value & ~(PKG_POWER_LIMIT_EN); + /* Elkhartlake SoC does not shadow PKG_POWER_LIMIT MCHBAR settings + to MSR correctly. */ + if (CONFIG(SOC_INTEL_ELKHARTLAKE)) { + msr = rdmsr(MSR_PKG_POWER_LIMIT); + msr.hi = 0; + msr.lo = 0; + wrmsr(MSR_PKG_POWER_LIMIT, msr); + } } else { msr = rdmsr(MSR_PKG_POWER_LIMIT); msr.lo &= ~PKG_POWER_LIMIT_EN; -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 7 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot

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[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Werner Zeh (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Johannes Hahn, Uwe Poeche. Werner Zeh has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email ) Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 6 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 06:56:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Shuo Liu (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Paul Menzel, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 05:57:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit January 2025