coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
745 discussions

[M] Change in coreboot[main]: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters
by Subrata Banik (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Subrata Banik has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85850?usp=email ) Change subject: mb/google/nissa/var/rull: Update 6W and 15W DPTF parameters ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85850?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaee949fa8b2e990efaf6a118bd3b77784ea4340 Gerrit-Change-Number: 85850 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 07 Jan 2025 05:47:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Xeon ICX-SP support
by Shuo Liu (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85845?usp=email ) Change subject: soc/intel/xeon_sp: Add Xeon ICX-SP support ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85845/comment/7d6a06c4_23d3e521?us… : PS3, Line 9: Add support for the 1st Gen 10nm Xeon-SP CPUs. Supported and tested > ICX might be advertised as 3rd gen Xeon-SP, but this term is intentionally not used as CPX is also 3 […] Technically yes but what I'm worried about is many users will refer to public URLs to check the products, e.g., https://www.intel.com/content/www/us/en/ark.html#@PanelLabel595, thus not straightforward to find a match. Back to the previous discussion for SKX/CPX code merge, if we have both concept of ?? nm and ?? gen to co-exist, it would be helpful to be consistent with the meaning of 'gen' as the global generation instead of per 'nm' generation. This is adequate to distinguish CPX (14nm gen3) and ICX (10nm gen3), and as well as others. Your opinion? https://review.coreboot.org/c/coreboot/+/85845/comment/a60b94cd_dc91faa0?us… : PS3, Line 10: are dual socket systems with a LBG PCH. > Yes. Mainboard support will be added as separate commit. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85845?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bb74c0db2c91c87bf623c079f89fd139780160b Gerrit-Change-Number: 85845 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 05:36:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_common.c
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

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[XS] Change in coreboot[main]: soc/mediatek/common/dp: Initialize dptx_misc
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85877?usp=email ) Change subject: soc/mediatek/common/dp: Initialize dptx_misc ...................................................................... soc/mediatek/common/dp: Initialize dptx_misc Initialize dptx_misc to prevent unexpected value set to REG_3034_DP_ENCODER0_P0. TEST=emerge-geralt coreboot && emerge-rauru coreboot Change-Id: I80e0f83f238d9b4c1ed0e1d1b219f4fb89a6cd22 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/dp/dptx_common.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/85877/1 diff --git a/src/soc/mediatek/common/dp/dptx_common.c b/src/soc/mediatek/common/dp/dptx_common.c index d835f57..0d078cd 100644 --- a/src/soc/mediatek/common/dp/dptx_common.c +++ b/src/soc/mediatek/common/dp/dptx_common.c @@ -333,7 +333,7 @@ static void dptx_set_misc(struct mtk_dp *mtk_dp) { u8 format, depth; - union misc_t dptx_misc; + union misc_t dptx_misc = { .cmisc = {0} }; format = mtk_dp->info.format; depth = mtk_dp->info.depth; -- To view, visit https://review.coreboot.org/c/coreboot/+/85877?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80e0f83f238d9b4c1ed0e1d1b219f4fb89a6cd22 Gerrit-Change-Number: 85877 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Delay 0.5ms after enabling PMIF SPMI SW interface
by Jarried Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85799?usp=email ) Change subject: soc/mediatek/mt8196: Delay 0.5ms after enabling PMIF SPMI SW interface ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85799/comment/d53ac222_35808cfe?us… : PS4, Line 7: pmif_spmi_enable_swinf > Modify the commit subject to `Delay 0.5ms after enabling PMIF SPMI SW interface`. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4 Gerrit-Change-Number: 85799 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 05:25:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Delay 0.5ms after enabling PMIF SPMI SW interface
by Jarried Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85799?usp=email to look at the new patch set (#5). Change subject: soc/mediatek/mt8196: Delay 0.5ms after enabling PMIF SPMI SW interface ...................................................................... soc/mediatek/mt8196: Delay 0.5ms after enabling PMIF SPMI SW interface The initialization process of SPMI requires a certain amount of time (0.5ms) to ensure all components are correctly configured and synchronized. Otherwise, if the SPMI calibration fails, it will result in the non-serial firmware failing to boot. TEST=Build pass, non-serial firmware boot ok. BUG=b:341054056 Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/pmif_spmi.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/85799/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4 Gerrit-Change-Number: 85799 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_common.c
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85860?usp=email ) Change subject: soc/mediatek/common/dp: Move common functions to dptx_common.c ...................................................................... Patch Set 5: (11 comments) File src/soc/mediatek/common/dp/dptx.c: https://review.coreboot.org/c/coreboot/+/85860/comment/f5daafad_e021790b?us… : PS3, Line 15: dptx_link_train_clock_recovery_delay > Looks the same as mt8196's `drm_dp_link_train_clock_recovery_delay`, except that in the edge case (` […] Done https://review.coreboot.org/c/coreboot/+/85860/comment/94e0386f_fe90bd40?us… : PS3, Line 32: dptx_link_train_channel_eq_delay > Same here. Done https://review.coreboot.org/c/coreboot/+/85860/comment/0ca98c2b_b5812c9c?us… : PS3, Line 49: dptx_channel_eq_ok > Looks the same as mt8196's `drm_dp_channel_eq_ok`. Done https://review.coreboot.org/c/coreboot/+/85860/comment/eb990f6b_beee6e3a?us… : PS3, Line 425: dptx_set_trainingstart > I think it's also possible to share this with mt8196. The differences are: […] It is difficult for me to realize whole flow within one or two days (plus verification on mt8188/mt8196). Current target is to mitigate the upstream progress of the MT8196 eDP driver. I think there are still a lot of works on DPTX_HAL refactoring. I would like to the keep current approach and refactor this function when I have the spare time. https://review.coreboot.org/c/coreboot/+/85860/comment/c1dd2bb8_98c3e598?us… : PS3, Line 536: static void dptx_video_enable(struct mtk_dp *mtk_dp, bool enable) > Looks the same as mt8196. Done https://review.coreboot.org/c/coreboot/+/85860/comment/faafadfa_7f81d549?us… : PS3, Line 559: dptx_video_config > Can this be shared with mt8196? Done File src/soc/mediatek/common/dp/include/soc/dptx_common.h: https://review.coreboot.org/c/coreboot/+/85860/comment/2559e946_5916d5e1?us… : PS3, Line 50: DP_LANE_CHANNEL_EQ_DONE | \ > align Done https://review.coreboot.org/c/coreboot/+/85860/comment/0772b7d5_5048d33d?us… : PS3, Line 107: > tabs Done https://review.coreboot.org/c/coreboot/+/85860/comment/f6c64965_75508d5f?us… : PS3, Line 214: dptx_get_lane_status > If `dptx_channel_eq_ok` is shared with mt8196, then this can be static. Done https://review.coreboot.org/c/coreboot/+/85860/comment/7f522990_e580e41c?us… : PS3, Line 217: bool dptx_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, > `dptx_auxwrite_bytes` and `dptx_auxread_bytes` can be static functions. Done https://review.coreboot.org/c/coreboot/+/85860/comment/7321a3df_2e500db1?us… : PS3, Line 221: void dptx_videomute(struct mtk_dp *mtk_dp, bool enable); : void dptx_set_dptxout(struct mtk_dp *mtk_dp); > These 2 functions can be static if `dptx_video_enable` is shared with mt8196. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5074feee9efa62f27c118eaf7adb25875ba4c16 Gerrit-Change-Number: 85860 Gerrit-PatchSet: 5 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 04:15:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek: Rename DP related header files
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85859?usp=email to look at the new patch set (#5). Change subject: soc/mediatek: Rename DP related header files ...................................................................... soc/mediatek: Rename DP related header files Add `_common` postfix to the header files located in common/dp/include/soc/. The patch helps MT8196 managing its own DP register difition and macros in its include/soc folder. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-cherry coreboot Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- R src/soc/mediatek/common/dp/include/soc/dp_intf_common.h R src/soc/mediatek/common/dp/include/soc/dptx_common.h R src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h R src/soc/mediatek/common/dp/include/soc/dptx_reg_common.h A src/soc/mediatek/mt8186/include/soc/dptx.h A src/soc/mediatek/mt8188/include/soc/dp_intf.h A src/soc/mediatek/mt8188/include/soc/dptx.h A src/soc/mediatek/mt8188/include/soc/dptx_hal.h A src/soc/mediatek/mt8188/include/soc/dptx_reg.h A src/soc/mediatek/mt8195/include/soc/dp_intf.h A src/soc/mediatek/mt8195/include/soc/dptx.h A src/soc/mediatek/mt8195/include/soc/dptx_hal.h A src/soc/mediatek/mt8195/include/soc/dptx_reg.h 13 files changed, 84 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85859/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ebfa2aa0dde759275c9826c605f3285c777f58d Gerrit-Change-Number: 85859 Gerrit-PatchSet: 5 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>

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[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_common.c
by Yidi Lin (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85860?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/common/dp: Move common functions to dptx_common.c ...................................................................... soc/mediatek/common/dp: Move common functions to dptx_common.c Move the functions that can be shared with MT8196 to dptx_common.c. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-cherry coreboot Change-Id: Ic5074feee9efa62f27c118eaf7adb25875ba4c16 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/dp/dptx.c A src/soc/mediatek/common/dp/dptx_common.c M src/soc/mediatek/common/dp/include/soc/dptx_common.h M src/soc/mediatek/mt8188/Makefile.mk M src/soc/mediatek/mt8195/Makefile.mk 5 files changed, 645 insertions(+), 617 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85860/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5074feee9efa62f27c118eaf7adb25875ba4c16 Gerrit-Change-Number: 85860 Gerrit-PatchSet: 5 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21
by Wonkyu Kim (Code Review) 07 Jan '25

07 Jan '25

Wonkyu Kim has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85781?usp=email ) Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 21 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Gerrit-Change-Number: 85781 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 04:02:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit January 2025