coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/intel/tigerlake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 28 Jan '25

28 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86199?usp=email ) Change subject: soc/intel/tigerlake: Change the maximum C state to C8 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fe0f5a8f9b52a44d1951037d74df4a244ba602e Gerrit-Change-Number: 86199 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 28 Jan 2025 19:41:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85690?usp=email ) Change subject: soc/intel/meteorlake: Change the maximum C state to C8 ...................................................................... Patch Set 5: (1 comment) Patchset: PS4: > The only board left I can rely experiment with is Panther Lake. […] Patches pushed for the boards I can test - will leave the others alone -- To view, visit https://review.coreboot.org/c/coreboot/+/85690?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7de1220b0e26aa9dcca71e58caf17a0f168e7b24 Gerrit-Change-Number: 85690 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 19:41:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB
by Jon Murphy (Code Review) 28 Jan '25

28 Jan '25

Jon Murphy has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86202?usp=email ) Change subject: mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB ...................................................................... mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB The google/fatcat board's flash layout was modified to increase the size of RW_SECTION_A and RW_SECTION_B by 1MB each (from 7MB to 8MB). The RW_UNUSED region size was reduced to accommodate the increased RW_SECTION sizes. This change provides additional space in the RW slots to accommodate growth in the payload (depthcharge). TEST=Built and flashed the image. Verified that both RW_SECTION_A and RW_SECTION_B are populated with the correct firmware components and that the system boots successfully. Change-Id: Ie489d53cef00ddc2dc6beef891f870c6bc0562a8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86202 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/fatcat/chromeos.fmd 1 file changed, 11 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Jayvik Desai: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Jon Murphy: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/chromeos.fmd b/src/mainboard/google/fatcat/chromeos.fmd index ca29bbc..0ff14e3 100644 --- a/src/mainboard/google/fatcat/chromeos.fmd +++ b/src/mainboard/google/fatcat/chromeos.fmd @@ -4,11 +4,20 @@ SI_ME } SI_BIOS 24M { - RW_SECTION_A 7M { + RW_SECTION_A 8M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 } + # This section starts at the 16M boundary in SPI flash. + # PTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 8M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } RW_MISC 1M { UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K @@ -22,17 +31,8 @@ RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 24K } - # This section starts at the 16M boundary in SPI flash. - # PTL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 7M { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - } RW_LEGACY(CBFS) 1M - RW_UNUSED 4M + RW_UNUSED 2M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 4M { -- To view, visit https://review.coreboot.org/c/coreboot/+/86202?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie489d53cef00ddc2dc6beef891f870c6bc0562a8 Gerrit-Change-Number: 86202 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB
by Karthik Ramasubramanian (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Kapil Porwal, Pranava Y N, Raul Rangel, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86202?usp=email ) Change subject: mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86202?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie489d53cef00ddc2dc6beef891f870c6bc0562a8 Gerrit-Change-Number: 86202 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 19:41:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB
by Jon Murphy (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Kapil Porwal, Karthik Ramasubramanian, Pranava Y N, Raul Rangel, Subrata Banik. Jon Murphy has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86202?usp=email ) Change subject: mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86202?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie489d53cef00ddc2dc6beef891f870c6bc0562a8 Gerrit-Change-Number: 86202 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 19:40:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Update UFS disable sequence
by Subrata Banik (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86170?usp=email ) Change subject: soc/intel/alderlake/romstage: Update UFS disable sequence ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/86170/comment/3ccc2203_8070d682?us… : PS3, Line 202: if ((ps->prev_sleep_state == ACPI_S5 || : cse_match_current_pm_event(PWR_CYCLE_RESET_CMOFF)) && : !mainboard_expects_another_reset()) { > Sure, I can take it out of the stack. CB:86111 is not strictly required. perfect. -- To view, visit https://review.coreboot.org/c/coreboot/+/86170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97 Gerrit-Change-Number: 86170 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 18:34:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Subrata Banik (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Karthik Ramasubramanian, Krishna P Bhat D. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86169?usp=email ) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/86169/comment/3f225a01_5b487954?us… : PS3, Line 301: #define ME_HFSTS2_CUR_PM_EVENT_SHIFT 24 > There are 16 events listed in the doc. For now, we are hitting only this event that is equivalent to S5. I can update the API as `bool cse_match_host_cold_reset(void)` to check for an equivalent of S5 reset and include `Power cycle reset through CMOFF` event for now. We can internally update the API to check for other events as we learn more from Intel. sounds like a step wise approach and i fully agree to this. we should land initial CLs and seek feedback from Intel to map the S5 equivalent reset types from CSE reset types to ensure we are not just limited to `Power cycle reset through CMOFF` alone in future. -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 18:33:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB
by Jayvik Desai (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Jayvik Desai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86202?usp=email ) Change subject: mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86202?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie489d53cef00ddc2dc6beef891f870c6bc0562a8 Gerrit-Change-Number: 86202 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 17:57:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB
by Subrata Banik (Code Review) 28 Jan '25

28 Jan '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86202?usp=email ) Change subject: mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB ...................................................................... mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB The google/fatcat board's flash layout was modified to increase the size of RW_SECTION_A and RW_SECTION_B by 1MB each (from 7MB to 8MB). The RW_UNUSED region size was reduced to accommodate the increased RW_SECTION sizes. This change provides additional space in the RW slots to accommodate growth in the payload (depthcharge). TEST=Built and flashed the image. Verified that both RW_SECTION_A and RW_SECTION_B are populated with the correct firmware components and that the system boots successfully. Change-Id: Ie489d53cef00ddc2dc6beef891f870c6bc0562a8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/chromeos.fmd 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/86202/1 diff --git a/src/mainboard/google/fatcat/chromeos.fmd b/src/mainboard/google/fatcat/chromeos.fmd index ca29bbc..0ff14e3 100644 --- a/src/mainboard/google/fatcat/chromeos.fmd +++ b/src/mainboard/google/fatcat/chromeos.fmd @@ -4,11 +4,20 @@ SI_ME } SI_BIOS 24M { - RW_SECTION_A 7M { + RW_SECTION_A 8M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 } + # This section starts at the 16M boundary in SPI flash. + # PTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 8M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } RW_MISC 1M { UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K @@ -22,17 +31,8 @@ RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 24K } - # This section starts at the 16M boundary in SPI flash. - # PTL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 7M { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - } RW_LEGACY(CBFS) 1M - RW_UNUSED 4M + RW_UNUSED 2M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 4M { -- To view, visit https://review.coreboot.org/c/coreboot/+/86202?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie489d53cef00ddc2dc6beef891f870c6bc0562a8 Gerrit-Change-Number: 86202 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/starlabs/*: Correct the enable GPIO for WLAN
by Matt DeVillier (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86184?usp=email ) Change subject: mb/starlabs/*: Correct the enable GPIO for WLAN ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12797875acacc231e155ab4e427a950a3b1b9703 Gerrit-Change-Number: 86184 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 28 Jan 2025 17:50:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit January 2025