coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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3270 discussions

[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Dinesh Gehlot (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Karthik Ramasubramanian, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik. Dinesh Gehlot has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86169?usp=email ) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/86169/comment/38f56cd6_2be1d69f?us… : PS4, Line 315: switch (event) { : case PWR_CYCLE_RESET_CMOFF: : return true; : default: : return false; > We will include more events in the CSE cold boot event in the coming days - after consultation with […] got it, thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 21:15:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Karthik Ramasubramanian (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jérémy Compostella, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86169?usp=email ) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/86169/comment/9580315a_be6416e7?us… : PS4, Line 315: switch (event) { : case PWR_CYCLE_RESET_CMOFF: : return true; : default: : return false; > I believe the function is solely for checking a CSE cold boot event. […] We will include more events in the CSE cold boot event in the coming days - after consultation with Intel. We are starting with just one event for now to address the problem in Brox. That is why this switch case approach. -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 21:08:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Update UFS disable sequence
by Dinesh Gehlot (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Dinesh Gehlot has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86170?usp=email ) Change subject: soc/intel/alderlake/romstage: Update UFS disable sequence ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97 Gerrit-Change-Number: 86170 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 21:05:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Add API to match current PM event
by Dinesh Gehlot (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Karthik Ramasubramanian, Krishna P Bhat D, Sowmya Aralguppe, Subrata Banik. Dinesh Gehlot has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86169?usp=email ) Change subject: soc/intel/common/block/cse: Add API to match current PM event ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/86169/comment/8b7ea262_7289e1c7?us… : PS4, Line 315: switch (event) { : case PWR_CYCLE_RESET_CMOFF: : return true; : default: : return false; I believe the function is solely for checking a CSE cold boot event. Should we simply return (event == PWR_CYCLE_RESET_CMOFF)? -- To view, visit https://review.coreboot.org/c/coreboot/+/86169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad Gerrit-Change-Number: 86169 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 21:04:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver
by Felix Held (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Nick Kochlowski, Varshit Pandya. Felix Held has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85634?usp=email ) Change subject: drivers/amd/opensil/memmap.c: Factor out common memmap code to driver ...................................................................... Patch Set 15: (3 comments) Patchset: PS15: only had a very brief look File src/drivers/amd/opensil/memmap.c: https://review.coreboot.org/c/coreboot/+/85634/comment/cebda5c3_287c362d?us… : PS15, Line 16: } HOLE_INFO; please add a comment to this struct that it matches and needs to match openSIL's MEMORY_HOLE_TYPES struct https://review.coreboot.org/c/coreboot/+/85634/comment/208a1e3b_a293c933?us… : PS15, Line 18: // This assumes holes are allocated since this code is moved from vendorcode into the regular coreboot code base, it would be better to update the comment style to the one used in coreboot: /* */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80b9bdd7fd633c7b12d695ced5d4b9b518570d80 Gerrit-Change-Number: 85634 Gerrit-PatchSet: 15 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 20:43:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Change the maximum C state to C8
by Jérémy Compostella (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Kapil Porwal, Sean Rhodes, Subrata Banik, Tarun. Jérémy Compostella has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85690?usp=email ) Change subject: soc/intel/meteorlake: Change the maximum C state to C8 ...................................................................... Patch Set 5: (1 comment) Patchset: PS4: > No, but only reaching C6 - same for TGL Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85690?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7de1220b0e26aa9dcca71e58caf17a0f168e7b24 Gerrit-Change-Number: 85690 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 20:20:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/skylake: Change the maximum C state to C8
by Jérémy Compostella (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Sean Rhodes. Jérémy Compostella has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86201?usp=email ) Change subject: soc/intel/skylake: Change the maximum C state to C8 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86201?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f0bf7c4d1ccc04b3ceae8b5f1d492dd6faa77e0 Gerrit-Change-Number: 86201 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 20:20:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/cannonlake: Change the maximum C state to C8
by Jérémy Compostella (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Sean Rhodes. Jérémy Compostella has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86200?usp=email ) Change subject: soc/intel/cannonlake: Change the maximum C state to C8 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia73e5119041616d4b2e0916b3f0d537c30f8568a Gerrit-Change-Number: 86200 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Comment-Date: Tue, 28 Jan 2025 20:20:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/tigerlake: Change the maximum C state to C8
by Jérémy Compostella (Code Review) 28 Jan '25

28 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Nick Vaccaro, Sean Rhodes, Subrata Banik. Jérémy Compostella has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86199?usp=email ) Change subject: soc/intel/tigerlake: Change the maximum C state to C8 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fe0f5a8f9b52a44d1951037d74df4a244ba602e Gerrit-Change-Number: 86199 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 28 Jan 2025 20:19:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver
by Felix Held (Code Review) 28 Jan '25

28 Jan '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85635?usp=email ) Change subject: drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver ...................................................................... drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver Define the generic cbmem_top_chipset() in the driver code, which will invoke a SoC-specific vendorcode openSIL call to retrieve the low usable DRAM address. Change-Id: Ibc79456b0429cdd3d8e3fa5c224799a05add8359 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85635 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/amd/opensil/Makefile.mk A src/drivers/amd/opensil/romstage.c M src/vendorcode/amd/opensil/genoa_poc/romstage.c M src/vendorcode/amd/opensil/opensil.h M src/vendorcode/amd/opensil/stub/romstage.c 5 files changed, 38 insertions(+), 24 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/amd/opensil/Makefile.mk b/src/drivers/amd/opensil/Makefile.mk index 82e025b..9837718 100644 --- a/src/drivers/amd/opensil/Makefile.mk +++ b/src/drivers/amd/opensil/Makefile.mk @@ -4,6 +4,8 @@ subdirs-y += mpio +romstage-y += romstage.c + ramstage-y += acpi.c ramstage-y += ramstage.c diff --git a/src/drivers/amd/opensil/romstage.c b/src/drivers/amd/opensil/romstage.c new file mode 100644 index 0000000..b9ef239 --- /dev/null +++ b/src/drivers/amd/opensil/romstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <console/console.h> +#include <cpu/amd/mtrr.h> +#include <vendorcode/amd/opensil/opensil.h> + +uintptr_t cbmem_top_chipset(void) +{ + printk(BIOS_DEBUG, "TOM1: 0x%x\n", get_top_of_mem_below_4gb()); + uintptr_t top_mem = opensil_get_low_usable_dram_address(); + + /* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size to + account for potentially ill aligned TOP_MEM. */ + if (CONFIG_SMM_TSEG_SIZE) { + top_mem -= CONFIG_SMM_TSEG_SIZE; + top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE); + } + + return top_mem; +} diff --git a/src/vendorcode/amd/opensil/genoa_poc/romstage.c b/src/vendorcode/amd/opensil/genoa_poc/romstage.c index e55ed1b..5b871f6 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/romstage.c +++ b/src/vendorcode/amd/opensil/genoa_poc/romstage.c @@ -1,23 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbmem.h> #include <console/console.h> #include "opensil_console.h" #include <xSIM-api.h> #include <xPRF-api.h> -uintptr_t cbmem_top_chipset(void) +#include "../opensil.h" + +uintptr_t opensil_get_low_usable_dram_address(void) { SilDebugSetup(HostDebugService); - uintptr_t top_mem = xPrfGetLowUsableDramAddress(0); - printk(BIOS_DEBUG, "xPrfGetLowUsableDramAddress: 0x%lx\n", top_mem); + uintptr_t low_usable_dram_addr = xPrfGetLowUsableDramAddress(0); + printk(BIOS_DEBUG, "xPrfGetLowUsableDramAddress: 0x%lx\n", low_usable_dram_addr); - /* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size so - account for potentially ill aligned TOP_MEM. */ - if (CONFIG_SMM_TSEG_SIZE) { - top_mem -= CONFIG_SMM_TSEG_SIZE; - top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE); - } - - return top_mem; + return low_usable_dram_addr; } diff --git a/src/vendorcode/amd/opensil/opensil.h b/src/vendorcode/amd/opensil/opensil.h index cd71dfc..c84a180 100644 --- a/src/vendorcode/amd/opensil/opensil.h +++ b/src/vendorcode/amd/opensil/opensil.h @@ -5,6 +5,7 @@ #include <acpi/acpi.h> #include <device/device.h> +#include <types.h> void SIL_STATUS_report(const char *function, const int status); // Add the memory map to dev, starting at index idx, returns last use idx @@ -13,6 +14,8 @@ void opensil_fill_fadt(acpi_fadt_t *fadt); unsigned long add_opensil_acpi_table(unsigned long current, acpi_rsdp_t *rsdp); +uintptr_t opensil_get_low_usable_dram_address(void); + void setup_opensil(void); void opensil_xSIM_timepoint_1(void); void opensil_xSIM_timepoint_2(void); diff --git a/src/vendorcode/amd/opensil/stub/romstage.c b/src/vendorcode/amd/opensil/stub/romstage.c index 36dff95..989843f 100644 --- a/src/vendorcode/amd/opensil/stub/romstage.c +++ b/src/vendorcode/amd/opensil/stub/romstage.c @@ -1,23 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <cbmem.h> #include <console/console.h> #include <inttypes.h> -uintptr_t cbmem_top_chipset(void) +#include "../opensil.h" + +uintptr_t opensil_get_low_usable_dram_address(void) { /* Since the stub doesn't have the openSIL function xPrfGetLowUsableDramAddress to call, we just use 0xc0000000 here which should be a usable value in most cases */ - uintptr_t top_mem = 0xc0000000; + uintptr_t low_usable_dram_addr = 0xc0000000; - printk(BIOS_NOTICE, "openSIL stub: %s retuns %" PRIxPTR "\n", __func__, top_mem); + printk(BIOS_NOTICE, "openSIL stub: %s retuns %" PRIxPTR "\n", __func__, low_usable_dram_addr); - /* The TSEG MSR has an 8M granularity. TSEG also needs to be aligned to its size so - account for potentially ill aligned TOP_MEM. */ - if (CONFIG_SMM_TSEG_SIZE) { - top_mem -= CONFIG_SMM_TSEG_SIZE; - top_mem = ALIGN_DOWN(top_mem, CONFIG_SMM_TSEG_SIZE); - } - - return top_mem; + return low_usable_dram_addr; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc79456b0429cdd3d8e3fa5c224799a05add8359 Gerrit-Change-Number: 85635 Gerrit-PatchSet: 14 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

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