coreboot-gerrit January 2025

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[L] Change in coreboot[main]: tree: Use true false for PcieRpLtrEnable[]
by Sean Rhodes (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Alexander Couzens, Angel Pons, Christian Walter, Elyes Haouas, Frans Hendriks, Intel coreboot Reviewers, Jeremy Soller, Jonathon Hall, Matt DeVillier, Maxim Polyakov, Michael Niewöhner, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Subrata Banik, Tim Crawford. Sean Rhodes has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86193?usp=email ) Change subject: tree: Use true false for PcieRpLtrEnable[] ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b557683b7897487dedfef0bf77e60b0dab9cbcf Gerrit-Change-Number: 86193 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 29 Jan 2025 11:47:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports
by Sean Rhodes (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Michał Żygowski, Nick Vaccaro, Subrata Banik. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84620?usp=email ) Change subject: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... Patch Set 6: (1 comment) Patchset: PS4: > Error: […] ping 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/84620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e36cee37716d3b003b9ce250f28fdf5581a15bc Gerrit-Change-Number: 84620 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 29 Jan 2025 11:47:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/{adl_n,mtl}: Don't configure GPE routes
by Sean Rhodes (Code Review) 29 Jan '25

29 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86165?usp=email ) Change subject: mb/starlabs/starbook/{adl_n,mtl}: Don't configure GPE routes ...................................................................... mb/starlabs/starbook/{adl_n,mtl}: Don't configure GPE routes This are not used or needed, so remove the configuration for them. Change-Id: Id422f953dae3157a4ecc61421d246ce1d20019a0 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86165 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb M src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb 2 files changed, 0 insertions(+), 8 deletions(-) Approvals: Jérémy Compostella: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb index af9e30e..d84c243 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb @@ -26,10 +26,6 @@ register "pch_slp_sus_min_assertion_width" = "3" # 500ms register "pch_slp_a_min_assertion_width" = "3" # 2s - register "pmc_gpe0_dw0" = "PMC_GPP_F" - register "pmc_gpe0_dw1" = "PMC_GPP_C" - register "pmc_gpe0_dw2" = "PMC_GPP_E" - # Device Tree device domain 0 on device ref igpu on diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb index c02b642..f53b549 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb @@ -18,10 +18,6 @@ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, }" - register "pmc_gpe0_dw0" = "PMC_GPP_F" - register "pmc_gpe0_dw1" = "PMC_GPP_C" - register "pmc_gpe0_dw2" = "PMC_GPP_E" - # Device Tree device domain 0 on device ref igpu on -- To view, visit https://review.coreboot.org/c/coreboot/+/86165?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id422f953dae3157a4ecc61421d246ce1d20019a0 Gerrit-Change-Number: 86165 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/common/pmc: Change GPE DW duplicate message to warning
by Sean Rhodes (Code Review) 29 Jan '25

29 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86174?usp=email ) Change subject: soc/intel/common/pmc: Change GPE DW duplicate message to warning ...................................................................... soc/intel/common/pmc: Change GPE DW duplicate message to warning The message printed when duplicate GPE DW register values are detected was previously logged at the INFO level. This commit changes the log level to WARNING, as duplicate DW values indicate a potential misconfiguration and warrant closer attention. While the system falls back to the default GPE route (as per MISCCFG register), this situation should be investigated to ensure correct platform configuration. This change ensures that developers are more clearly notified of potential GPE routing issues. TEST=Built and booted on a platform using PMC GPE routing. Verified that the message is printed at the WARNING level when duplicate DW values are present. Change-Id: I7804ddfa6e067014e034364bd8efbf6efe746cd7 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86174 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Jérémy Compostella: Looks good to me, approved Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 18a527a..8c48e88 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -657,7 +657,8 @@ * are different, and if they aren't use the reset values. */ if (dw0 == dw1 || dw1 == dw2 || dw0 == dw2) { - printk(BIOS_INFO, "PMC: Using default GPE route.\n"); + printk(BIOS_WARNING, "PMC: Duplicate GPE DW register values detected; " + "using default GPE route from MISCCFG register\n"); gpio_cfg = read32p(pmc_bar + GPIO_GPE_CFG); dw0 = (gpio_cfg >> GPE0_DW_SHIFT(0)) & GPE0_DWX_MASK; -- To view, visit https://review.coreboot.org/c/coreboot/+/86174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7804ddfa6e067014e034364bd8efbf6efe746cd7 Gerrit-Change-Number: 86174 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/common/pmc: Fix duplicate GPE DW register check
by Sean Rhodes (Code Review) 29 Jan '25

29 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86173?usp=email ) Change subject: soc/intel/common/pmc: Fix duplicate GPE DW register check ...................................................................... soc/intel/common/pmc: Fix duplicate GPE DW register check The `pmc_gpe_init` function's check for duplicate GPE DW register values was incomplete. It only checked for duplicates between DW0 and DW1, and DW1 and DW2, but failed to check if DW0 and DW2 were the same. This could lead to incorrect GPE routing if DW0 and DW2 happened to have the same value, even if DW1 was different. This commit corrects the check to ensure that all three DW registers (DW0, DW1, and DW2) are compared against each other. If any two registers have the same value, a message is printed indicating that the default GPE route will be used. Change-Id: I0a52e6aeee619fbc2f712c9c976b067d080ca591 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86173 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Jérémy Compostella: Looks good to me, approved diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 0fadd6e..18a527a 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -656,7 +656,7 @@ * Route the GPIOs to the GPE0 block. Determine that all values * are different, and if they aren't use the reset values. */ - if (dw0 == dw1 || dw1 == dw2) { + if (dw0 == dw1 || dw1 == dw2 || dw0 == dw2) { printk(BIOS_INFO, "PMC: Using default GPE route.\n"); gpio_cfg = read32p(pmc_bar + GPIO_GPE_CFG); -- To view, visit https://review.coreboot.org/c/coreboot/+/86173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a52e6aeee619fbc2f712c9c976b067d080ca591 Gerrit-Change-Number: 86173 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel: Allow zero values for PMC GPE0 DW registers
by Sean Rhodes (Code Review) 29 Jan '25

29 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86164?usp=email ) Change subject: soc/intel: Allow zero values for PMC GPE0 DW registers ...................................................................... soc/intel: Allow zero values for PMC GPE0 DW registers The `pmc_gpe0_different_values` function previously asserted if any two of the GPE0 DW registers (DW0, DW1, DW2) had the same value, as introduced in commit 640a41f3ee938b794b14 ("soc/intel: Assert if `pmc_/gpe0_dwX` values are not unique"). This prevented platforms from configuring GPE routing via PMC as per default register (MISCCFG) value. This commit modifies the check to allow all DW registers to be zero. This enables platforms that rely on MISCCFG register for PMC-controlled GPE routing to boot without triggering the assertion. The change was verified by testing the following scenarios: - All DWs zero: The system boots using the default GPE route. No assertion occurs. - Duplicate DWs (e.g., DW0=1, DW1=2, DW2=2): The existing assertion is triggered as expected. - Unique DWs (e.g., DW0=1, DW1=2, DW2=3): No errors occur. TEST=Built and booted normally. No assertion failure observed. Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86164 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/pantherlake/pmutil.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/pmutil.c 9 files changed, 63 insertions(+), 18 deletions(-) Approvals: Dinesh Gehlot: Looks good to me, approved Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 60d6e10..c459100 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -156,11 +156,16 @@ static void pmc_gpe0_different_values(const struct soc_intel_alderlake_config *config) { - bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && + bool all_zero = (config->pmc_gpe0_dw0 == 0) && + (config->pmc_gpe0_dw1 == 0) && + (config->pmc_gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ + bool all_different = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); - assert(result); + assert(all_different || all_zero); } void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 5366ca8..ddc5647 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -140,11 +140,16 @@ static void gpe0_different_values(const struct soc_intel_apollolake_config *config) { - bool result = (config->gpe0_dw1 != config->gpe0_dw2) && + bool all_zero = (config->gpe0_dw1 == 0) && + (config->gpe0_dw2 == 0) && + (config->gpe0_dw3 == 0); + + /* Check if all values are different AND not all zero */ + bool all_different = (config->gpe0_dw1 != config->gpe0_dw2) && (config->gpe0_dw1 != config->gpe0_dw3) && (config->gpe0_dw2 != config->gpe0_dw3); - assert(result); + assert(all_different || all_zero); } void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 63eed16..f7d9345 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -150,11 +150,16 @@ static void gpe0_different_values(const struct soc_intel_cannonlake_config *config) { - bool result = (config->gpe0_dw0 != config->gpe0_dw1) && + bool all_zero = (config->gpe0_dw0 == 0) && + (config->gpe0_dw1 == 0) && + (config->gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ + bool all_different = (config->gpe0_dw0 != config->gpe0_dw1) && (config->gpe0_dw0 != config->gpe0_dw2) && (config->gpe0_dw1 != config->gpe0_dw2); - assert(result); + assert(all_different || all_zero); } void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index a862bdd..72f9bd6 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -149,11 +149,16 @@ static void pmc_gpe0_different_values(const struct soc_intel_elkhartlake_config *config) { - bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && + bool all_zero = (config->pmc_gpe0_dw0 == 0) && + (config->pmc_gpe0_dw1 == 0) && + (config->pmc_gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ + bool all_different = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); - assert(result); + assert(all_different || all_zero); } void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index 569eac7..09eb57f 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -149,11 +149,16 @@ static void pmc_gpe0_different_values(const struct soc_intel_jasperlake_config *config) { - bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && + bool all_zero = (config->pmc_gpe0_dw0 == 0) && + (config->pmc_gpe0_dw1 == 0) && + (config->pmc_gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ + bool all_different = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); - assert(result); + assert(all_different || all_zero); } void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 154c3be..a0bba92 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -152,11 +152,16 @@ static void pmc_gpe0_different_values(const struct soc_intel_meteorlake_config *config) { - bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && + bool all_zero = (config->pmc_gpe0_dw0 == 0) && + (config->pmc_gpe0_dw1 == 0) && + (config->pmc_gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ + bool all_different = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); - assert(result); + assert(all_different || all_zero); } void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) diff --git a/src/soc/intel/pantherlake/pmutil.c b/src/soc/intel/pantherlake/pmutil.c index 306d834..7ce1dac 100644 --- a/src/soc/intel/pantherlake/pmutil.c +++ b/src/soc/intel/pantherlake/pmutil.c @@ -147,11 +147,16 @@ static void pmc_gpe0_different_values(const struct soc_intel_pantherlake_config *config) { - bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && + bool all_zero = (config->pmc_gpe0_dw0 == 0) && + (config->pmc_gpe0_dw1 == 0) && + (config->pmc_gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ + bool all_different = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); - assert(result); + assert(all_different || all_zero); } void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index ed1ab8b..91f0836 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -156,11 +156,16 @@ static void gpe0_different_values(const struct soc_intel_skylake_config *config) { - bool result = (config->gpe0_dw0 != config->gpe0_dw1) && + bool all_zero = (config->gpe0_dw0 == 0) && + (config->gpe0_dw1 == 0) && + (config->gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ + bool all_different = (config->gpe0_dw0 != config->gpe0_dw1) && (config->gpe0_dw0 != config->gpe0_dw2) && (config->gpe0_dw1 != config->gpe0_dw2); - assert(result); + assert(all_different || all_zero); } void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 7903264..0c5a1b59 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -155,11 +155,16 @@ static void pmc_gpe0_different_values(const struct soc_intel_tigerlake_config *config) { - bool result = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && + bool all_zero = (config->pmc_gpe0_dw0 == 0) && + (config->pmc_gpe0_dw1 == 0) && + (config->pmc_gpe0_dw2 == 0); + + /* Check if all values are different AND not all zero */ + bool all_different = (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw1) && (config->pmc_gpe0_dw0 != config->pmc_gpe0_dw2) && (config->pmc_gpe0_dw1 != config->pmc_gpe0_dw2); - assert(result); + assert(all_different || all_zero); } void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) -- To view, visit https://review.coreboot.org/c/coreboot/+/86164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51 Gerrit-Change-Number: 86164 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/skylake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 29 Jan '25

29 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86201?usp=email ) Change subject: soc/intel/skylake: Change the maximum C state to C8 ...................................................................... soc/intel/skylake: Change the maximum C state to C8 The EDS says that SkyLake "supports C0, C2, C3, C6, C8, and C10 package states". Update the highest state for non-S0ix boards accordingly. Change-Id: I9f0bf7c4d1ccc04b3ceae8b5f1d492dd6faa77e0 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86201 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 3a60ada..7694033 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -124,7 +124,7 @@ static int cstate_set_non_s0ix[] = { C_STATE_C1E, C_STATE_C3, - C_STATE_C7S_LONG_LAT, + C_STATE_C8 }; const acpi_cstate_t *soc_get_cstate_map(size_t *entries) -- To view, visit https://review.coreboot.org/c/coreboot/+/86201?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f0bf7c4d1ccc04b3ceae8b5f1d492dd6faa77e0 Gerrit-Change-Number: 86201 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/cannonlake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 29 Jan '25

29 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86200?usp=email ) Change subject: soc/intel/cannonlake: Change the maximum C state to C8 ...................................................................... soc/intel/cannonlake: Change the maximum C state to C8 The EDS says that Cannon Lake "supports C0, C2, C3, C6, C8, and C10 package states". Update the highest state for non-S0ix boards accordingly. Change-Id: Ia73e5119041616d4b2e0916b3f0d537c30f8568a Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86200 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 3b2a57c..d6cfa68 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -103,7 +103,7 @@ static int cstate_set_non_s0ix[] = { C_STATE_C1E, C_STATE_C6_LONG_LAT, - C_STATE_C7S_LONG_LAT + C_STATE_C8 }; static int cstate_set_s0ix[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/86200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia73e5119041616d4b2e0916b3f0d537c30f8568a Gerrit-Change-Number: 86200 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/tigerlake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 29 Jan '25

29 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86199?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/tigerlake: Change the maximum C state to C8 ...................................................................... soc/intel/tigerlake: Change the maximum C state to C8 The EDS says that Tiger Lake "supports C0, C2, C3, C6, C8, and C10 package states". Update the highest state for non-S0ix boards accordingly. Change-Id: I3fe0f5a8f9b52a44d1951037d74df4a244ba602e Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86199 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/tigerlake/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index dd9ef73..14286f7 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -102,7 +102,7 @@ static int cstate_set_non_s0ix[] = { C_STATE_C1, C_STATE_C6_LONG_LAT, - C_STATE_C7S_LONG_LAT + C_STATE_C8 }; static int cstate_set_s0ix[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/86199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fe0f5a8f9b52a44d1951037d74df4a244ba602e Gerrit-Change-Number: 86199 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/tigerlake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 29 Jan '25

29 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Nick Vaccaro, Paul Menzel, Subrata Banik. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86199?usp=email ) Change subject: soc/intel/tigerlake: Change the maximum C state to C8 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86199/comment/c3ed1507_07d657ac?us… : PS1, Line 9: Tigerr > Tiger Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fe0f5a8f9b52a44d1951037d74df4a244ba602e Gerrit-Change-Number: 86199 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 29 Jan 2025 11:45:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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