coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
3269 discussions

[S] Change in coreboot[main]: drivers/tpm: Use fieldlist for dynamic TPPF field creation
by Matt DeVillier (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84606?usp=email ) Change subject: drivers/tpm: Use fieldlist for dynamic TPPF field creation ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If80bb5bf69562f8b904c1b315e95a0b5627efbc4 Gerrit-Change-Number: 84606 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 14 Jan 2025 15:48:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in blobs[main]: soc/mediatek/mt8196: Add MCUPM firmware v1.1
by agogo (Code Review) 14 Jan '25

14 Jan '25

agogo has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/85980?usp=email ) Change subject: soc/mediatek/mt8196: Add MCUPM firmware v1.1 ...................................................................... soc/mediatek/mt8196: Add MCUPM firmware v1.1 Change to use release branch TEST=NA BUG=b:317009620 Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Signed-off-by: Agogo Huang <agogo.huang(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/mcupm.bin M soc/mediatek/mt8196/mcupm.bin.md5 M soc/mediatek/mt8196/mcupm_release_notes.txt 3 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/80/85980/1 diff --git a/soc/mediatek/mt8196/mcupm.bin b/soc/mediatek/mt8196/mcupm.bin index df4ea8f..74511bc 100644 --- a/soc/mediatek/mt8196/mcupm.bin +++ b/soc/mediatek/mt8196/mcupm.bin Binary files differ diff --git a/soc/mediatek/mt8196/mcupm.bin.md5 b/soc/mediatek/mt8196/mcupm.bin.md5 index a30b9f0..c4c2d57 100644 --- a/soc/mediatek/mt8196/mcupm.bin.md5 +++ b/soc/mediatek/mt8196/mcupm.bin.md5 @@ -1 +1 @@ -5b8708510dc7d2f305791fdf286c2d42 *mcupm.bin +500f2d5f92c3b38113d2eaf911067a51 mcupm.bin diff --git a/soc/mediatek/mt8196/mcupm_release_notes.txt b/soc/mediatek/mt8196/mcupm_release_notes.txt index f3b09fd..c3ca54b 100644 --- a/soc/mediatek/mt8196/mcupm_release_notes.txt +++ b/soc/mediatek/mt8196/mcupm_release_notes.txt @@ -2,3 +2,6 @@ # Version 1.0 1. Initial release. + +# Version 1.1 +1. Change to use release branch -- To view, visit https://review.coreboot.org/c/blobs/+/85980?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Gerrit-Change-Number: 85980 Gerrit-PatchSet: 1 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com>

1 0

[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by agogo (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. agogo has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85888/comment/7b26cdbe_ca50ab69?us… : PS5, Line 21: agogo.huang > Please spell it Agogo Huang. Done File src/soc/mediatek/mt8196/Kconfig: https://review.coreboot.org/c/coreboot/+/85888/comment/792c6c85_526ceb02?us… : PS5, Line 64: The file name of the MediaTek MCUPM firmware. > Can we add MCUPM firmware introduction in commit message? This is not necessary, config just specifies mcupm bin file name -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 14 Jan 2025 14:21:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[XS] Change in coreboot[main]: mb/google/rauru: Enable RTC
by Jarried Lin (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85979?usp=email ) Change subject: mb/google/rauru: Enable RTC ...................................................................... mb/google/rauru: Enable RTC Enable RTC so that we can see the correct timestamp and date in CromeOS. rauru-rev0 ~ # tail /var/log/eventtlog.txt suspend_stress_test -c 5 --suspend_max=30 --suspend_min=30 rauru-rev0 ~ # date Thu Nov 7 14:54:09 CST 2024 TEST=Build pass, check date in CromeOS BUG=b:355550460 Change-Id: I95822fc7646d41dbbc61258741a2a42988fc31d7 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/romstage.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/85979/1 diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index 57e8c1b..4752257 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -33,6 +33,7 @@ select TPM_GOOGLE_TI50 if VBOOT select COMMONLIB_STORAGE select COMMONLIB_STORAGE_MMC + select RTC config MAINBOARD_DIR string diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index d82e152..f5e7c69 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -9,6 +9,7 @@ #include <soc/mt6363.h> #include <soc/mt6373.h> #include <soc/mt6685.h> +#include <soc/mt6685_rtc.h> #include <soc/mtk_pwrsel.h> #include <soc/pcie.h> #include <soc/pll.h> @@ -37,6 +38,8 @@ mt6685_init(); srclken_rc_init(); clk_buf_init(); + if (CONFIG(RTC)) + rtc_boot(); mtk_dram_init(); modem_power_down(); -- To view, visit https://review.coreboot.org/c/coreboot/+/85979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I95822fc7646d41dbbc61258741a2a42988fc31d7 Gerrit-Change-Number: 85979 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

1 0

[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Jarried Lin (Code Review) 14 Jan '25

14 Jan '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... soc/mediatek/mt8196: Add RTC driver Add rtc drivers for mt6685. TEST=build pass. BUG=b:317009620 Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Signed-off-by: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/rtc_osc_init.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/include/soc/mt6685_hw.h A src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h A src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h A src/soc/mediatek/mt8196/include/soc/rtc.h A src/soc/mediatek/mt8196/mt6685_rtc.c 8 files changed, 2,148 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/85978/1 diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index d257357c..551e0e7 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -104,4 +104,10 @@ bool rtc_powerkey_init(void); void rtc_boot_common(void); +/* The return result of the clock calibration + * The result is relationship coefficient between 26M and 32K, + * which is non-unit. + */ +u16 rtc_eosc_cali(void); + #endif /* SOC_MEDIATEK_RTC_COMMON_H */ diff --git a/src/soc/mediatek/common/rtc_osc_init.c b/src/soc/mediatek/common/rtc_osc_init.c index 521e7a0..55cb51f 100644 --- a/src/soc/mediatek/common/rtc_osc_init.c +++ b/src/soc/mediatek/common/rtc_osc_init.c @@ -4,7 +4,7 @@ #include <soc/rtc_common.h> /* 32k clock calibration */ -static int rtc_eosc_cali(void) +u16 rtc_eosc_cali(void) { u16 diff_left, diff_right, cksel; u16 val = 0; diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index a287949..6418f45 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -39,10 +39,12 @@ romstage-y += ../common/mt6363.c mt6363.c romstage-y += ../common/mt6373.c mt6373.c romstage-y += ../common/mt6685.c mt6685.c +romstage-y += mt6685_rtc.c romstage-y += ../common/mtk_fsp.c romstage-y += mtk_pwrsel.c romstage-y += ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif.c pmif_init.c +romstage-y += ../common/rtc.c ../common/rtc_osc_init.c romstage-y += pmif_spmi.c romstage-y += srclken_rc.c @@ -60,6 +62,8 @@ ramstage-y += ../common/mt6363.c mt6363.c ramstage-y += ../common/mt6363_sdmadc.c ramstage-y += ../common/mt6373.c mt6373.c +ramstage-y += ../common/mt6685.c mt6685.c +ramstage-y += mt6685_rtc.c ramstage-y += ../common/mtk_fsp.c ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c @@ -67,6 +71,7 @@ ramstage-y += ../common/pmif_clk.c pmif_clk.c ramstage-y += ../common/pmif.c pmif_init.c ramstage-y += pmif_spmi.c +ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c ramstage-y += ../common/usb.c usb.c BL31_MAKEARGS += PLAT=mt8196 diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_hw.h b/src/soc/mediatek/mt8196/include/soc/mt6685_hw.h new file mode 100644 index 0000000..dce7a07 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/mt6685_hw.h @@ -0,0 +1,942 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 14.2.4 + */ + +#ifndef SOC_MEDIATEK_MT8196_MT6685_HW_H +#define SOC_MEDIATEK_MT8196_MT6685_HW_H + +#define MT6685_HWCID_L 0x8 + +#define MT6685_RG_OCT1_IO_0 0xa7 +#define MT6685_RG_OCT1_IO_1 0xa8 +#define MT6685_TOP_CON 0x18 +#define MT6685_TOP_CKPDN_CON0 0x10b +#define MT6685_TOP_CKPDN_CON0_SET 0x10c +#define MT6685_TOP_CKPDN_CON0_CLR 0x10d +#define MT6685_TOP_CKSEL_CON0 0x111 +#define MT6685_TOP_CKSEL_CON0_SET 0x112 +#define MT6685_TOP_CKSEL_CON0_CLR 0x113 +#define MT6685_TOP_RST_MISC_CLR 0x129 +#define MT6685_RG_SEQ_OFF 0x12f +#define MT6685_RG_OCTL_SDAT 0x131 +#define MT6685_TOP_TMA_KEY 0x39e +#define MT6685_TOP_TMA_KEY_H 0x39f +#define MT6685_TOP_DIG_WPK 0x3a8 +#define MT6685_TOP_DIG_WPK_H 0x3a9 +#define MT6685_SPMI_PWR_CMD 0x408 +#define MT6685_SCK_TOP_CON0_L 0x50c +#define MT6685_SCK_TOP_CON0_H 0x50d +#define MT6685_SCK_TOP_CKPDN_CON0_L 0x514 +#define MT6685_SCK_TOP_CKPDN_CON0_L_SET 0x515 +#define MT6685_SCK_TOP_CKPDN_CON0_L_CLR 0x516 +#define MT6685_SCK_TOP_RST_CON0 0x522 +#define MT6685_FQMTR_CON0_L 0x546 +#define MT6685_FQMTR_CON0_H 0x547 +#define MT6685_FQMTR_CON1_L 0x548 +#define MT6685_FQMTR_CON2_L 0x54a +#define MT6685_SCK_TOP_CKSEL_CON 0x568 +#define MT6685_RTC_SPAR_RELOAD 0x56a +#define MT6685_RTC_ANA_ID 0x580 +#define MT6685_RTC_DIG_ID 0x581 +#define MT6685_RTC_ANA_REV 0x582 +#define MT6685_RTC_DIG_REV 0x583 +#define MT6685_RTC_DBI 0x584 +#define MT6685_RTC_ESP 0x585 +#define MT6685_RTC_FPI 0x586 +#define MT6685_RTC_DXI 0x587 +#define MT6685_RTC_BBPU_L 0x588 +#define MT6685_RTC_BBPU_H 0x589 +#define MT6685_RTC_IRQ_STA 0x58a +#define MT6685_RTC_IRQ_EN 0x58c +#define MT6685_RTC_CII_EN_L 0x58e +#define MT6685_RTC_CII_EN_H 0x58f +#define MT6685_RTC_AL_MASK 0x590 +#define MT6685_RTC_TC_SEC 0x592 +#define MT6685_RTC_TC_MIN 0x594 +#define MT6685_RTC_TC_HOU 0x596 +#define MT6685_RTC_TC_DOM 0x598 +#define MT6685_RTC_TC_DOW 0x59a +#define MT6685_RTC_TC_MTH_L 0x59c +#define MT6685_RTC_TC_MTH_H 0x59d +#define MT6685_RTC_TC_YEA 0x59e +#define MT6685_RTC_AL_SEC_L 0x5a0 +#define MT6685_RTC_AL_SEC_H 0x5a1 +#define MT6685_RTC_AL_MIN 0x5a2 +#define MT6685_RTC_AL_HOU_L 0x5a4 +#define MT6685_RTC_AL_HOU_H 0x5a5 +#define MT6685_RTC_AL_DOM_L 0x5a6 +#define MT6685_RTC_AL_DOM_H 0x5a7 +#define MT6685_RTC_AL_DOW_L 0x5a8 +#define MT6685_RTC_AL_DOW_H 0x5a9 +#define MT6685_RTC_AL_MTH_L 0x5aa +#define MT6685_RTC_AL_MTH_H 0x5ab +#define MT6685_RTC_AL_YEA_L 0x5ac +#define MT6685_RTC_AL_YEA_H 0x5ad +#define MT6685_RTC_OSC32CON_L 0x5ae +#define MT6685_RTC_OSC32CON_H 0x5af +#define MT6685_RTC_POWERKEY1_L 0x5b0 +#define MT6685_RTC_POWERKEY1_H 0x5b1 +#define MT6685_RTC_POWERKEY2_L 0x5b2 +#define MT6685_RTC_POWERKEY2_H 0x5b3 +#define MT6685_RTC_PDN1_L 0x5b4 +#define MT6685_RTC_PDN1_H 0x5b5 +#define MT6685_RTC_PDN2_L 0x5b6 +#define MT6685_RTC_PDN2_H 0x5b7 +#define MT6685_RTC_SPAR0_L 0x5b8 +#define MT6685_RTC_SPAR0_H 0x5b9 +#define MT6685_RTC_SPAR1_L 0x5ba +#define MT6685_RTC_SPAR1_H 0x5bb +#define MT6685_RTC_PROT_L 0x5bc +#define MT6685_RTC_PROT_H 0x5bd +#define MT6685_RTC_DIFF_L 0x5be +#define MT6685_RTC_DIFF_H 0x5bf +#define MT6685_RTC_CALI_L 0x5c0 +#define MT6685_RTC_CALI_H 0x5c1 +#define MT6685_RTC_WRTGR 0x5c2 +#define MT6685_RTC_CON_L 0x5c4 +#define MT6685_RTC_CON_H 0x5c5 +#define MT6685_RTC_SEC_CTRL 0x5c6 +#define MT6685_RTC_INT_CNT_L 0x5c8 +#define MT6685_RTC_INT_CNT_H 0x5c9 +#define MT6685_RTC_SEC_DAT0_L 0x5ca +#define MT6685_RTC_SEC_DAT0_H 0x5cb +#define MT6685_RTC_SEC_DAT1_L 0x5cc +#define MT6685_RTC_SEC_DAT1_H 0x5cd +#define MT6685_RTC_SEC_DAT2_L 0x5ce +#define MT6685_RTC_SEC_DAT2_H 0x5cf +#define MT6685_RTC_RG_FG0 0x5d0 +#define MT6685_RTC_RG_FG1 0x5d2 +#define MT6685_RTC_RG_FG2 0x5d4 +#define MT6685_RTC_RG_FG3 0x5d6 +#define MT6685_RTC_SPAR_MACRO 0x5d8 +#define MT6685_RTC_SPAR_CORE 0x5e0 +#define MT6685_RTC_EOSC_CALI 0x5e2 +#define MT6685_RTC_SEC_ANA_ID 0x600 +#define MT6685_RTC_SEC_DIG_ID 0x601 +#define MT6685_RTC_SEC_ANA_REV 0x602 +#define MT6685_RTC_SEC_DIG_REV 0x603 +#define MT6685_RTC_SEC_DBI 0x604 +#define MT6685_RTC_SEC_ESP 0x605 +#define MT6685_RTC_SEC_FPI 0x606 +#define MT6685_RTC_SEC_DXI 0x607 +#define MT6685_RTC_TC_SEC_SEC 0x608 +#define MT6685_RTC_TC_MIN_SEC 0x60a +#define MT6685_RTC_TC_HOU_SEC 0x60c +#define MT6685_RTC_TC_DOM_SEC 0x60e +#define MT6685_RTC_TC_DOW_SEC 0x610 +#define MT6685_RTC_TC_MTH_SEC 0x612 +#define MT6685_RTC_TC_YEA_SEC 0x614 +#define MT6685_RTC_SEC_CK_PDN 0x616 +#define MT6685_RTC_SEC_WRTGR 0x618 +#define MT6685_DCXO_DIG_MODE_CW0 0x789 + +#define MT6685_RG_SRCLKEN_IN0_HW_MODE_ADDR \ + MT6685_TOP_CON +#define MT6685_RG_SRCLKEN_IN0_HW_MODE_MASK 0x1 +#define MT6685_RG_SRCLKEN_IN0_HW_MODE_SHIFT 1 +#define MT6685_RG_SRCLKEN_IN1_HW_MODE_ADDR \ + MT6685_TOP_CON +#define MT6685_RG_SRCLKEN_IN1_HW_MODE_MASK 0x1 +#define MT6685_RG_FQMTR_32K_CK_PDN_ADDR \ + MT6685_TOP_CKPDN_CON0 +#define MT6685_RG_FQMTR_32K_CK_PDN_MASK 0x1 +#define MT6685_RG_FQMTR_32K_CK_PDN_SHIFT 4 +#define MT6685_RG_SRCLKEN_IN1_HW_MODE_SHIFT 2 +#define MT6685_RG_FQMTR_CK_PDN_ADDR \ + MT6685_TOP_CKPDN_CON0 +#define MT6685_RG_FQMTR_CK_PDN_MASK 0x1 +#define MT6685_RG_FQMTR_CK_PDN_SHIFT 5 +#define MT6685_RG_INTRP_CK_PDN_ADDR \ + MT6685_TOP_CKPDN_CON0 +#define MT6685_RG_INTRP_CK_PDN_MASK 0x1 +#define MT6685_RG_INTRP_CK_PDN_SHIFT 6 +#define MT6685_TOP_CKPDN_CON0_SET_ADDR \ + MT6685_TOP_CKPDN_CON0_SET +#define MT6685_TOP_CKPDN_CON0_SET_MASK 0xFF +#define MT6685_TOP_CKPDN_CON0_SET_SHIFT 0 +#define MT6685_TOP_CKPDN_CON0_CLR_ADDR \ + MT6685_TOP_CKPDN_CON0_CLR +#define MT6685_TOP_CKPDN_CON0_CLR_MASK 0xFF +#define MT6685_TOP_CKPDN_CON0_CLR_SHIFT 0 +#define MT6685_RG_FQMTR_CK_CKSEL_ADDR \ + MT6685_TOP_CKSEL_CON0 +#define MT6685_RG_FQMTR_CK_CKSEL_MASK 0x7 +#define MT6685_RG_FQMTR_CK_CKSEL_SHIFT 0 +#define MT6685_RG_PMU32K_CK_CKSEL_ADDR \ + MT6685_TOP_CKSEL_CON0 +#define MT6685_RG_PMU32K_CK_CKSEL_MASK 0x1 +#define MT6685_RG_PMU32K_CK_CKSEL_SHIFT 3 +#define MT6685_TOP_CKSEL_CON0_SET_ADDR \ + MT6685_TOP_CKSEL_CON0_SET +#define MT6685_TOP_CKSEL_CON0_SET_MASK 0xFF +#define MT6685_TOP_CKSEL_CON0_SET_SHIFT 0 +#define MT6685_TOP_CKSEL_CON0_CLR_ADDR \ + MT6685_TOP_CKSEL_CON0_CLR +#define MT6685_TOP_CKSEL_CON0_CLR_MASK 0xFF +#define MT6685_TOP_CKSEL_CON0_CLR_SHIFT 0 +#define MT6685_TOP_RST_MISC_CLR_ADDR \ + MT6685_TOP_RST_MISC_CLR +#define MT6685_TOP_RST_MISC_CLR_MASK 0xFF +#define MT6685_TOP_RST_MISC_CLR_SHIFT 0 + +#define MT6685_RG_SEQ_OFF_ADDR \ + MT6685_RG_SEQ_OFF +#define MT6685_RG_SEQ_OFF_MASK 0x1 +#define MT6685_RG_SEQ_OFF_SHIFT 0 +#define MT6685_TMA_KEY_ADDR \ + MT6685_TOP_TMA_KEY +#define MT6685_TMA_KEY_MASK 0xFF +#define MT6685_TMA_KEY_SHIFT 0 +#define MT6685_TMA_KEY_H_ADDR \ + MT6685_TOP_TMA_KEY_H +#define MT6685_TMA_KEY_H_MASK 0xFF +#define MT6685_TMA_KEY_H_SHIFT 0 +#define MT6685_DIG_WPK_KEY_ADDR \ + MT6685_TOP_DIG_WPK +#define MT6685_DIG_WPK_KEY_MASK 0xFF +#define MT6685_DIG_WPK_KEY_SHIFT 0 +#define MT6685_DIG_WPK_KEY_H_ADDR \ + MT6685_TOP_DIG_WPK_H +#define MT6685_DIG_WPK_KEY_H_MASK 0xFF +#define MT6685_DIG_WPK_KEY_H_SHIFT 0 +#define MT6685_SCK_TOP_XTAL_SEL_ADDR \ + MT6685_SCK_TOP_CON0_L +#define MT6685_SCK_TOP_XTAL_SEL_MASK 0x1 +#define MT6685_SCK_TOP_XTAL_SEL_SHIFT 0 +#define MT6685_RG_RTC_SEC_MCLK_PDN_ADDR \ + MT6685_SCK_TOP_CKPDN_CON0_L +#define MT6685_RG_RTC_SEC_MCLK_PDN_MASK 0x1 +#define MT6685_RG_RTC_SEC_MCLK_PDN_SHIFT 0 +#define MT6685_RG_RTC_EOSC32_CK_PDN_ADDR \ + MT6685_SCK_TOP_CKPDN_CON0_L +#define MT6685_RG_RTC_EOSC32_CK_PDN_MASK 0x1 +#define MT6685_RG_RTC_EOSC32_CK_PDN_SHIFT 2 +#define MT6685_RG_RTC_SEC_32K_CK_PDN_ADDR \ + MT6685_SCK_TOP_CKPDN_CON0_L +#define MT6685_RG_RTC_SEC_32K_CK_PDN_MASK 0x1 +#define MT6685_RG_RTC_SEC_32K_CK_PDN_SHIFT 3 +#define MT6685_RG_RTC_MCLK_PDN_ADDR \ + MT6685_SCK_TOP_CKPDN_CON0_L +#define MT6685_RG_RTC_MCLK_PDN_MASK 0x1 +#define MT6685_RG_RTC_MCLK_PDN_SHIFT 4 +#define MT6685_RG_SHUTDOWN_SRC_SEL_ADDR \ + MT6685_SPMI_PWR_CMD +#define MT6685_RG_SHUTDOWN_SRC_SEL_MASK 0x1 +#define MT6685_RG_SHUTDOWN_SRC_SEL_SHIFT 1 +#define MT6685_SCK_TOP_CKPDN_CON0_L_SET_ADDR \ + MT6685_SCK_TOP_CKPDN_CON0_L_SET +#define MT6685_SCK_TOP_CKPDN_CON0_L_SET_MASK 0xFF +#define MT6685_SCK_TOP_CKPDN_CON0_L_SET_SHIFT 0 +#define MT6685_SCK_TOP_CKPDN_CON0_L_CLR_ADDR \ + MT6685_SCK_TOP_CKPDN_CON0_L_CLR +#define MT6685_SCK_TOP_CKPDN_CON0_L_CLR_MASK 0xFF +#define MT6685_SCK_TOP_CKPDN_CON0_L_CLR_SHIFT 0 +#define MT6685_RG_BANK_FQMTR_RST_ADDR \ + MT6685_SCK_TOP_RST_CON0 +#define MT6685_RG_BANK_FQMTR_RST_MASK 0x1 +#define MT6685_RG_BANK_FQMTR_RST_SHIFT 6 +#define MT6685_RG_RTC_DIG_TEST_MODE_ADDR \ + MT6685_RTC_DIG_CON0_H +#define MT6685_RG_RTC_DIG_TEST_MODE_MASK 0x1 +#define MT6685_RG_RTC_DIG_TEST_MODE_SHIFT 7 +#define MT6685_FQMTR_TCKSEL_ADDR \ + MT6685_FQMTR_CON0_L +#define MT6685_FQMTR_TCKSEL_MASK 0x7 +#define MT6685_FQMTR_TCKSEL_SHIFT 0 +#define MT6685_FQMTR_BUSY_ADDR \ + MT6685_FQMTR_CON0_L +#define MT6685_FQMTR_BUSY_MASK 0x1 +#define MT6685_FQMTR_BUSY_SHIFT 3 +#define MT6685_FQMTR_DCXO26M_EN_ADDR \ + MT6685_FQMTR_CON0_L +#define MT6685_FQMTR_DCXO26M_EN_MASK 0x1 +#define MT6685_FQMTR_DCXO26M_EN_SHIFT 4 +#define MT6685_FQMTR_EN_ADDR \ + MT6685_FQMTR_CON0_H +#define MT6685_FQMTR_EN_MASK 0x1 +#define MT6685_FQMTR_EN_SHIFT 7 +#define MT6685_FQMTR_WINSET_L_ADDR \ + MT6685_FQMTR_CON1_L +#define MT6685_FQMTR_WINSET_L_MASK 0xFF +#define MT6685_FQMTR_WINSET_L_SHIFT 0 +#define MT6685_FQMTR_WINSET_H_ADDR \ + MT6685_FQMTR_CON1_H +#define MT6685_FQMTR_WINSET_H_MASK 0xFF +#define MT6685_FQMTR_WINSET_H_SHIFT 0 +#define MT6685_FQMTR_DATA_L_ADDR \ + MT6685_FQMTR_CON2_L +#define MT6685_FQMTR_DATA_L_MASK 0xFF +#define MT6685_FQMTR_DATA_L_SHIFT 0 +#define MT6685_RG_RTC_32K1V8_0_SEL_ADDR \ + MT6685_SCK_TOP_CKSEL_CON +#define MT6685_RG_RTC_32K1V8_0_SEL_MASK 0x3 +#define MT6685_RG_RTC_32K1V8_0_SEL_SHIFT 0 +#define MT6685_SPAR_SW_RELOAD_ADDR \ + MT6685_RTC_SPAR_RELOAD +#define MT6685_SPAR_SW_RELOAD_MASK 0x1 +#define MT6685_SPAR_SW_RELOAD_SHIFT 0 +#define MT6685_RTC_ANA_ID_ADDR \ + MT6685_RTC_ANA_ID +#define MT6685_RTC_ANA_ID_MASK 0xFF +#define MT6685_RTC_ANA_ID_SHIFT 0 +#define MT6685_RTC_DIG_ID_ADDR \ + MT6685_RTC_DIG_ID +#define MT6685_RTC_DIG_ID_MASK 0xFF +#define MT6685_RTC_DIG_ID_SHIFT 0 +#define MT6685_RTC_ANA_MINOR_REV_ADDR \ + MT6685_RTC_ANA_REV +#define MT6685_RTC_ANA_MINOR_REV_MASK 0xF +#define MT6685_RTC_ANA_MINOR_REV_SHIFT 0 +#define MT6685_RTC_ANA_MAJOR_REV_ADDR \ + MT6685_RTC_ANA_REV +#define MT6685_RTC_ANA_MAJOR_REV_MASK 0xF +#define MT6685_RTC_ANA_MAJOR_REV_SHIFT 4 +#define MT6685_RTC_DIG_MINOR_REV_ADDR \ + MT6685_RTC_DIG_REV +#define MT6685_RTC_DIG_MINOR_REV_MASK 0xF +#define MT6685_RTC_DIG_MINOR_REV_SHIFT 0 +#define MT6685_RTC_DIG_MAJOR_REV_ADDR \ + MT6685_RTC_DIG_REV +#define MT6685_RTC_DIG_MAJOR_REV_MASK 0xF +#define MT6685_RTC_DIG_MAJOR_REV_SHIFT 4 +#define MT6685_RTC_CBS_ADDR \ + MT6685_RTC_DBI +#define MT6685_RTC_CBS_MASK 0x3 +#define MT6685_RTC_CBS_SHIFT 0 +#define MT6685_RTC_BIX_ADDR \ + MT6685_RTC_DBI +#define MT6685_RTC_BIX_MASK 0x3 +#define MT6685_RTC_BIX_SHIFT 2 +#define MT6685_RTC_ESP_ADDR \ + MT6685_RTC_ESP +#define MT6685_RTC_ESP_MASK 0xFF +#define MT6685_RTC_ESP_SHIFT 0 +#define MT6685_RTC_FPI_ADDR \ + MT6685_RTC_FPI +#define MT6685_RTC_FPI_MASK 0xFF +#define MT6685_RTC_FPI_SHIFT 0 +#define MT6685_RTC_DXI_ADDR \ + MT6685_RTC_DXI +#define MT6685_RTC_DXI_MASK 0xFF +#define MT6685_RTC_DXI_SHIFT 0 +#define MT6685_BBPU_ADDR \ + MT6685_RTC_BBPU_L +#define MT6685_BBPU_MASK 0xF +#define MT6685_BBPU_SHIFT 0 +#define MT6685_CLRPKY_ADDR \ + MT6685_RTC_BBPU_L +#define MT6685_CLRPKY_MASK 0x1 +#define MT6685_CLRPKY_SHIFT 4 +#define MT6685_RELOAD_ADDR \ + MT6685_RTC_BBPU_L +#define MT6685_RELOAD_MASK 0x1 +#define MT6685_RELOAD_SHIFT 5 +#define MT6685_CBUSY_ADDR \ + MT6685_RTC_BBPU_L +#define MT6685_CBUSY_MASK 0x1 +#define MT6685_CBUSY_SHIFT 6 +#define MT6685_ALARM_STATUS_ADDR \ + MT6685_RTC_BBPU_L +#define MT6685_ALARM_STATUS_MASK 0x1 +#define MT6685_ALARM_STATUS_SHIFT 7 +#define MT6685_KEY_BBPU_ADDR \ + MT6685_RTC_BBPU_H +#define MT6685_KEY_BBPU_MASK 0xFF +#define MT6685_KEY_BBPU_SHIFT 0 +#define MT6685_ALSTA_ADDR \ + MT6685_RTC_IRQ_STA +#define MT6685_ALSTA_MASK 0x1 +#define MT6685_ALSTA_SHIFT 0 +#define MT6685_TCSTA_ADDR \ + MT6685_RTC_IRQ_STA +#define MT6685_TCSTA_MASK 0x1 +#define MT6685_TCSTA_SHIFT 1 +#define MT6685_LPSTA_ADDR \ + MT6685_RTC_IRQ_STA +#define MT6685_LPSTA_MASK 0x1 +#define MT6685_LPSTA_SHIFT 3 +#define MT6685_AL_EN_ADDR \ + MT6685_RTC_IRQ_EN +#define MT6685_AL_EN_MASK 0x1 +#define MT6685_AL_EN_SHIFT 0 +#define MT6685_TC_EN_ADDR \ + MT6685_RTC_IRQ_EN +#define MT6685_TC_EN_MASK 0x1 +#define MT6685_TC_EN_SHIFT 1 +#define MT6685_ONESHOT_ADDR \ + MT6685_RTC_IRQ_EN +#define MT6685_ONESHOT_MASK 0x1 +#define MT6685_ONESHOT_SHIFT 2 +#define MT6685_LP_EN_ADDR \ + MT6685_RTC_IRQ_EN +#define MT6685_LP_EN_MASK 0x1 +#define MT6685_LP_EN_SHIFT 3 +#define MT6685_SECCII_ADDR \ + MT6685_RTC_CII_EN_L +#define MT6685_SECCII_MASK 0x1 +#define MT6685_SECCII_SHIFT 0 +#define MT6685_MINCII_ADDR \ + MT6685_RTC_CII_EN_L +#define MT6685_MINCII_MASK 0x1 +#define MT6685_MINCII_SHIFT 1 +#define MT6685_HOUCII_ADDR \ + MT6685_RTC_CII_EN_L +#define MT6685_HOUCII_MASK 0x1 +#define MT6685_HOUCII_SHIFT 2 +#define MT6685_DOMCII_ADDR \ + MT6685_RTC_CII_EN_L +#define MT6685_DOMCII_MASK 0x1 +#define MT6685_DOMCII_SHIFT 3 +#define MT6685_DOWCII_ADDR \ + MT6685_RTC_CII_EN_L +#define MT6685_DOWCII_MASK 0x1 +#define MT6685_DOWCII_SHIFT 4 +#define MT6685_MTHCII_ADDR \ + MT6685_RTC_CII_EN_L +#define MT6685_MTHCII_MASK 0x1 +#define MT6685_MTHCII_SHIFT 5 +#define MT6685_YEACII_ADDR \ + MT6685_RTC_CII_EN_L +#define MT6685_YEACII_MASK 0x1 +#define MT6685_YEACII_SHIFT 6 +#define MT6685_SECCII_1_2_ADDR \ + MT6685_RTC_CII_EN_L +#define MT6685_SECCII_1_2_MASK 0x1 +#define MT6685_SECCII_1_2_SHIFT 7 +#define MT6685_SECCII_1_4_ADDR \ + MT6685_RTC_CII_EN_H +#define MT6685_SECCII_1_4_MASK 0x1 +#define MT6685_SECCII_1_4_SHIFT 0 +#define MT6685_SECCII_1_8_ADDR \ + MT6685_RTC_CII_EN_H +#define MT6685_SECCII_1_8_MASK 0x1 +#define MT6685_SECCII_1_8_SHIFT 1 +#define MT6685_SEC_MSK_ADDR \ + MT6685_RTC_AL_MASK +#define MT6685_SEC_MSK_MASK 0x1 +#define MT6685_SEC_MSK_SHIFT 0 +#define MT6685_MIN_MSK_ADDR \ + MT6685_RTC_AL_MASK +#define MT6685_MIN_MSK_MASK 0x1 +#define MT6685_MIN_MSK_SHIFT 1 +#define MT6685_HOU_MSK_ADDR \ + MT6685_RTC_AL_MASK +#define MT6685_HOU_MSK_MASK 0x1 +#define MT6685_HOU_MSK_SHIFT 2 +#define MT6685_DOM_MSK_ADDR \ + MT6685_RTC_AL_MASK +#define MT6685_DOM_MSK_MASK 0x1 +#define MT6685_DOM_MSK_SHIFT 3 +#define MT6685_DOW_MSK_ADDR \ + MT6685_RTC_AL_MASK +#define MT6685_DOW_MSK_MASK 0x1 +#define MT6685_DOW_MSK_SHIFT 4 +#define MT6685_MTH_MSK_ADDR \ + MT6685_RTC_AL_MASK +#define MT6685_MTH_MSK_MASK 0x1 +#define MT6685_MTH_MSK_SHIFT 5 +#define MT6685_YEA_MSK_ADDR \ + MT6685_RTC_AL_MASK +#define MT6685_YEA_MSK_MASK 0x1 +#define MT6685_YEA_MSK_SHIFT 6 +#define MT6685_TC_SECOND_ADDR \ + MT6685_RTC_TC_SEC +#define MT6685_TC_SECOND_MASK 0x3F +#define MT6685_TC_SECOND_SHIFT 0 +#define MT6685_TC_MINUTE_ADDR \ + MT6685_RTC_TC_MIN +#define MT6685_TC_MINUTE_MASK 0x3F +#define MT6685_TC_MINUTE_SHIFT 0 +#define MT6685_TC_HOUR_ADDR \ + MT6685_RTC_TC_HOU +#define MT6685_TC_HOUR_MASK 0x1F +#define MT6685_TC_HOUR_SHIFT 0 +#define MT6685_TC_DOM_ADDR \ + MT6685_RTC_TC_DOM +#define MT6685_TC_DOM_MASK 0x1F +#define MT6685_TC_DOM_SHIFT 0 +#define MT6685_TC_DOW_ADDR \ + MT6685_RTC_TC_DOW +#define MT6685_TC_DOW_MASK 0x7 +#define MT6685_TC_DOW_SHIFT 0 +#define MT6685_TC_MONTH_ADDR \ + MT6685_RTC_TC_MTH_L +#define MT6685_TC_MONTH_MASK 0xF +#define MT6685_TC_MONTH_SHIFT 0 +#define MT6685_RTC_MACRO_ID_L_ADDR \ + MT6685_RTC_TC_MTH_L +#define MT6685_RTC_MACRO_ID_L_MASK 0xF +#define MT6685_RTC_MACRO_ID_L_SHIFT 4 +#define MT6685_RTC_MACRO_ID_H_ADDR \ + MT6685_RTC_TC_MTH_H +#define MT6685_RTC_MACRO_ID_H_MASK 0xFF +#define MT6685_RTC_MACRO_ID_H_SHIFT 0 +#define MT6685_TC_YEAR_ADDR \ + MT6685_RTC_TC_YEA +#define MT6685_TC_YEAR_MASK 0x7F +#define MT6685_TC_YEAR_SHIFT 0 +#define MT6685_AL_SECOND_ADDR \ + MT6685_RTC_AL_SEC_L +#define MT6685_AL_SECOND_MASK 0x3F +#define MT6685_AL_SECOND_SHIFT 0 +#define MT6685_BBPU_AUTO_PDN_SEL_ADDR \ + MT6685_RTC_AL_SEC_L +#define MT6685_BBPU_AUTO_PDN_SEL_MASK 0x1 +#define MT6685_BBPU_AUTO_PDN_SEL_SHIFT 6 +#define MT6685_BBPU_2SEC_CK_SEL_ADDR \ + MT6685_RTC_AL_SEC_L +#define MT6685_BBPU_2SEC_CK_SEL_MASK 0x1 +#define MT6685_BBPU_2SEC_CK_SEL_SHIFT 7 +#define MT6685_BBPU_2SEC_EN_ADDR \ + MT6685_RTC_AL_SEC_H +#define MT6685_BBPU_2SEC_EN_MASK 0x1 +#define MT6685_BBPU_2SEC_EN_SHIFT 0 +#define MT6685_BBPU_2SEC_MODE_ADDR \ + MT6685_RTC_AL_SEC_H +#define MT6685_BBPU_2SEC_MODE_MASK 0x3 +#define MT6685_BBPU_2SEC_MODE_SHIFT 1 +#define MT6685_BBPU_2SEC_STAT_CLEAR_ADDR \ + MT6685_RTC_AL_SEC_H +#define MT6685_BBPU_2SEC_STAT_CLEAR_MASK 0x1 +#define MT6685_BBPU_2SEC_STAT_CLEAR_SHIFT 3 +#define MT6685_BBPU_2SEC_STAT_STA_ADDR \ + MT6685_RTC_AL_SEC_H +#define MT6685_BBPU_2SEC_STAT_STA_MASK 0x1 +#define MT6685_BBPU_2SEC_STAT_STA_SHIFT 4 +#define MT6685_RTC_LPD_OPT_ADDR \ + MT6685_RTC_AL_SEC_H +#define MT6685_RTC_LPD_OPT_MASK 0x3 +#define MT6685_RTC_LPD_OPT_SHIFT 5 +#define MT6685_K_EOSC32_VTCXO_ON_SEL_ADDR \ + MT6685_RTC_AL_SEC_H +#define MT6685_K_EOSC32_VTCXO_ON_SEL_MASK 0x1 +#define MT6685_K_EOSC32_VTCXO_ON_SEL_SHIFT 7 + +#define MT6685_AL_MINUTE_ADDR \ + MT6685_RTC_AL_MIN +#define MT6685_AL_MINUTE_MASK 0x3F +#define MT6685_AL_MINUTE_SHIFT 0 +#define MT6685_AL_HOUR_ADDR \ + MT6685_RTC_AL_HOU_L +#define MT6685_AL_HOUR_MASK 0x1F +#define MT6685_AL_HOUR_SHIFT 0 +#define MT6685_NEW_SPARE0_ADDR \ + MT6685_RTC_AL_HOU_H +#define MT6685_NEW_SPARE0_MASK 0xFF +#define MT6685_NEW_SPARE0_SHIFT 0 +#define MT6685_AL_DOM_ADDR \ + MT6685_RTC_AL_DOM_L +#define MT6685_AL_DOM_MASK 0x1F +#define MT6685_AL_DOM_SHIFT 0 +#define MT6685_NEW_SPARE1_ADDR \ + MT6685_RTC_AL_DOM_H +#define MT6685_NEW_SPARE1_MASK 0xFF +#define MT6685_NEW_SPARE1_SHIFT 0 +#define MT6685_AL_DOW_ADDR \ + MT6685_RTC_AL_DOW_L +#define MT6685_AL_DOW_MASK 0x7 +#define MT6685_AL_DOW_SHIFT 0 +#define MT6685_RG_EOSC_CALI_TD_ADDR \ + MT6685_RTC_AL_DOW_L +#define MT6685_RG_EOSC_CALI_TD_MASK 0x7 +#define MT6685_RG_EOSC_CALI_TD_SHIFT 5 +#define MT6685_NEW_SPARE2_ADDR \ + MT6685_RTC_AL_DOW_H +#define MT6685_NEW_SPARE2_MASK 0xFF +#define MT6685_NEW_SPARE2_SHIFT 0 +#define MT6685_AL_MONTH_ADDR \ + MT6685_RTC_AL_MTH_L +#define MT6685_AL_MONTH_MASK 0xF +#define MT6685_AL_MONTH_SHIFT 0 +#define MT6685_NEW_SPARE3_ADDR \ + MT6685_RTC_AL_MTH_H +#define MT6685_NEW_SPARE3_MASK 0xFF +#define MT6685_NEW_SPARE3_SHIFT 0 +#define MT6685_AL_YEAR_ADDR \ + MT6685_RTC_AL_YEA_L +#define MT6685_AL_YEAR_MASK 0x7F +#define MT6685_AL_YEAR_SHIFT 0 +#define MT6685_RTC_K_EOSC_RSV_ADDR \ + MT6685_RTC_AL_YEA_H +#define MT6685_RTC_K_EOSC_RSV_MASK 0xFF +#define MT6685_RTC_K_EOSC_RSV_SHIFT 0 +#define MT6685_XOSCCALI_ADDR \ + MT6685_RTC_OSC32CON_L +#define MT6685_XOSCCALI_MASK 0x1F +#define MT6685_XOSCCALI_SHIFT 0 +#define MT6685_RTC_XOSC32_ENB_ADDR \ + MT6685_RTC_OSC32CON_L +#define MT6685_RTC_XOSC32_ENB_MASK 0x1 +#define MT6685_RTC_XOSC32_ENB_SHIFT 5 +#define MT6685_RTC_EMBCK_SEL_MODE_ADDR \ + MT6685_RTC_OSC32CON_L +#define MT6685_RTC_EMBCK_SEL_MODE_MASK 0x3 +#define MT6685_RTC_EMBCK_SEL_MODE_SHIFT 6 +#define MT6685_RTC_EMBCK_SRC_SEL_ADDR \ + MT6685_RTC_OSC32CON_H + +#define MT6685_RTC_EMBCK_SRC_SEL_MASK 0x1 +#define MT6685_RTC_EMBCK_SRC_SEL_SHIFT 0 +#define MT6685_RTC_EMBCK_SEL_OPTION_ADDR \ + MT6685_RTC_OSC32CON_H +#define MT6685_RTC_EMBCK_SEL_OPTION_MASK 0x1 +#define MT6685_RTC_EMBCK_SEL_OPTION_SHIFT 1 +#define MT6685_RTC_GPS_CKOUT_EN_ADDR \ + MT6685_RTC_OSC32CON_H +#define MT6685_RTC_GPS_CKOUT_EN_MASK 0x1 +#define MT6685_RTC_GPS_CKOUT_EN_SHIFT 2 +#define MT6685_RTC_EOSC32_VCT_EN_ADDR \ + MT6685_RTC_OSC32CON_H +#define MT6685_RTC_EOSC32_VCT_EN_MASK 0x1 +#define MT6685_RTC_EOSC32_VCT_EN_SHIFT 3 +#define MT6685_RTC_EOSC32_CHOP_EN_ADDR \ + MT6685_RTC_OSC32CON_H +#define MT6685_RTC_EOSC32_CHOP_EN_MASK 0x1 +#define MT6685_RTC_EOSC32_CHOP_EN_SHIFT 4 +#define MT6685_RTC_GP_OSC32_CON_ADDR \ + MT6685_RTC_OSC32CON_H +#define MT6685_RTC_GP_OSC32_CON_MASK 0x3 +#define MT6685_RTC_GP_OSC32_CON_SHIFT 5 +#define MT6685_RTC_REG_XOSC32_ENB_ADDR \ + MT6685_RTC_OSC32CON_H +#define MT6685_RTC_REG_XOSC32_ENB_MASK 0x1 +#define MT6685_RTC_REG_XOSC32_ENB_SHIFT 7 +#define MT6685_RTC_POWERKEY1_L_ADDR \ + MT6685_RTC_POWERKEY1_L +#define MT6685_RTC_POWERKEY1_L_MASK 0xFF +#define MT6685_RTC_POWERKEY1_L_SHIFT 0 +#define MT6685_RTC_POWERKEY1_H_ADDR \ + MT6685_RTC_POWERKEY1_H +#define MT6685_RTC_POWERKEY1_H_MASK 0xFF +#define MT6685_RTC_POWERKEY1_H_SHIFT 0 +#define MT6685_RTC_POWERKEY2_L_ADDR \ + MT6685_RTC_POWERKEY2_L +#define MT6685_RTC_POWERKEY2_L_MASK 0xFF +#define MT6685_RTC_POWERKEY2_L_SHIFT 0 +#define MT6685_RTC_POWERKEY2_H_ADDR \ + MT6685_RTC_POWERKEY2_H +#define MT6685_RTC_POWERKEY2_H_MASK 0xFF +#define MT6685_RTC_POWERKEY2_H_SHIFT 0 +#define MT6685_RTC_PDN1_L_ADDR \ + MT6685_RTC_PDN1_L +#define MT6685_RTC_PDN1_L_MASK 0xFF +#define MT6685_RTC_PDN1_L_SHIFT 0 +#define MT6685_RTC_PDN1_H_ADDR \ + MT6685_RTC_PDN1_H +#define MT6685_RTC_PDN1_H_MASK 0xFF +#define MT6685_RTC_PDN1_H_SHIFT 0 +#define MT6685_RTC_PDN2_L_ADDR \ + MT6685_RTC_PDN2_L +#define MT6685_RTC_PDN2_L_MASK 0xFF +#define MT6685_RTC_PDN2_L_SHIFT 0 +#define MT6685_RTC_PDN2_H_ADDR \ + MT6685_RTC_PDN2_H +#define MT6685_RTC_PDN2_H_MASK 0xFF +#define MT6685_RTC_PDN2_H_SHIFT 0 +#define MT6685_RTC_SPAR0_L_ADDR \ + MT6685_RTC_SPAR0_L +#define MT6685_RTC_SPAR0_L_MASK 0xFF +#define MT6685_RTC_SPAR0_L_SHIFT 0 +#define MT6685_RTC_SPAR0_H_ADDR \ + MT6685_RTC_SPAR0_H +#define MT6685_RTC_SPAR0_H_MASK 0xFF +#define MT6685_RTC_SPAR0_H_SHIFT 0 +#define MT6685_RTC_SPAR1_L_ADDR \ + MT6685_RTC_SPAR1_L +#define MT6685_RTC_SPAR1_L_MASK 0xFF +#define MT6685_RTC_SPAR1_L_SHIFT 0 +#define MT6685_RTC_SPAR1_H_ADDR \ + MT6685_RTC_SPAR1_H +#define MT6685_RTC_SPAR1_H_MASK 0xFF +#define MT6685_RTC_SPAR1_H_SHIFT 0 +#define MT6685_RTC_PROT_L_ADDR \ + MT6685_RTC_PROT_L +#define MT6685_RTC_PROT_L_MASK 0xFF +#define MT6685_RTC_PROT_L_SHIFT 0 +#define MT6685_RTC_PROT_H_ADDR \ + MT6685_RTC_PROT_H +#define MT6685_RTC_PROT_H_MASK 0xFF +#define MT6685_RTC_PROT_H_SHIFT 0 +#define MT6685_RTC_DIFF_L_ADDR \ + MT6685_RTC_DIFF_L +#define MT6685_RTC_DIFF_L_MASK 0xFF +#define MT6685_RTC_DIFF_L_SHIFT 0 +#define MT6685_RTC_DIFF_H_ADDR \ + MT6685_RTC_DIFF_H +#define MT6685_RTC_DIFF_H_MASK 0xF +#define MT6685_RTC_DIFF_H_SHIFT 0 +#define MT6685_POWER_DETECTED_ADDR \ + MT6685_RTC_DIFF_H +#define MT6685_POWER_DETECTED_MASK 0x1 +#define MT6685_POWER_DETECTED_SHIFT 4 +#define MT6685_K_EOSC32_RSV_ADDR \ + MT6685_RTC_DIFF_H +#define MT6685_K_EOSC32_RSV_MASK 0x1 +#define MT6685_K_EOSC32_RSV_SHIFT 6 +#define MT6685_CALI_RD_SEL_ADDR \ + MT6685_RTC_DIFF_H +#define MT6685_CALI_RD_SEL_MASK 0x1 +#define MT6685_CALI_RD_SEL_SHIFT 7 +#define MT6685_RTC_CALI_L_ADDR \ + MT6685_RTC_CALI_L +#define MT6685_RTC_CALI_L_MASK 0xFF +#define MT6685_RTC_CALI_L_SHIFT 0 +#define MT6685_RTC_CALI_H_ADDR \ + MT6685_RTC_CALI_H +#define MT6685_RTC_CALI_H_MASK 0x3F +#define MT6685_RTC_CALI_H_SHIFT 0 +#define MT6685_CALI_WR_SEL_ADDR \ + MT6685_RTC_CALI_H +#define MT6685_CALI_WR_SEL_MASK 0x1 +#define MT6685_CALI_WR_SEL_SHIFT 6 +#define MT6685_K_EOSC32_OVERFLOW_ADDR \ + MT6685_RTC_CALI_H +#define MT6685_K_EOSC32_OVERFLOW_MASK 0x1 +#define MT6685_K_EOSC32_OVERFLOW_SHIFT 7 +#define MT6685_WRTGR_ADDR \ + MT6685_RTC_WRTGR +#define MT6685_WRTGR_MASK 0x1 +#define MT6685_WRTGR_SHIFT 0 +#define MT6685_VBAT_LPSTA_RAW_ADDR \ + MT6685_RTC_CON_L +#define MT6685_VBAT_LPSTA_RAW_MASK 0x1 +#define MT6685_VBAT_LPSTA_RAW_SHIFT 0 +#define MT6685_EOSC32_LPEN_ADDR \ + MT6685_RTC_CON_L +#define MT6685_EOSC32_LPEN_MASK 0x1 +#define MT6685_EOSC32_LPEN_SHIFT 1 +#define MT6685_XOSC32_LPEN_ADDR \ + MT6685_RTC_CON_L +#define MT6685_XOSC32_LPEN_MASK 0x1 +#define MT6685_XOSC32_LPEN_SHIFT 2 +#define MT6685_LPRST_ADDR \ + MT6685_RTC_CON_L +#define MT6685_LPRST_MASK 0x1 +#define MT6685_LPRST_SHIFT 3 +#define MT6685_CDBO_ADDR \ + MT6685_RTC_CON_L + +#define MT6685_CDBO_MASK 0x1 +#define MT6685_CDBO_SHIFT 4 +#define MT6685_F32KOB_ADDR \ + MT6685_RTC_CON_L +#define MT6685_F32KOB_MASK 0x1 +#define MT6685_F32KOB_SHIFT 5 +#define MT6685_GPO_ADDR \ + MT6685_RTC_CON_L +#define MT6685_GPO_MASK 0x1 +#define MT6685_GPO_SHIFT 6 +#define MT6685_GOE_ADDR \ + MT6685_RTC_CON_L +#define MT6685_GOE_MASK 0x1 +#define MT6685_GOE_SHIFT 7 +#define MT6685_GSR_ADDR \ + MT6685_RTC_CON_H +#define MT6685_GSR_MASK 0x1 +#define MT6685_GSR_SHIFT 0 +#define MT6685_GSMT_ADDR \ + MT6685_RTC_CON_H +#define MT6685_GSMT_MASK 0x1 +#define MT6685_GSMT_SHIFT 1 +#define MT6685_GPEN_ADDR \ + MT6685_RTC_CON_H +#define MT6685_GPEN_MASK 0x1 +#define MT6685_GPEN_SHIFT 2 +#define MT6685_GPU_ADDR \ + MT6685_RTC_CON_H +#define MT6685_GPU_MASK 0x1 +#define MT6685_GPU_SHIFT 3 +#define MT6685_GE4_ADDR \ + MT6685_RTC_CON_H +#define MT6685_GE4_MASK 0x1 +#define MT6685_GE4_SHIFT 4 +#define MT6685_GE8_ADDR \ + MT6685_RTC_CON_H +#define MT6685_GE8_MASK 0x1 +#define MT6685_GE8_SHIFT 5 +#define MT6685_GPI_ADDR \ + MT6685_RTC_CON_H +#define MT6685_GPI_MASK 0x1 +#define MT6685_GPI_SHIFT 6 +#define MT6685_LPSTA_RAW_ADDR \ + MT6685_RTC_CON_H +#define MT6685_LPSTA_RAW_MASK 0x1 +#define MT6685_LPSTA_RAW_SHIFT 7 +#define MT6685_DAT0_LOCK_ADDR \ + MT6685_RTC_SEC_CTRL +#define MT6685_DAT0_LOCK_MASK 0x1 +#define MT6685_DAT0_LOCK_SHIFT 0 +#define MT6685_DAT1_LOCK_ADDR \ + MT6685_RTC_SEC_CTRL +#define MT6685_DAT1_LOCK_MASK 0x1 +#define MT6685_DAT1_LOCK_SHIFT 1 +#define MT6685_DAT2_LOCK_ADDR \ + MT6685_RTC_SEC_CTRL +#define MT6685_DAT2_LOCK_MASK 0x1 +#define MT6685_DAT2_LOCK_SHIFT 2 +#define MT6685_RTC_INT_CNT_L_ADDR \ + MT6685_RTC_INT_CNT_L +#define MT6685_RTC_INT_CNT_L_MASK 0xFF +#define MT6685_RTC_INT_CNT_L_SHIFT 0 +#define MT6685_RTC_INT_CNT_H_ADDR \ + MT6685_RTC_INT_CNT_H +#define MT6685_RTC_INT_CNT_H_MASK 0x7F +#define MT6685_RTC_INT_CNT_H_SHIFT 0 +#define MT6685_RTC_SEC_DAT0_L_ADDR \ + MT6685_RTC_SEC_DAT0_L +#define MT6685_RTC_SEC_DAT0_L_MASK 0xFF +#define MT6685_RTC_SEC_DAT0_L_SHIFT 0 +#define MT6685_RTC_SEC_DAT0_H_ADDR \ + MT6685_RTC_SEC_DAT0_H +#define MT6685_RTC_SEC_DAT0_H_MASK 0xFF +#define MT6685_RTC_SEC_DAT0_H_SHIFT 0 +#define MT6685_RTC_SEC_DAT1_L_ADDR \ + MT6685_RTC_SEC_DAT1_L +#define MT6685_RTC_SEC_DAT1_L_MASK 0xFF +#define MT6685_RTC_SEC_DAT1_L_SHIFT 0 +#define MT6685_RTC_SEC_DAT1_H_ADDR \ + MT6685_RTC_SEC_DAT1_H +#define MT6685_RTC_SEC_DAT1_H_MASK 0xFF +#define MT6685_RTC_SEC_DAT1_H_SHIFT 0 +#define MT6685_RTC_SEC_DAT2_L_ADDR \ + MT6685_RTC_SEC_DAT2_L +#define MT6685_RTC_SEC_DAT2_L_MASK 0xFF +#define MT6685_RTC_SEC_DAT2_L_SHIFT 0 +#define MT6685_RTC_SEC_DAT2_H_ADDR \ + MT6685_RTC_SEC_DAT2_H +#define MT6685_RTC_SEC_DAT2_H_MASK 0xFF +#define MT6685_RTC_SEC_DAT2_H_SHIFT 0 +#define MT6685_RTC_RG_FG0_ADDR \ + MT6685_RTC_RG_FG0 +#define MT6685_RTC_RG_FG0_MASK 0xFF +#define MT6685_RTC_RG_FG0_SHIFT 0 +#define MT6685_RTC_RG_FG1_ADDR \ + MT6685_RTC_RG_FG1 +#define MT6685_RTC_RG_FG1_MASK 0xFF +#define MT6685_RTC_RG_FG1_SHIFT 0 +#define MT6685_RTC_RG_FG2_ADDR \ + MT6685_RTC_RG_FG2 +#define MT6685_RTC_RG_FG2_MASK 0xFF +#define MT6685_RTC_RG_FG2_SHIFT 0 +#define MT6685_RTC_RG_FG3_ADDR \ + MT6685_RTC_RG_FG3 +#define MT6685_RTC_RG_FG3_MASK 0xFF +#define MT6685_RTC_RG_FG3_SHIFT a + +#define MT6685_RTC_UVLO_WAIT_ADDR \ + MT6685_RTC_SPAR_MACRO +#define MT6685_RTC_UVLO_WAIT_MASK 0x3 +#define MT6685_RTC_UVLO_WAIT_SHIFT 0 +#define MT6685_RTC_SPAR_THRE_SEL_ADDR \ + MT6685_RTC_SPAR_MACRO +#define MT6685_RTC_SPAR_THRE_SEL_MASK 0x1 +#define MT6685_RTC_SPAR_THRE_SEL_SHIFT 2 +#define MT6685_RTC_SPAR_PWRKEY_MATCH_LPD_ADDR \ + MT6685_RTC_SPAR_MACRO +#define MT6685_RTC_SPAR_PWRKEY_MATCH_LPD_MASK 0x1 +#define MT6685_RTC_SPAR_PWRKEY_MATCH_LPD_SHIFT 4 +#define MT6685_RTC_SPAR_PWRKEY_MATCH_ADDR \ + MT6685_RTC_SPAR_MACRO +#define MT6685_RTC_SPAR_PWRKEY_MATCH_MASK 0x1 +#define MT6685_RTC_SPAR_PWRKEY_MATCH_SHIFT 5 +#define MT6685_SPAR_PROT_STAT_ADDR \ + MT6685_RTC_SPAR_MACRO +#define MT6685_RTC_SPAR_PROT_STAT_MASK 0x3 +#define MT6685_RTC_SPAR_PROT_STAT_SHIFT 6 +#define MT6685_RTC_SPAR_CORE_ADDR \ + MT6685_RTC_SPAR_CORE +#define MT6685_RTC_SPAR_CORE_MASK 0xFF +#define MT6685_RTC_SPAR_CORE_SHIFT 0 +#define MT6685_RTC_RG_EOSC_CALI_ADDR \ + MT6685_RTC_EOSC_CALI +#define MT6685_RTC_RG_EOSC_CALI_MASK 0x1F +#define MT6685_RTC_RG_EOSC_CALI_SHIFT 0 +#define MT6685_RTC_SEC_ANA_ID_ADDR \ + MT6685_RTC_SEC_ANA_ID +#define MT6685_RTC_SEC_ANA_ID_MASK 0xFF +#define MT6685_RTC_SEC_ANA_ID_SHIFT 0 +#define MT6685_RTC_SEC_DIG_ID_ADDR \ + MT6685_RTC_SEC_DIG_ID +#define MT6685_RTC_SEC_DIG_ID_MASK 0xFF +#define MT6685_RTC_SEC_DIG_ID_SHIFT 0 +#define MT6685_RTC_SEC_ANA_MINOR_REV_ADDR \ + MT6685_RTC_SEC_ANA_REV +#define MT6685_RTC_SEC_ANA_MINOR_REV_MASK 0xF +#define MT6685_RTC_SEC_ANA_MINOR_REV_SHIFT 0 +#define MT6685_RTC_SEC_ANA_MAJOR_REV_ADDR \ + MT6685_RTC_SEC_ANA_REV +#define MT6685_RTC_SEC_ANA_MAJOR_REV_MASK 0xF +#define MT6685_RTC_SEC_ANA_MAJOR_REV_SHIFT 4 +#define MT6685_RTC_SEC_DIG_MINOR_REV_ADDR \ + MT6685_RTC_SEC_DIG_REV +#define MT6685_RTC_SEC_DIG_MINOR_REV_MASK 0xF +#define MT6685_RTC_SEC_DIG_MINOR_REV_SHIFT 0 +#define MT6685_RTC_SEC_DIG_MAJOR_REV_ADDR \ + MT6685_RTC_SEC_DIG_REV +#define MT6685_RTC_SEC_DIG_MAJOR_REV_MASK 0xF +#define MT6685_RTC_SEC_DIG_MAJOR_REV_SHIFT 4 +#define MT6685_RTC_SEC_CBS_ADDR \ + MT6685_RTC_SEC_DBI +#define MT6685_RTC_SEC_CBS_MASK 0x3 +#define MT6685_RTC_SEC_CBS_SHIFT 0 +#define MT6685_RTC_SEC_BIX_ADDR \ + MT6685_RTC_SEC_DBI +#define MT6685_RTC_SEC_BIX_MASK 0x3 +#define MT6685_RTC_SEC_BIX_SHIFT 2 +#define MT6685_RTC_SEC_ESP_ADDR \ + MT6685_RTC_SEC_ESP +#define MT6685_RTC_SEC_ESP_MASK 0xFF +#define MT6685_RTC_SEC_ESP_SHIFT 0 +#define MT6685_RTC_SEC_FPI_ADDR \ + MT6685_RTC_SEC_FPI +#define MT6685_RTC_SEC_FPI_MASK 0xFF +#define MT6685_RTC_SEC_FPI_SHIFT 0 +#define MT6685_RTC_SEC_DXI_ADDR \ + MT6685_RTC_SEC_DXI +#define MT6685_RTC_SEC_DXI_MASK 0xFF +#define MT6685_RTC_SEC_DXI_SHIFT 0 +#define MT6685_TC_SECOND_SEC_ADDR \ + MT6685_RTC_TC_SEC_SEC +#define MT6685_TC_SECOND_SEC_MASK 0x3F +#define MT6685_TC_SECOND_SEC_SHIFT 0 +#define MT6685_TC_MINUTE_SEC_ADDR \ + MT6685_RTC_TC_MIN_SEC +#define MT6685_TC_MINUTE_SEC_MASK 0x3F +#define MT6685_TC_MINUTE_SEC_SHIFT 0 +#define MT6685_TC_HOUR_SEC_ADDR \ + MT6685_RTC_TC_HOU_SEC +#define MT6685_TC_HOUR_SEC_MASK 0x1F +#define MT6685_TC_HOUR_SEC_SHIFT 0 +#define MT6685_TC_DOM_SEC_ADDR \ + MT6685_RTC_TC_DOM_SEC +#define MT6685_TC_DOM_SEC_MASK 0x1F +#define MT6685_TC_DOM_SEC_SHIFT 0 +#define MT6685_TC_DOW_SEC_ADDR \ + MT6685_RTC_TC_DOW_SEC +#define MT6685_TC_DOW_SEC_MASK 0x7 +#define MT6685_TC_DOW_SEC_SHIFT 0 +#define MT6685_TC_MONTH_SEC_ADDR \ + MT6685_RTC_TC_MTH_SEC +#define MT6685_TC_MONTH_SEC_MASK 0xF +#define MT6685_TC_MONTH_SEC_SHIFT 0 +#define MT6685_TC_YEAR_SEC_ADDR \ + MT6685_RTC_TC_YEA_SEC +#define MT6685_TC_YEAR_SEC_MASK 0x7F +#define MT6685_TC_YEAR_SEC_SHIFT 0 +#define MT6685_RTC_SEC_CK_PDN_ADDR \ + MT6685_RTC_SEC_CK_PDN +#define MT6685_RTC_SEC_CK_PDN_MASK 0x1 +#define MT6685_RTC_SEC_CK_PDN_SHIFT 0 +#define MT6685_RTC_SEC_WRTGR_ADDR \ + MT6685_RTC_SEC_WRTGR +#define MT6685_RTC_SEC_WRTGR_MASK 0x1 +#define MT6685_RTC_SEC_WRTGR_SHIFT 0 +#define MT6685_XO_EN32K_MAN_ADDR \ + MT6685_DCXO_DIG_MODE_CW0 +#define MT6685_XO_EN32K_MAN_MASK 0x1 +#define MT6685_XO_EN32K_MAN_SHIFT 1 + +#endif /* SOC_MEDIATEK_MT8196_MT6685_HW_H */ diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h new file mode 100644 index 0000000..a23bd72 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 14.2.4 + */ + +#ifndef SOC_MEDIATEK_MT8196_MT6685_RTC_H +#define SOC_MEDIATEK_MT8196_MT6685_RTC_H + +#include <commonlib/bsd/bcd.h> +#include <console/console.h> +#include <rtc.h> +#include <stdbool.h> +#include <timer.h> + +/* frequency meter related */ +#define RG_BANK_FQMTR_RST MT6685_RG_BANK_FQMTR_RST_ADDR +#define RG_BANK_FQMTR_RST_MASK MT6685_RG_BANK_FQMTR_RST_MASK +#define RG_BANK_FQMTR_RST_SHIFT MT6685_RG_BANK_FQMTR_RST_SHIFT +#define RG_FQMTR_TCKSEL MT6685_FQMTR_TCKSEL_ADDR +#define RG_FQMTR_WINSET MT6685_FQMTR_WINSET_L_ADDR +#define RG_FQMTR_BUSY MT6685_FQMTR_BUSY_ADDR +#define RG_FQMTR_DCXO26M_EN MT6685_FQMTR_DCXO26M_EN_ADDR +#define RG_FQMTR_DCXO26M_MASK MT6685_FQMTR_DCXO26M_EN_MASK +#define RG_FQMTR_DCXO26M_SHIFT MT6685_FQMTR_DCXO26M_EN_SHIFT +#define RG_FQMTR_DATA MT6685_FQMTR_DATA_L_ADDR +#define RG_FQMTR_EN MT6685_FQMTR_EN_ADDR +#define RG_FQMTR_EN_MASK MT6685_FQMTR_EN_MASK +#define RG_FQMTR_EN_SHIFT MT6685_FQMTR_EN_SHIFT + +#define RG_FQMTR_32K_CK_PDN_SET MT6685_TOP_CKPDN_CON0_SET_ADDR +#define RG_FQMTR_32K_CK_PDN_CLR MT6685_TOP_CKPDN_CON0_CLR_ADDR +#define RG_FQMTR_32K_CK_PDN_MASK MT6685_RG_FQMTR_32K_CK_PDN_MASK +#define RG_FQMTR_32K_CK_PDN_SHIFT MT6685_RG_FQMTR_32K_CK_PDN_SHIFT + +#define RG_FQMTR_CLK_CK_PDN_SET MT6685_TOP_CKPDN_CON0_SET_ADDR +#define RG_FQMTR_CLK_CK_PDN_CLR MT6685_TOP_CKPDN_CON0_CLR_ADDR +#define RG_FQMTR_CLK_CK_PDN_MASK MT6685_RG_FQMTR_CK_PDN_MASK +#define RG_FQMTR_CLK_CK_PDN_SHIFT MT6685_RG_FQMTR_CK_PDN_SHIFT + +#define RG_FQMTR_CKSEL MT6685_RG_FQMTR_CK_CKSEL_ADDR +#define RG_FQMTR_CKSEL_SET MT6685_TOP_CKSEL_CON0_SET_ADDR +#define RG_FQMTR_CKSEL_CLR MT6685_TOP_CKSEL_CON0_CLR_ADDR +#define RG_FQMTR_CKSEL_MASK MT6685_RG_FQMTR_CK_CKSEL_MASK +#define RG_FQMTR_CKSEL_SHIFT MT6685_RG_FQMTR_CK_CKSEL_SHIFT +#define RG_FQMTR_TCKSEL_MASK MT6685_FQMTR_TCKSEL_MASK +#define RG_FQMTR_TCKSEL_SHIFT MT6685_FQMTR_TCKSEL_SHIFT + +#define FQMTR_FIX_CLK_26M (0 << RG_FQMTR_CKSEL_SHIFT) +#define FQMTR_FIX_CLK_XOSC_32K_DET (1 << RG_FQMTR_CKSEL_SHIFT) +#define FQMTR_FIX_CLK_EOSC_32K (2 << RG_FQMTR_CKSEL_SHIFT) +#define FQMTR_FIX_CLK_RTC_32K (3 << RG_FQMTR_CKSEL_SHIFT) +#define FQMTR_FIX_CLK_SMPS_CK (4 << RG_FQMTR_CKSEL_SHIFT) +#define FQMTR_FIX_CLK_TCK_SEC (5 << RG_FQMTR_CKSEL_SHIFT) +#define FQMTR_FIX_CLK_PMU_75K (6 << RG_FQMTR_CKSEL_SHIFT) + +#define BANK_FQMTR_RST BIT(6) +#define FQMTR_EN BIT(7) +#define FQMTR_BUSY BIT(3) +#define FQMTR_DCXO26M_EN BIT(4) +#define FQMTR_XOSC32_CK 0 +#define FQMTR_DCXO_F32K_CK 1 +#define FQMTR_EOSC32_CK 2 +#define FQMTR_XOSC32_CK_DETECTON 3 +#define FQMTR_FQM26M_CK 4 +#define FQMTR_FQM32K_CK 5 +#define FQMTR_TEST_CK 6 +#define FQMTR_WINSET 0x0000 + +#define RG_75K_32K_SEL MT6685_TOP_CKSEL_CON0_CLR_ADDR +#define RTC_75K_TO_32K BIT(0) + +#define RG_OCT1_RTC32K_1V8_0 MT6685_RG_OCT1_IO_0 +#define RG_OCT1_RTC32K_1V8_0_MASK 0x3 +#define RG_OCT1_RTC32K_1V8_0_SHIFT 5 + +#define RG_OCT1_RTC32K_1V8_F MT6685_RG_OCT1_IO_1 +#define RG_OCT1_RTC32K_1V8_F_MASK 0x3 +#define RG_OCT1_RTC32K_1V8_F_SHIFT 1 + +#define HWCID_L MT6685_HWCID_L + +void rtc_boot(void); + +#endif /* SOC_MEDIATEK_MT8196_MT6685_RTC_H */ diff --git a/src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h new file mode 100644 index 0000000..d68b196 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h @@ -0,0 +1,371 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 14.2.4 + */ + +#ifndef SOC_MEDIATEK_MT8196_MT6685_RTC_HW_H +#define SOC_MEDIATEK_MT8196_MT6685_RTC_HW_H + +#include <soc/mt6685_hw.h> + +/* RTC_BBPU bit field */ +#define MT6685_PWREN_SHIFT 0 +#define MT6685_PWREN_MASK 0x1 +#define MT6685_SPAR_SW_SHIFT 1 +#define MT6685_SPAR_SW_MASK 0x1 +#define MT6685_RESET_SPAR_SHIFT 2 +#define MT6685_RESET_SPAR_MASK 0x1 +#define MT6685_RESET_ALARM_SHIFT 3 +#define MT6685_RESET_ALARM_MASK 0x1 + +/* RTC registers */ +#define RTC_BBPU MT6685_BBPU_ADDR +#define RTC_BBPU_PWREN (MT6685_PWREN_MASK << MT6685_PWREN_SHIFT) +#define RTC_BBPU_SPAR_SW (MT6685_SPAR_SW_MASK << MT6685_SPAR_SW_SHIFT) +#define RTC_BBPU_RESET_SPAR (MT6685_RESET_SPAR_MASK << MT6685_RESET_SPAR_SHIFT) +#define RTC_BBPU_RESET_ALARM (MT6685_RESET_ALARM_MASK << MT6685_RESET_ALARM_SHIFT) +#define RTC_BBPU_CLRPKY (MT6685_CLRPKY_MASK << MT6685_CLRPKY_SHIFT) +#define RTC_BBPU_RELOAD (MT6685_RELOAD_MASK << MT6685_RELOAD_SHIFT) +#define RTC_BBPU_CBUSY (MT6685_CBUSY_MASK << MT6685_CBUSY_SHIFT) +#define RTC_BBPU_ALARM_STATUS (MT6685_ALARM_STATUS_MASK << MT6685_ALARM_STATUS_SHIFT) +#define RTC_BBPU_KEY (0x43 << (MT6685_KEY_BBPU_SHIFT + 8)) + +#define RTC_IRQ_STA MT6685_ALSTA_ADDR +#define RTC_IRQ_STA_AL (MT6685_ALSTA_MASK << MT6685_ALSTA_SHIFT) +#define RTC_IRQ_STA_TC (MT6685_TCSTA_MASK << MT6685_TCSTA_SHIFT) +#define RTC_IRQ_STA_LP (MT6685_LPSTA_MASK << MT6685_LPSTA_SHIFT) + +#define RTC_IRQ_EN MT6685_AL_EN_ADDR +#define RTC_IRQ_EN_AL (MT6685_AL_EN_MASK << MT6685_AL_EN_SHIFT) +#define RTC_IRQ_EN_TC (MT6685_TC_EN_MASK << MT6685_TC_EN_SHIFT) +#define RTC_IRQ_EN_ONESHOT (MT6685_ONESHOT_MASK << MT6685_ONESHOT_SHIFT) +#define RTC_IRQ_EN_LP (MT6685_LP_EN_MASK << MT6685_LP_EN_SHIFT) +#define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL) + +#define RTC_CII_EN MT6685_SECCII_ADDR +#define RTC_CII_SEC (MT6685_SECCII_MASK << MT6685_SECCII_SHIFT) +#define RTC_CII_MIN (MT6685_MINCII_MASK << MT6685_MINCII_SHIFT) +#define RTC_CII_HOU (MT6685_HOUCII_MASK << MT6685_HOUCII_SHIFT) +#define RTC_CII_DOM (MT6685_DOMCII_MASK << MT6685_DOMCII_SHIFT) +#define RTC_CII_DOW (MT6685_DOWCII_MASK << MT6685_DOWCII_SHIFT) +#define RTC_CII_MTH (MT6685_MTHCII_MASK << MT6685_MTHCII_SHIFT) +#define RTC_CII_YEA (MT6685_YEACII_MASK << MT6685_YEACII_SHIFT) +#define RTC_CII_1_2_SEC (MT6685_SECCII_1_2_MASK << MT6685_SECCII_1_2_SHIFT) +#define RTC_CII_1_4_SEC (MT6685_SECCII_1_4_MASK << (MT6685_SECCII_1_4_SHIFT + 8)) +#define RTC_CII_1_8_SEC (MT6685_SECCII_1_8_MASK << (MT6685_SECCII_1_8_SHIFT + 8)) + +#define RTC_AL_MASK MT6685_SEC_MSK_ADDR +#define RTC_AL_MASK_SEC (MT6685_SEC_MSK_MASK << MT6685_SEC_MSK_SHIFT) +#define RTC_AL_MASK_MIN (MT6685_MIN_MSK_MASK << MT6685_MIN_MSK_SHIFT) +#define RTC_AL_MASK_HOU (MT6685_HOU_MSK_MASK << MT6685_HOU_MSK_SHIFT) +#define RTC_AL_MASK_DOM (MT6685_DOM_MSK_MASK << MT6685_DOM_MSK_SHIFT) +#define RTC_AL_MASK_DOW (MT6685_DOW_MSK_MASK << MT6685_DOW_MSK_SHIFT) +#define RTC_AL_MASK_MTH (MT6685_MTH_MSK_MASK << MT6685_MTH_MSK_SHIFT) +#define RTC_AL_MASK_YEA (MT6685_YEA_MSK_MASK << MT6685_YEA_MSK_SHIFT) + +#define RTC_TC_SEC MT6685_TC_SECOND_ADDR +#define RTC_TC_SEC_MASK MT6685_TC_SECOND_MASK +#define RTC_TC_MIN MT6685_TC_MINUTE_ADDR +#define RTC_TC_MIN_MASK MT6685_TC_MINUTE_MASK +#define RTC_TC_HOU MT6685_TC_HOUR_ADDR +#define RTC_TC_HOU_MASK MT6685_TC_HOUR_MASK +#define RTC_TC_DOM MT6685_TC_DOM_ADDR +#define RTC_TC_DOM_MASK MT6685_TC_DOM_MASK +#define RTC_TC_DOW MT6685_TC_DOW_ADDR +#define RTC_TC_DOW_MASK MT6685_TC_DOW_MASK +#define RTC_TC_MTH MT6685_TC_MONTH_ADDR +#define RTC_TC_MTH_MASK MT6685_TC_MONTH_MASK +#define RTC_TC_YEA MT6685_TC_YEAR_ADDR +#define RTC_TC_YEA_MASK MT6685_TC_YEAR_MASK +#define RTC_AL_SEC MT6685_AL_SECOND_ADDR +#define RTC_AL_SEC_MASK MT6685_AL_SECOND_MASK + +#define RTC_BBPU_AUTO_PDN_SEL (MT6685_BBPU_AUTO_PDN_SEL_MASK << MT6685_BBPU_AUTO_PDN_SEL_SHIFT) +#define RTC_BBPU_2SEC_CK_SEL (MT6685_BBPU_2SEC_CK_SEL_MASK << MT6685_BBPU_2SEC_CK_SEL_SHIFT) +#define RTC_BBPU_2SEC_EN (MT6685_BBPU_2SEC_EN_MASK << (MT6685_BBPU_2SEC_EN_SHIFT + 8)) +#define RTC_BBPU_2SEC_MODE (MT6685_BBPU_2SEC_MODE_MASK << (MT6685_BBPU_2SEC_MODE_SHIFT + 8)) +/* RTC mask include shift */ +#define RTC_BBPU_2SEC_MODE_MSK (MT6685_BBPU_2SEC_MODE_MASK << (MT6685_BBPU_2SEC_MODE_SHIFT + 8)) +#define RTC_BBPU_2SEC_MODE_SHIFT (MT6685_BBPU_2SEC_MODE_SHIFT + 8) +#define RTC_BBPU_2SEC_STAT_CLEAR (MT6685_BBPU_2SEC_STAT_CLEAR_MASK << (MT6685_BBPU_2SEC_STAT_CLEAR_SHIFT + 8)) +#define RTC_BBPU_2SEC_STAT_STA (MT6685_BBPU_2SEC_STAT_STA_MASK << (MT6685_BBPU_2SEC_STAT_STA_SHIFT + 8)) +#define RTC_LPD_OPT_SHIFT (MT6685_RTC_LPD_OPT_SHIFT + 8) +#define RTC_LPD_OPT_MASK (MT6685_RTC_LPD_OPT_MASK << (MT6685_RTC_LPD_OPT_SHIFT + 8)) +#define RTC_LPD_OPT_XOSC_AND_EOSC_LPD (0U << (MT6685_RTC_LPD_OPT_SHIFT + 8)) +#define RTC_LPD_OPT_EOSC_LPD (1U << (MT6685_RTC_LPD_OPT_SHIFT + 8)) +#define RTC_LPD_OPT_XOSC_LPD (2U << (MT6685_RTC_LPD_OPT_SHIFT + 8)) +#define RTC_LPD_OPT_F32K_CK_ALIVE (3U << (MT6685_RTC_LPD_OPT_SHIFT + 8)) +#define RTC_K_EOSC32_VTCXO_ON_SEL (MT6685_K_EOSC32_VTCXO_ON_SEL_MASK << (MT6685_K_EOSC32_VTCXO_ON_SEL_SHIFT + 8)) + +#define RTC_AL_MIN MT6685_AL_MINUTE_ADDR +#define RTC_AL_MIN_MASK (MT6685_AL_MINUTE_MASK << MT6685_AL_MINUTE_SHIFT) + +/* + * RTC_NEW_SPARE0: RTC_AL_HOU bit0~4 + * bit 8 ~ 15 : For design used, can't be overwritten. + */ +#define RTC_AL_HOU MT6685_AL_HOUR_ADDR +#define RTC_AL_HOU_MASK (MT6685_AL_HOUR_MASK << MT6685_AL_HOUR_SHIFT) +#define RTC_NEW_SPARE0 (MT6685_NEW_SPARE0_MASK << (MT6685_NEW_SPARE0_SHIFT + 8)) +#define RTC_AL_HOU_FG_SHIFT 8 +#define RTC_AL_HOU_FG_MASK 0xff00 + +/* + * RTC_NEW_SPARE1: RTC_AL_DOM bit0~4 + * bit 8 ~ 15 : for 2 second reboot desing used, + * can't be overwritten. + */ +#define RTC_AL_DOM MT6685_AL_DOM_ADDR +#define RTC_AL_DOM_MASK (MT6685_AL_DOM_MASK << MT6685_AL_DOM_SHIFT) +#define RTC_NEW_SPARE1 (MT6685_NEW_SPARE1_MASK << (MT6685_NEW_SPARE1_SHIFT + 8)) +#define RTC_SPAR_CONDITION BIT(8) /* by uvlo */ +#define RTC_AUTOMATICALLY_SPAR BIT(9) /* clear by sw */ +#define RTC_ALARM_CLEAR_METHOD BIT(11) /* by sw */ + +/* + * RTC_NEW_SPARE2: RTC_AL_DOW bit0~2 + * bit 8 ~ 15 : reserved bits + */ +#define RTC_AL_DOW MT6685_AL_DOW_ADDR +#define RTC_AL_DOW_MASK (MT6685_AL_DOW_MASK << MT6685_AL_DOW_SHIFT) +#define RTC_RG_EOSC_CALI_TD_1SEC (3 << (MT6685_NEW_SPARE2_SHIFT + 8)) +#define RTC_RG_EOSC_CALI_TD_2SEC (4 << (MT6685_NEW_SPARE2_SHIFT + 8)) +#define RTC_RG_EOSC_CALI_TD_4SEC (5 << (MT6685_NEW_SPARE2_SHIFT + 8)) +#define RTC_RG_EOSC_CALI_TD_8SEC (6 << (MT6685_NEW_SPARE2_SHIFT + 8)) +#define RTC_RG_EOSC_CALI_TD_16SEC (7 << (MT6685_NEW_SPARE2_SHIFT + 8)) +#define RTC_RG_EOSC_CALI_TD_MASK (0x7 << (MT6685_NEW_SPARE2_SHIFT + 8)) +#define RTC_NEW_SPARE2 (MT6685_NEW_SPARE2_MASK << (MT6685_NEW_SPARE2_SHIFT + 8)) + +/* + * RTC_NEW_SPARE3: RTC_AL_MTH bit0~3 + * bit 8 ~ 15 : Fuel Gauge + */ +#define RTC_AL_MTH MT6685_AL_MONTH_ADDR +#define RTC_AL_MTH_MASK (MT6685_AL_MONTH_MASK << MT6685_AL_MONTH_SHIFT) +#define RTC_NEW_SPARE3 (MT6685_NEW_SPARE3_MASK << (MT6685_NEW_SPARE3_SHIFT + 8)) +#define RTC_AL_MTH_FG_SHIFT 8 +#define RTC_AL_MTH_FG_MASK 0xff00 + +#define RTC_AL_YEA MT6685_AL_YEAR_ADDR +#define RTC_AL_YEA_MASK (MT6685_AL_YEAR_MASK << MT6685_AL_YEAR_SHIFT) +#define RTC_K_EOSC_RSV_0 BIT(8) +#define RTC_K_EOSC_RSV_1 BIT(9) +#define RTC_K_EOSC_RSV_2 BIT(10) +#define RTC_K_EOSC_RSV_3 BIT(11) +#define RTC_K_EOSC_RSV_4 BIT(12) +#define RTC_K_EOSC_RSV_5 BIT(13) +#define RTC_K_EOSC_RSV_6 BIT(14) +#define RTC_K_EOSC_RSV_7 BIT(15) + +#define RTC_OSC32CON MT6685_XOSCCALI_ADDR +#define RTC_OSC32CON_UNLOCK1 0x1a57 +#define RTC_OSC32CON_UNLOCK2 0x2b68 + +/* Default 4'b0111, 2nd step suggest to set to 4'b0000 EOSC_CALI = charging cap calibration */ +#define RTC_XOSCCALI_MASK (MT6685_XOSCCALI_MASK << MT6685_XOSCCALI_SHIFT) + +/* 0 (32k crystal exist) 1 (32k crystal doesn't exist)*/ +#define RTC_XOSC32_ENB (MT6685_RTC_XOSC32_ENB_MASK << MT6685_RTC_XOSC32_ENB_SHIFT) +#define RTC_EMBCK_SEL_MODE (MT6685_RTC_EMBCK_SEL_MODE_MASK << MT6685_RTC_EMBCK_SEL_MODE_SHIFT) +#define RTC_EMBCK_SRC_SEL (MT6685_RTC_EMBCK_SRC_SEL_MASK << (MT6685_RTC_EMBCK_SRC_SEL_SHIFT + 8)) +#define RTC_EMBCK_SEL_OPTION (MT6685_RTC_EMBCK_SEL_OPTION_MASK << (MT6685_RTC_EMBCK_SEL_OPTION_SHIFT + 8)) +#define RTC_GPS_CKOUT_EN (MT6685_RTC_GPS_CKOUT_EN_MASK << (MT6685_RTC_GPS_CKOUT_EN_SHIFT + 8)) +#define RTC_EOSC32_VCT_EN (MT6685_RTC_EOSC32_VCT_EN_MASK << (MT6685_RTC_EOSC32_VCT_EN_SHIFT + 8)) +#define RTC_EOSC32_CHOP_EN (MT6685_RTC_EOSC32_CHOP_EN_MASK << (MT6685_RTC_EOSC32_CHOP_EN_SHIFT + 8)) + +/* Keep RG_EOSC_RSV[0] to low for lower EOSC leakage current hardware design change. */ +#define RTC_GP_OSC32_CON (2U << (MT6685_RTC_GP_OSC32_CON_SHIFT + 8)) +#define RTC_REG_XOSC32_ENB (MT6685_RTC_REG_XOSC32_ENB_MASK << (MT6685_RTC_REG_XOSC32_ENB_SHIFT + 8)) + +/* 0: emb_hw 1: emb_k_eosc_32 2:dcxo_ck 3: eosc32_ck*/ +#define RTC_EMBCK_SEL_HW (0 << MT6685_RTC_EMBCK_SEL_MODE_SHIFT) +#define RTC_EMBCK_SEL_K_EOSC (1U << MT6685_RTC_EMBCK_SEL_MODE_SHIFT) +#define RTC_EMBCK_SEL_DCXO (2U << MT6685_RTC_EMBCK_SEL_MODE_SHIFT) +#define RTC_EMBCK_SEL_EOSC (3U << MT6685_RTC_EMBCK_SEL_MODE_SHIFT) + +#define OSC32CON_ANALOG_SETTING (RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN | \ + RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | \ + RTC_EMBCK_SEL_OPTION | RTC_EMBCK_SEL_K_EOSC) + +#define RTC_XOSCCALI_START 0x0000 +#define RTC_XOSCCALI_END 0x001f + +#define RTC_POWERKEY1 MT6685_RTC_POWERKEY1_L_ADDR +#define RTC_POWERKEY2 MT6685_RTC_POWERKEY2_L_ADDR +#define RTC_POWERKEY1_KEY 0xa357 +#define RTC_POWERKEY2_KEY 0x67d2 + +#define RTC_PDN1 MT6685_RTC_PDN1_L_ADDR +#define RTC_PDN1_RECOVERY_MASK 0x0030 +#define RTC_PDN1_FAC_RESET BIT(4) +#define RTC_PDN1_BYPASS_PWR BIT(6) +#define RTC_PDN1_PWRON_TIME BIT(7) +#define RTC_PDN1_FAST_BOOT BIT(13) +#define RTC_PDN1_KPOC BIT(14) +#define RTC_PDN1_DEBUG BIT(15) + +#define RTC_PDN2 MT6685_RTC_PDN2_L_ADDR +#define RTC_PDN2_PWRON_MTH_MASK 0x000f +#define RTC_PDN2_PWRON_MTH_SHIFT 0 +#define RTC_PDN2_PWRON_ALARM BIT(4) +#define RTC_PDN2_PWRON_YEA_MASK 0x7f00 +#define RTC_PDN2_AUTOBOOT BIT(7) +#define RTC_PDN2_PWRON_YEA_SHIFT 8 +#define RTC_PDN2_PWRON_LOGO BIT(15) + +#define RTC_SPAR0 MT6685_RTC_SPAR0_L_ADDR +#define RTC_SPAR0_PWRON_SEC_MASK 0x003f +#define RTC_SPAR0_PWRON_SEC_SHIFT 0 +#define RTC_SPAR0_32K_LESS BIT(6) + +#define RTC_SPAR1 MT6685_RTC_SPAR1_L_ADDR +#define RTC_SPAR1_PWRON_MIN_MASK 0x003f +#define RTC_SPAR1_PWRON_MIN_SHIFT 0 +#define RTC_SPAR1_PWRON_HOU_MASK 0x07c0 +#define RTC_SPAR1_PWRON_HOU_SHIFT 6 +#define RTC_SPAR1_PWRON_DOM_MASK 0xf800 +#define RTC_SPAR1_PWRON_DOM_SHIFT 11 + +#define RTC_PROT MT6685_RTC_PROT_L_ADDR +#define RTC_PROT_UNLOCK1 0x586a +#define RTC_PROT_UNLOCK2 0x9136 +#define RTC_PROT_UNLOCK_SUCCESS 0x3 + +#define RTC_DIFF MT6685_RTC_DIFF_L_ADDR +#define RTC_POWER_DETECTED (MT6685_POWER_DETECTED_MASK << (MT6685_POWER_DETECTED_SHIFT + 8)) +#define RTC_K_EOSC32_RSV (MT6685_K_EOSC32_RSV_MASK << (MT6685_K_EOSC32_RSV_SHIFT + 8)) +#define RTC_CALI_RD_SEL_SHIFT (MT6685_CALI_RD_SEL_SHIFT + 8) +#define RTC_CALI_RD_SEL (MT6685_CALI_RD_SEL_MASK << (MT6685_CALI_RD_SEL_SHIFT + 8)) + +#define RTC_CALI MT6685_RTC_CALI_L_ADDR +#define RTC_CALI_MASK (MT6685_RTC_CALI_H_MASK << (MT6685_RTC_CALI_H_SHIFT + 8) | \ + MT6685_RTC_CALI_L_MASK << MT6685_RTC_CALI_L_SHIFT) + +#define RTC_CALI_WR_SEL (MT6685_CALI_WR_SEL_MASK << (MT6685_CALI_WR_SEL_SHIFT + 8)) +#define RTC_CALI_WR_SEL_SHIFT (MT6685_CALI_WR_SEL_SHIFT + 8) +#define RTC_K_EOSC32_OVERFLOW (MT6685_K_EOSC32_OVERFLOW_MASK << (MT6685_K_EOSC32_OVERFLOW_SHIFT + 8)) + +#define RTC_WRTGR MT6685_WRTGR_ADDR + +#define RTC_CON MT6685_VBAT_LPSTA_RAW_ADDR +#define RTC_VBAT_LPSTA_RAW (MT6685_VBAT_LPSTA_RAW_MASK << MT6685_VBAT_LPSTA_RAW_SHIFT) +#define RTC_EOSC32_LPEN (MT6685_EOSC32_LPEN_MASK << MT6685_EOSC32_LPEN_SHIFT) +#define RTC_XOSC32_LPEN (MT6685_XOSC32_LPEN_MASK << MT6685_XOSC32_LPEN_SHIFT) +#define RTC_CON_LPRST (MT6685_LPRST_MASK << MT6685_LPRST_SHIFT) +#define RTC_CON_CDBO (MT6685_CDBO_MASK << MT6685_CDBO_SHIFT) +/* 0: RTC_GPIO exports 32K */ +#define RTC_CON_F32KOB (MT6685_F32KOB_MASK << MT6685_F32KOB_SHIFT) +#define RTC_CON_GPO (MT6685_GPO_MASK << MT6685_GPO_SHIFT) +/* 1: GPO mode, 0: GPI mode */ +#define RTC_CON_GOE (MT6685_GOE_MASK << MT6685_GOE_SHIFT) +#define RTC_CON_GSR (MT6685_GSR_MASK << (MT6685_GSR_SHIFT + 8)) +#define RTC_CON_GSMT (MT6685_GSMT_MASK << (MT6685_GSMT_SHIFT + 8)) +#define RTC_CON_GPEN (MT6685_GPEN_MASK << (MT6685_GPEN_SHIFT + 8)) +#define RTC_CON_GPU (MT6685_GPU_MASK << (MT6685_GPU_SHIFT + 8)) +#define RTC_CON_GE4 (MT6685_GE4_MASK << (MT6685_GE4_SHIFT + 8)) +#define RTC_CON_GE8 (MT6685_GE8_MASK << (MT6685_GE8_SHIFT + 8)) +#define RTC_CON_GPI (MT6685_GPI_MASK << (MT6685_GPI_SHIFT + 8)) +/* 32K was stopped */ +#define RTC_CON_LPSTA_RAW (MT6685_LPSTA_RAW_MASK << (MT6685_LPSTA_RAW_SHIFT + 8)) + +#define RTC_INT_CNT MT6685_RTC_INT_CNT_L_ADDR + +#define SCK_TOP_CKPDN_CON0_L_SET MT6685_SCK_TOP_CKPDN_CON0_L_SET_ADDR +#define RG_RTC_EOSC32_CK_PDN_MASK MT6685_RG_RTC_EOSC32_CK_PDN_MASK +#define RG_RTC_EOSC32_CK_PDN_SHIFT MT6685_RG_RTC_EOSC32_CK_PDN_SHIFT + +#define SCK_TOP_CKPDN_CON0_L_CLR MT6685_SCK_TOP_CKPDN_CON0_L_CLR_ADDR +#define SCK_TOP_CKPDN_CON0_L_CLR_SHIFT MT6685_SCK_TOP_CKPDN_CON0_L_CLR_SHIFT + +#define SCK_TOP_CKPDN_CON0_L MT6685_SCK_TOP_CKPDN_CON0_L +#define RG_RTC_SEC_MCLK_PDN_MASK MT6685_RG_RTC_SEC_MCLK_PDN_MASK +#define RG_RTC_SEC_32K_CK_PDN_MASK MT6685_RG_RTC_SEC_32K_CK_PDN_MASK +#define RG_RTC_SEC_32K_CK_PDN_SHIFT MT6685_RG_RTC_SEC_32K_CK_PDN_SHIFT + +#define SCK_TOP_XTAL_SEL_ADDR MT6685_SCK_TOP_XTAL_SEL_ADDR +#define SCK_TOP_XTAL_SEL_MASK MT6685_SCK_TOP_XTAL_SEL_MASK +#define SCK_TOP_XTAL_SEL_SHIFT MT6685_SCK_TOP_XTAL_SEL_SHIFT + +#define TOP_RST_MISC_CLR MT6685_TOP_RST_MISC_CLR_ADDR +#define TOP_RST_MISC_CLR_MASK MT6685_TOP_RST_MISC_CLR_MASK +#define TOP_RST_MISC_CLR_SHIFT MT6685_TOP_RST_MISC_CLR_SHIFT + +#define TMA_KEY MT6685_TMA_KEY_ADDR +#define TMA_KEY_MASK MT6685_TMA_KEY_MASK +#define TMA_KEY_SHIFT MT6685_TMA_KEY_SHIFT + +#define TMA_KEY_H MT6685_TMA_KEY_H_ADDR +#define TMA_KEY_H_MASK MT6685_TMA_KEY_H_MASK +#define TMA_KEY_H_SHIFT MT6685_TMA_KEY_H_SHIFT + +#define TOP_DIG_WPK MT6685_TOP_DIG_WPK +#define DIG_WPK_KEY_MASK MT6685_DIG_WPK_KEY_MASK +#define DIG_WPK_KEY_SHIFT MT6685_DIG_WPK_KEY_SHIFT + +#define TOP_DIG_WPK_H MT6685_TOP_DIG_WPK_H +#define DIG_WPK_KEY_H_MASK MT6685_DIG_WPK_KEY_H_MASK +#define DIG_WPK_KEY_H_SHIFT MT6685_DIG_WPK_KEY_H_SHIFT + +#define RG_RTC_MCLK_PDN_SET MT6685_SCK_TOP_CKPDN_CON0_L_SET +#define RG_RTC_MCLK_PDN_CLR MT6685_SCK_TOP_CKPDN_CON0_L_CLR +#define RG_RTC_MCLK_PDN_MASK MT6685_RG_RTC_MCLK_PDN_MASK +#define RG_RTC_MCLK_PDN_SHIFT MT6685_RG_RTC_MCLK_PDN_SHIFT + +#define RG_SHUTDOWN_SRC_SEL MT6685_RG_SHUTDOWN_SRC_SEL_ADDR +#define RG_SHUTDOWN_SRC_SEL_MASK MT6685_RG_SHUTDOWN_SRC_SEL_MASK +#define RG_SHUTDOWN_SRC_SEL_SHIFT MT6685_RG_SHUTDOWN_SRC_SEL_SHIFT + +#define RG_SRCLKEN_IN0_HW_MODE MT6685_TOP_CON +#define RG_SRCLKEN_IN0_HW_MODE_MASK MT6685_RG_SRCLKEN_IN0_HW_MODE_MASK +#define RG_SRCLKEN_IN0_HW_MODE_SHIFT MT6685_RG_SRCLKEN_IN0_HW_MODE_SHIFT + +#define RG_SRCLKEN_IN1_HW_MODE MT6685_TOP_CON +#define RG_SRCLKEN_IN1_HW_MODE_MASK MT6685_RG_SRCLKEN_IN1_HW_MODE_MASK +#define RG_SRCLKEN_IN1_HW_MODE_SHIFT MT6685_RG_SRCLKEN_IN1_HW_MODE_SHIFT + +#define RG_RTC_EOSC32_CK_PDN MT6685_SCK_TOP_CKPDN_CON0_L +#define RG_RTC_EOSC32_CK_PDN_MASK MT6685_RG_RTC_EOSC32_CK_PDN_MASK +#define RG_RTC_EOSC32_CK_PDN_SHIFT MT6685_RG_RTC_EOSC32_CK_PDN_SHIFT + +#define XO_EN32K_MAN_ADDR MT6685_DCXO_DIG_MODE_CW0 +#define XO_EN32K_MAN_MASK MT6685_XO_EN32K_MAN_MASK +#define XO_EN32K_MAN_SHIFT MT6685_XO_EN32K_MAN_SHIFT + +#define SCK_TOP_CKSEL_CON MT6685_SCK_TOP_CKSEL_CON +#define R_SCK32K_CK_MASK 0x1 +#define R_SCK32K_CK_SHIFT 0 + +#define RTC_SPAR_MACRO MT6685_RTC_SPAR_MACRO +#define SPAR_THRE_SEL (MT6685_RTC_SPAR_THRE_SEL_MASK << MT6685_RTC_SPAR_THRE_SEL_SHIFT) +#define SPAR_UVLO_WAIT_SHIFT MT6685_RTC_UVLO_WAIT_SHIFT +#define SPAR_UVLO_WAIT_1T 0x0 +#define SPAR_UVLO_WAIT_4ms 0x1 +#define SPAR_UVLO_WAIT_16ms 0x2 +#define SPAR_UVLO_WAIT_32ms 0x3 +#define RTC_SPAR_PWRKEY_MATCH_LPD_MASK 0x1 +#define RTC_SPAR_PWRKEY_MATCH_LPD_SHIFT 4 +#define RTC_SPAR_PWRKEY_MATCH_MASK 0x1 +#define RTC_SPAR_PWRKEY_MATCH_SHIFT 5 +#define RTC_SPAR_PROT_STAT_MASK 0x3 +#define RTC_SPAR_PROT_STAT_SHIFT 6 + +/* Secure RTC */ +#define RTC_TC_SEC_SEC MT6685_TC_SECOND_SEC_ADDR +#define RTC_TC_MIN_SEC MT6685_TC_MINUTE_SEC_ADDR +#define RTC_TC_HOU_SEC MT6685_TC_HOUR_SEC_ADDR +#define RTC_TC_DOM_SEC MT6685_TC_DOM_SEC_ADDR +#define RTC_TC_DOW_SEC MT6685_TC_DOW_SEC_ADDR +#define RTC_TC_MTH_SEC MT6685_TC_MONTH_SEC_ADDR +#define RTC_TC_YEA_SEC MT6685_TC_YEAR_SEC_ADDR + +#define RTC_WRTGR_SEC MT6685_RTC_SEC_WRTGR_ADDR +#define RTC_SEC_CK_PDN MT6685_RTC_SEC_CK_PDN_ADDR + +#define RTC_SEC_DSN_REV0 MT6685_RTC_SEC_ANA_REV +#define RTC_SEC_DSN_ID MT6685_RTC_SEC_ANA_ID + +#define RTC_SEC_BAS RTC_SEC_DSN_ID + +#endif /* SOC_MEDIATEK_MT8196_MT6685_RTC_HW_H */ diff --git a/src/soc/mediatek/mt8196/include/soc/rtc.h b/src/soc/mediatek/mt8196/include/soc/rtc.h new file mode 100644 index 0000000..3b778e2 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/rtc.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 14.2.4 + */ + +#ifndef SOC_MEDIATEK_MT8196_RTC_H +#define SOC_MEDIATEK_MT8196_RTC_H + +#include <soc/rtc_common.h> +#include <soc/rtc_reg_common.h> +#include <stdbool.h> +#include <types.h> + +/* RTC registers */ +enum { + RTC_BBPU_PWREN = BIT(0), + RTC_BBPU_CLRPKY = BIT(4), + RTC_BBPU_RELOAD = BIT(5), + RTC_BBPU_CBUSY = BIT(6), + + RTC_CBUSY_TIMEOUT_US = 8000, +}; + +enum { + RTC_XOSCCALI_MASK = 0x1F << 0, + RTC_XOSC32_ENB = BIT(5), + RTC_EMBCK_SEL_MODE_MASK = 3U << 6, + RTC_EMBCK_SRC_SEL = BIT(8), + RTC_EMBCK_SEL_OPTION = BIT(9), + RTC_GPS_CKOUT_EN = BIT(10), + RTC_REG_XOSC32_ENB = BIT(15), +}; + +/* PMIC Frequency Meter Definition */ +enum { + PMIC_RG_FQMTR_CKSEL = 0x0118, + PMIC_RG_FQMTR_RST = 0x013E, + PMIC_RG_FQMTR_CON0 = 0x0514, + PMIC_RG_FQMTR_WINSET = 0x0516, + PMIC_RG_FQMTR_DATA = 0x0518, + + FQMTR_TIMEOUT_US = 100000, +}; + +enum { + PMIC_FQMTR_FIX_CLK_26M = 0U, + PMIC_FQMTR_FIX_CLK_XOSC_32K_DET = 1U, + PMIC_FQMTR_FIX_CLK_EOSC_32K = 2U, + PMIC_FQMTR_FIX_CLK_RTC_32K = 3U, + PMIC_FQMTR_FIX_CLK_SMPS_CK = 4U, + PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U, + PMIC_FQMTR_FIX_CLK_PMU_75K = 6U, + PMIC_FQMTR_CKSEL_MASK = 7U, +}; + +#define WATCH_INIT_EXPIRED_TIME 100000 +#define WAIT_TIME_US 1000000 +#define RETRY_MAX_TIME 3 + +struct rtc_clk_freq { + u16 freq[3]; +}; + +int rtc_init(int recover); +bool rtc_gpio_init(void); +//void rtc_boot(void); +u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size); +void rtc_get_time(struct rtc_time *tm); +void rtc_read(u16 addr, u16 *rdata); +void rtc_write(u16 addr, u16 wdata); + +#endif /* SOC_MEDIATEK_MT8196_RTC_H */ diff --git a/src/soc/mediatek/mt8196/mt6685_rtc.c b/src/soc/mediatek/mt8196/mt6685_rtc.c new file mode 100644 index 0000000..a33bdd3 --- /dev/null +++ b/src/soc/mediatek/mt8196/mt6685_rtc.c @@ -0,0 +1,663 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * This file is created based on MT8196 Functional Specification + * Chapter number: 14.2.4 + */ + +#include <commonlib/bsd/bcd.h> +#include <console/console.h> +#include <delay.h> +#include <soc/rtc.h> +#include <soc/mt6685.h> +#include <soc/mt6685_rtc.h> +#include <soc/mt6685_hw.h> +#include <soc/mt6685_rtc_hw.h> +#include <soc/mt6685.h> +#include <soc/pmif.h> +#include <soc/spmi.h> +#include <stdbool.h> +#include <timer.h> + +static u16 config_interface_read(u16 addr) +{ + return mt6685_read_field(addr, 0xff, 0); +} + +static void config_interface(u16 addr, u16 val, u16 mask, u16 shift) +{ + mt6685_write_field(addr, val, mask, shift); +} + +void rtc_read(u16 addr, u16 *rdata) +{ + *rdata = mt6685_read16(addr); +} + +void rtc_write(u16 addr, u16 wdata) +{ + mt6685_write16(addr, wdata); +} + +static bool rtc_eosc_check_clock(const struct rtc_clk_freq *result) +{ + if ((result->freq[0] >= 3 && result->freq[0] <= 7) && + (result->freq[1] > 2 && result->freq[1] < 9) && + (result->freq[2] > 300 && result->freq[2] < 10400)) + return true; + else + return false; +} + +u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) +{ + u16 ret; + u16 osc32con; + u16 rdata; + + if (val != 0) { + rtc_read(RTC_BBPU, &rdata); + rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + rtc_read(RTC_OSC32CON, &rdata); + osc32con = rdata & 0xFFE0; + rtc_xosc_write(osc32con | (val & RTC_XOSCCALI_MASK)); + } + + /* RG_BANK_FQMTR_RST = 1 reset FQMTR */ + config_interface(RG_BANK_FQMTR_RST, 1, RG_BANK_FQMTR_RST_MASK, + RG_BANK_FQMTR_RST_SHIFT); + udelay(20); + /* RG_BANK_FQMTR_RST = 0 release FQMTR */ + config_interface(RG_BANK_FQMTR_RST, 0, RG_BANK_FQMTR_RST_MASK, + RG_BANK_FQMTR_RST_SHIFT); + + /* Write Protection Key to unlock TOP_CKPDN_CON0 */ + config_interface(TOP_DIG_WPK, 0x15, DIG_WPK_KEY_MASK, DIG_WPK_KEY_SHIFT); + config_interface(TOP_DIG_WPK_H, 0x63, DIG_WPK_KEY_H_MASK, DIG_WPK_KEY_H_SHIFT); + + config_interface(RG_FQMTR_CLK_CK_PDN_CLR, 1, RG_FQMTR_CLK_CK_PDN_MASK, + RG_FQMTR_CLK_CK_PDN_SHIFT); + config_interface(RG_FQMTR_32K_CK_PDN_CLR, 1, RG_FQMTR_32K_CK_PDN_MASK, + RG_FQMTR_32K_CK_PDN_SHIFT); + + config_interface(RG_FQMTR_DCXO26M_EN, 1, RG_FQMTR_DCXO26M_MASK, + RG_FQMTR_DCXO26M_SHIFT); + + /* Set freq meter window value (0=1X32K(fix clock)) */ + rtc_write(RG_FQMTR_WINSET, window_size); + + /* Enable 26M and set test clock source */ + config_interface(RG_FQMTR_TCKSEL, FQMTR_DCXO26M_EN | measure_src, + RG_FQMTR_TCKSEL_MASK, RG_FQMTR_TCKSEL_SHIFT); + + udelay(100); + + /* Enable FQMTR */ + config_interface(RG_FQMTR_EN, 1, RG_FQMTR_EN_MASK, RG_FQMTR_EN_SHIFT); + udelay(100); + + /* FQMTR read until ready */ + if (!wait_us(FQMTR_TIMEOUT_US, + !((rtc_read(RG_FQMTR_BUSY, &rdata), rdata) & FQMTR_BUSY))) { + printk(BIOS_ERR, "%s: ERROR: get frequency time out\n", __func__); + return false; + } + + /* read data should be closed to 26M/32k = 794 */ + rtc_read(RG_FQMTR_DATA, &rdata); + ret = rdata; + + config_interface(RG_FQMTR_DCXO26M_EN, 0, + RG_FQMTR_DCXO26M_MASK, RG_FQMTR_DCXO26M_SHIFT); + config_interface(RG_FQMTR_TCKSEL, 0, + RG_FQMTR_DCXO26M_MASK, RG_FQMTR_DCXO26M_SHIFT); + udelay(100); + + /* Disable FQMTR */ + config_interface(RG_FQMTR_EN, 0, RG_FQMTR_EN_MASK, RG_FQMTR_EN_SHIFT); + + printk(BIOS_INFO, "%s: input=%#x, output=%u\n", __func__, val, rdata); + + config_interface(RG_FQMTR_CLK_CK_PDN_SET, 1, + RG_FQMTR_CLK_CK_PDN_MASK, RG_FQMTR_CLK_CK_PDN_SHIFT); + config_interface(RG_FQMTR_32K_CK_PDN_SET, 1, + RG_FQMTR_32K_CK_PDN_MASK, RG_FQMTR_32K_CK_PDN_SHIFT); + + return ret; +} + +static void rtc_measure_four_clock(struct rtc_clk_freq *result) +{ + config_interface(RG_FQMTR_CKSEL, FQMTR_FIX_CLK_26M, RG_FQMTR_CKSEL_MASK, + RG_FQMTR_CKSEL_SHIFT); + udelay(100); + /* Select 26M as target clock */ + result->freq[0] = rtc_get_frequency_meter(0, FQMTR_FQM26M_CK, 4); + + config_interface(RG_FQMTR_CKSEL, FQMTR_FIX_CLK_26M, RG_FQMTR_CKSEL_MASK, + RG_FQMTR_CKSEL_SHIFT); + + udelay(100); + /* Select DCXO_32 as target clock */ + result->freq[1] = rtc_get_frequency_meter(0, FQMTR_DCXO_F32K_CK, 3970); + + config_interface(RG_FQMTR_CKSEL, FQMTR_FIX_CLK_EOSC_32K, RG_FQMTR_CKSEL_MASK, + RG_FQMTR_CKSEL_SHIFT); + udelay(100); + /* Select 26M as target clock */ + result->freq[2] = rtc_get_frequency_meter(0, FQMTR_FQM26M_CK, 4); +} + +static bool rtc_frequency_meter_check(void) +{ + struct rtc_clk_freq result; + u16 osc32con, val; + + if (!wait_us(WAIT_TIME_US, + (rtc_measure_four_clock(&result), rtc_eosc_check_clock(&result)))) { + printk(BIOS_ERR, "%s: eosc clock check time out!\n", __func__); + return false; + } + + val = rtc_eosc_cali(); + printk(BIOS_INFO, "EOSC cali val = %#x\n", val); + /* ENB_HW_Mode */ + osc32con = OSC32CON_ANALOG_SETTING | RTC_REG_XOSC32_ENB; + val = (val & RTC_XOSCCALI_MASK) | osc32con; + printk(BIOS_INFO, "EOSC cali val = %#x\n", val); + rtc_xosc_write(val); + + return true; +} + +static bool rtc_clr_clrset_trigger(u16 addr, u32 clr_bits, u32 set_bits) +{ + u16 rdata; + + rtc_read(addr, &rdata); + + rdata &= ~clr_bits; + rdata |= set_bits; + + rtc_write(addr, rdata); + + return rtc_write_trigger(); +} + +bool rtc_gpio_init(void) +{ + /* GPI mode and pull enable + pull down */ + rtc_clr_clrset_trigger(RTC_CON, RTC_CON_GPU | RTC_CON_F32KOB | + ~(RTC_CON_LPSTA_RAW | RTC_CON_LPRST | + RTC_XOSC32_LPEN | RTC_EOSC32_LPEN), + RTC_CON_GPEN | RTC_CON_GOE); + + return rtc_write_trigger(); +} + +static bool rtc_hw_init(void) +{ + struct stopwatch sw; + u16 rdata; + + stopwatch_init_usecs_expire(&sw, WATCH_INIT_EXPIRED_TIME); + + rtc_read(RTC_BBPU, &rdata); + rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RESET_ALARM | + (RTC_BBPU_RESET_SPAR & (~RTC_BBPU_SPAR_SW))); + rtc_write_trigger(); + + do { + rtc_read(RTC_BBPU, &rdata); + rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + rtc_read(RTC_BBPU, &rdata); + + if (!(rdata & (RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR))) + return true; + + } while (!stopwatch_expired(&sw)); + + printk(BIOS_INFO, "%s time out!\n", __func__); + + return false; +} + +static bool rtc_lpd_init(void) +{ + u16 con; + u16 rdata; + + /* Enable EOSC LPD only */ + printk(BIOS_INFO, "Enable EOSC LPD only\n"); + rtc_read(RTC_AL_SEC, &rdata); + + rtc_write(RTC_AL_SEC, (rdata & (~RTC_LPD_OPT_MASK)) | RTC_LPD_OPT_EOSC_LPD); + if (!rtc_write_trigger()) + return false; + + rtc_read(RTC_CON, &rdata); + con = rdata | RTC_XOSC32_LPEN; + con &= ~RTC_CON_LPRST; + rtc_write(RTC_CON, con); + if (!rtc_write_trigger()) + return false; + + con |= RTC_CON_LPRST; + rtc_write(RTC_CON, con); + if (!rtc_write_trigger()) + return false; + + con &= ~RTC_CON_LPRST; + rtc_write(RTC_CON, con); + if (!rtc_write_trigger()) + return false; + + rtc_read(RTC_CON, &rdata); + con = rdata | RTC_EOSC32_LPEN; + con &= ~RTC_CON_LPRST; + rtc_write(RTC_CON, con); + if (!rtc_write_trigger()) + return false; + + con |= RTC_CON_LPRST; + rtc_write(RTC_CON, con); + if (!rtc_write_trigger()) + return false; + + con &= ~RTC_CON_LPRST; + rtc_write(RTC_CON, con); + if (!rtc_write_trigger()) + return false; + + rtc_read(RTC_CON, &rdata); + printk(BIOS_INFO, "%s: RTC_CON=%#x\n", __func__, rdata); + + /* bit 7 for low power detected in preloader */ + rtc_read(RTC_CON, &rdata); + rtc_write(RTC_SPAR0, rdata | RTC_PDN1_PWRON_TIME); + if (!rtc_write_trigger()) + return false; + + return true; +} + +static void secure_write_trigger(void) +{ + rtc_write(RTC_WRTGR_SEC, 1); +} + +static void secure_rtc_set_ck(void) +{ + u8 val; + u16 rtc_sec_dsn; + u16 rtc_sec_dsn_rev0; + u16 rtc_sec_ck_pdn; + + printk(BIOS_INFO, "%s: Enter\n", __func__); + + val = RG_RTC_SEC_MCLK_PDN_MASK | + (RG_RTC_SEC_32K_CK_PDN_MASK << RG_RTC_SEC_32K_CK_PDN_SHIFT); + + config_interface(SCK_TOP_CKPDN_CON0_L_CLR, val, + val, SCK_TOP_CKPDN_CON0_L_CLR_SHIFT); + + udelay(50); + rtc_write(RTC_SEC_CK_PDN, 1); + secure_write_trigger(); + + val = config_interface_read(MT6685_SCK_TOP_CKPDN_CON0_L); + rtc_read(RTC_SEC_DSN_ID, &rtc_sec_dsn); + rtc_read(RTC_SEC_DSN_REV0, &rtc_sec_dsn_rev0); + + printk(BIOS_INFO, "RTC_SEC_DSN_ID[%#x]=%#x, RTC_SEC_DSN_REV0[%#x]=%#x\n", + RTC_SEC_DSN_ID, rtc_sec_dsn, + RTC_SEC_DSN_REV0, rtc_sec_dsn_rev0); + + rtc_read(RTC_SEC_CK_PDN, &rtc_sec_ck_pdn); + printk(BIOS_INFO, "SCK_TOP_CKPDN_CON0[%#x]=0x%x, RTC_SEC_CK_PDN[%#x]=%#x\n", + SCK_TOP_CKPDN_CON0_L, val, RTC_SEC_CK_PDN, rtc_sec_ck_pdn); +} + +static void secure_rtc_init(void) +{ + printk(BIOS_INFO, "%s: Enter\n", __func__); + secure_rtc_set_ck(); + udelay(100); + + rtc_write(RTC_TC_YEA_SEC, RTC_DEFAULT_YEA - RTC_MIN_YEAR); + rtc_write(RTC_TC_MTH_SEC, RTC_DEFAULT_MTH); + rtc_write(RTC_TC_DOM_SEC, RTC_DEFAULT_DOM); + rtc_write(RTC_TC_DOW_SEC, 1); + rtc_write(RTC_TC_HOU_SEC, 0); + rtc_write(RTC_TC_MIN_SEC, 0); + rtc_write(RTC_TC_SEC_SEC, 0); + secure_write_trigger(); +} + +static bool rtc_init_after_recovery(void) +{ + /* write powerkeys */ + rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); + rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); + + if (!rtc_write_trigger()) + return false; + if (!rtc_writeif_unlock()) + return false; + if (!rtc_gpio_init()) + return false; + if (!rtc_hw_init()) + return false; + if (!rtc_reg_init()) + return false; + if (!rtc_lpd_init()) + return false; + + rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); + rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); + if (!rtc_write_trigger()) + return false; + if (!rtc_writeif_unlock()) + return false; + + secure_rtc_init(); + + printk(BIOS_INFO, "%s: done\n", __func__); + return true; +} + +static void rtc_recovery_flow(void) +{ + printk(BIOS_INFO, "%s: enter\n", __func__); + + if (!retry(RETRY_MAX_TIME, rtc_frequency_meter_check() && + rtc_init_after_recovery())) { + printk(BIOS_INFO, "%s: rtc recovery 3 times failed!!\n", __func__); + } +} + +static bool rtc_first_boot_init(void) +{ + u16 rdata; + printk(BIOS_INFO, "%s: Enter\n", __func__); + + rtc_read(RTC_BBPU, &rdata); + rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RESET_SPAR); + if (!rtc_write_trigger()) + return false; + + if (!rtc_writeif_unlock()) { + printk(BIOS_ERR, + "%s: rtc_writeif_unlock failed after writing BBPU\n", __func__); + return false; + } + + if (!rtc_gpio_init()) + return false; + + /* write powerkeys */ + rtc_read(RTC_AL_SEC, &rdata); + rtc_write(RTC_AL_SEC, rdata & (~RTC_K_EOSC32_VTCXO_ON_SEL)); + rtc_read(RTC_AL_YEA, &rdata); + rtc_write(RTC_AL_YEA, (rdata & RTC_AL_YEA_MASK) + | RTC_K_EOSC_RSV_7 | RTC_K_EOSC_RSV_6); + + rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); + rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); + if (!rtc_writeif_unlock()) { + printk(BIOS_ERR, + "%s: rtc_writeif_unlock failed after writing POWERKEY\n", __func__); + return false; + } + + rtc_read(RTC_BBPU, &rdata); + rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RESET_SPAR); + + + if (!rtc_write_trigger()) { + printk(BIOS_ERR, + "%s rtc_write_trigger failed after writing BBPU\n", __func__); + return false; + } + + if (!rtc_writeif_unlock()) { + printk(BIOS_ERR, + "%s rtc_writeif_unlock after writing BBPU\n", __func__); + return false; + } + + if (!rtc_lpd_init()) + return false; + + /* MT6351 need write POWERKEY again to unlock RTC */ + rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); + rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); + + if (!rtc_write_trigger()) { + printk(BIOS_ERR, + "%s rtc_write_trigger after writing POWERKEY\n", __func__); + return false; + } + + if (!rtc_writeif_unlock()) { + printk(BIOS_ERR, + "%s rtc_writeif_unlock after writing POWERKEY\n", __func__); + return false; + } + + if (!rtc_frequency_meter_check()) + return false; + + if (!rtc_hw_init()) + return false; + + if (!rtc_reg_init()) + return false; + + secure_rtc_init(); + + return true; +} + +static void rtc_enable_dcxo(void) +{ + u16 rdata; + u16 con, osc32con, sec; + + /* Unlock for reload */ + if (!rtc_writeif_unlock()) + printk(BIOS_ERR, "rtc_writeif_unlock() failed\n"); + + rtc_read(RTC_BBPU, &rdata); + rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + rtc_read(RTC_OSC32CON, &rdata); + + /* 0: f32k_ck src = dcxo_ck */ + rtc_xosc_write(rdata & ~RTC_EMBCK_SRC_SEL); + + rtc_read(RTC_BBPU, &rdata); + rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + + rtc_read(RTC_CON, &rdata); + con = rdata; + + rtc_read(RTC_OSC32CON, &rdata); + osc32con = rdata; + + rtc_read(RTC_AL_SEC, &rdata); + sec = rdata; + + printk(BIOS_INFO, "%s con = %#x, osc32con = %#x, sec = %#x\n", __func__, + con, osc32con, sec); +} + +void rtc_boot(void) +{ + bool need_secure_rtc_set_ck = false; + struct rtc_clk_freq result; + u16 rdata; + u16 rtc_diff; + u16 rtc_con; + u16 rtc_pwrkey1; + u16 rtc_pwrkey2; + u16 rtc_bbpu; + u16 rtc_osc32con; + u16 rtc_al_sec; + u16 rtc_al_yea; + + /* If EOSC cali is enabled in last power off. Needing to switch to DCXO clock source, */ + /* Or the FQMTR can't measure DCXO clock source. */ + rtc_read(RTC_DIFF, &rtc_diff); + rtc_read(RTC_CON, &rtc_con); + rtc_read(RTC_POWERKEY1, &rtc_pwrkey1); + rtc_read(RTC_POWERKEY2, &rtc_pwrkey2); + + if ((rtc_diff & RTC_POWER_DETECTED) && + !(rtc_con & RTC_CON_LPSTA_RAW) && + (rtc_pwrkey1 == RTC_POWERKEY1_KEY && + rtc_pwrkey2 == RTC_POWERKEY2_KEY)) + rtc_enable_dcxo(); + + /* Check clock source are match with 32K exist */ + rtc_measure_four_clock(&result); + + if (!rtc_eosc_check_clock(&result)) + printk(BIOS_INFO, "Enter first boot init.\n"); + + rtc_read(RTC_POWERKEY1, &rtc_pwrkey1); + rtc_read(RTC_POWERKEY2, &rtc_pwrkey2); + rtc_read(RTC_CON, &rtc_con); + printk(BIOS_INFO, "%s: powerkey1 = %#x, powerkey2 = %#x, %s LPD\n", __func__, + rtc_pwrkey1, rtc_pwrkey2, + (rtc_con & RTC_CON_LPSTA_RAW) ? + "with" : "without"); + + rtc_read(RTC_BBPU, &rtc_bbpu); + rtc_read(RTC_CON, &rtc_con); + rtc_read(RTC_OSC32CON, &rtc_osc32con); + rtc_read(RTC_AL_SEC, &rtc_al_sec); + rtc_read(RTC_AL_YEA, &rtc_al_yea); + + printk(BIOS_INFO, "bbpu = %#x, con = %#x, osc32con = %#x, sec = %#x, yea = %#x\n", + rtc_bbpu, rtc_con, rtc_osc32con, + rtc_al_sec, rtc_al_yea); + + rtc_read(RTC_BBPU, &rtc_bbpu); + rtc_write(RTC_BBPU, rtc_bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + + if (!rtc_write_trigger() || !rtc_writeif_unlock()) { + rtc_recovery_flow(); + } else { + rtc_read(RTC_POWERKEY1, &rtc_pwrkey1); + rtc_read(RTC_POWERKEY2, &rtc_pwrkey2); + if (rtc_pwrkey1 != RTC_POWERKEY1_KEY || + rtc_pwrkey2 != RTC_POWERKEY2_KEY) { + printk(BIOS_INFO, "%s: powerkey1 = %#x, powerkey2 = %#x\n", __func__, + rtc_pwrkey1, rtc_pwrkey2); + if (!rtc_first_boot_init()) + rtc_recovery_flow(); + } else { + rtc_osc_init(); + need_secure_rtc_set_ck = true; + } + } + + /* Make sure RTC get the latest register info. */ + rtc_read(RTC_BBPU, &rtc_bbpu); + rtc_write(RTC_BBPU, rtc_bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + + /* HW K EOSC mode whatever power off (including plug out battery) */ + rtc_read(RTC_AL_YEA, &rtc_al_yea); + /* HW K EOSC mode whatever power off (including plug out battery) */ + rtc_write(RTC_AL_YEA, ((rtc_al_yea | RTC_K_EOSC_RSV_0) & + (~RTC_K_EOSC_RSV_1)) & (~RTC_K_EOSC_RSV_2)); + + /* Write Protection Key to unlock RG_OCT1_RTC32K_1V8_0 */ + config_interface(TMA_KEY, 0x7a, TMA_KEY_MASK, TMA_KEY_SHIFT); + config_interface(TMA_KEY_H, 0x99, TMA_KEY_H_MASK, TMA_KEY_H_SHIFT); + + /* Set 32K1V8_0_driving 8mA */ + config_interface(RG_OCT1_RTC32K_1V8_0, 1, + RG_OCT1_RTC32K_1V8_0_MASK, RG_OCT1_RTC32K_1V8_0_SHIFT); + + /* Set 32K1V8_F_driving 8mA */ + config_interface(RG_OCT1_RTC32K_1V8_F, 1, + RG_OCT1_RTC32K_1V8_F_MASK, RG_OCT1_RTC32K_1V8_F_SHIFT); + + /* Write Protection Key to unlock TOP_CKPDN_CON0 */ + config_interface(TOP_DIG_WPK, 0x15, DIG_WPK_KEY_MASK, DIG_WPK_KEY_SHIFT); + config_interface(TOP_DIG_WPK_H, 0x63, DIG_WPK_KEY_H_MASK, DIG_WPK_KEY_H_SHIFT); + + /* Selects RTC_32K1V8_0_CK clock */ + config_interface(SCK_TOP_CKSEL_CON, 1, R_SCK32K_CK_MASK, R_SCK32K_CK_SHIFT); + rtc_read(SCK_TOP_CKSEL_CON, &rdata); + printk(BIOS_INFO, "SCK_TOP_CKSEL_CON = %#x\n", rdata); + + /* Truning off eosc cali mode clock */ + config_interface(SCK_TOP_CKPDN_CON0_L_SET, 1, + RG_RTC_EOSC32_CK_PDN_MASK, RG_RTC_EOSC32_CK_PDN_SHIFT); + + /* Set register to let MD know 32k status */ + rtc_read(RTC_SPAR0, &rdata); + rtc_write(RTC_SPAR0, (rdata & ~RTC_SPAR0_32K_LESS)); + + printk(BIOS_INFO, "32k-less mode\n"); + rtc_write_trigger(); + + rtc_read(RTC_BBPU, &rtc_bbpu); + rtc_write(RTC_BBPU, rtc_bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + + /* Clear ONESHOT bit to solve alarm issue */ + rtc_read(RTC_IRQ_EN, &rdata); + rtc_write(RTC_IRQ_EN, rdata & ~RTC_IRQ_EN_ONESHOT); + rtc_write_trigger(); + rtc_read(RTC_IRQ_EN, &rdata); + printk(BIOS_INFO, "check RTC_IRQ_EN = %#x\n", rdata); + + if (need_secure_rtc_set_ck) + secure_rtc_set_ck(); +} + +static void rtc_get_tick(struct rtc_time *tm) +{ + u16 rdata; + rtc_read(RTC_BBPU, &rdata); + rtc_write(RTC_BBPU, rdata | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + + rtc_read(RTC_TC_SEC, &rdata); + tm->sec = rdata; + + rtc_read(RTC_TC_MIN, &rdata); + tm->min = rdata; + + rtc_read(RTC_TC_HOU, &rdata); + tm->hour = rdata; + + rtc_read(RTC_TC_DOM, &rdata); + tm->mday = rdata; + + rtc_read(RTC_TC_MTH, &rdata); + tm->mon = rdata & RTC_TC_MTH_MASK; + + rtc_read(RTC_TC_YEA, &rdata); + tm->year = rdata; +} + +void rtc_get_time(struct rtc_time *tm) +{ + u16 rdata; + rtc_get_tick(tm); + rtc_read(RTC_TC_SEC, &rdata); + + /* SEC has carried */ + if (rdata < tm->sec) + rtc_get_tick(tm); + + tm->year += RTC_MIN_YEAR; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[XS] Change in coreboot[main]: DEMO: Enable AB recovery
by Bao Zheng (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85659?usp=email to look at the new patch set (#3). Change subject: DEMO: Enable AB recovery ...................................................................... DEMO: Enable AB recovery Change-Id: I2042071bbe273053d75d32d6a06e992ff55cc98e Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85659/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85659?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2042071bbe273053d75d32d6a06e992ff55cc98e Gerrit-Change-Number: 85659 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[M] Change in coreboot[main]: soc/amd: Add A/B recovery support to AMD SOC
by Bao Zheng (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85647?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd: Add A/B recovery support to AMD SOC ...................................................................... soc/amd: Add A/B recovery support to AMD SOC Copy the settings from Cezanne to glinda & phoenix. 1. Add A/B data address to command line. 2. Enable CBFS verificatin if A/B recovery is enabled. 3. Do not compress the bootblock binary. Change-Id: Iaa8c4175285c5ceb16972ea57f0c0ca0403d8b84 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.mk M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.mk 4 files changed, 48 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85647/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85647?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa8c4175285c5ceb16972ea57f0c0ca0403d8b84 Gerrit-Change-Number: 85647 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[M] Change in coreboot[main]: soc/amd: Add some PSP commands
by Bao Zheng (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Matt DeVillier, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85650?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd: Add some PSP commands ...................................................................... soc/amd: Add some PSP commands Getting and setting boot partition. Toggle boot partition. Set corruption reason. Change-Id: Ia7f2eedae5b277745cb34a0761bd1a8b61441695 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c 2 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/85650/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/85650?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7f2eedae5b277745cb34a0761bd1a8b61441695 Gerrit-Change-Number: 85650 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[XS] Change in coreboot[main]: AB recovery: Set some Kconfig settings to support A/B recovery
by Bao Zheng (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Marshall Dawson, Matt DeVillier, Zheng Bao. Hello Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Marshall Dawson, Matt DeVillier, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85664?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: AB recovery: Set some Kconfig settings to support A/B recovery ...................................................................... AB recovery: Set some Kconfig settings to support A/B recovery AB recovery depends on CBFS verification and is exclusive with VBOOT and ChromeOS. Change-Id: I0b89e7be11c198ab1819a3506dc55127345e5279 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/85664/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85664?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b89e7be11c198ab1819a3506dc55127345e5279 Gerrit-Change-Number: 85664 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Jarried Lin (Code Review) 14 Jan '25

14 Jan '25

Attention is currently required from: Hung-Te Lin, Paul Menzel, agogo. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/mt8196/Kconfig: https://review.coreboot.org/c/coreboot/+/85888/comment/4e98270d_3488e4a0?us… : PS5, Line 64: The file name of the MediaTek MCUPM firmware. > Please elaborate what MCUPM firmware is used for. Can we add MCUPM firmware introduction in commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 14 Jan 2025 14:15:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2025