coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: soc/mediatek: Modify MT6363 pmic driver
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86034?usp=email ) Change subject: soc/mediatek: Modify MT6363 pmic driver ...................................................................... soc/mediatek: Modify MT6363 pmic driver Use mt6363_write8 instead of mt6363_write16 when setting the protect key, only need 1 byte needs to be written to the register each time. Remove mt6363_write16 api to prevent build failure. TEST=Build pass, DUT can power on during S5. BUG=b:388666377 Change-Id: I0a7c0d2fa1f93a55731b4b58923d6f80a4c4be89 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/mt6363.c 1 file changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/86034/1 diff --git a/src/soc/mediatek/common/mt6363.c b/src/soc/mediatek/common/mt6363.c index 220a7ce..e675ef2 100644 --- a/src/soc/mediatek/common/mt6363.c +++ b/src/soc/mediatek/common/mt6363.c @@ -50,12 +50,6 @@ pmif_arb->write(pmif_arb, SPMI_SLAVE_4, reg, data); } -static void mt6363_write16(u32 reg, u16 data) -{ - assert(pmif_arb); - pmif_arb->write16(pmif_arb, SPMI_SLAVE_4, reg, data); -} - static u32 mt6363_read_field(u32 reg, u32 mask, u32 shift) { assert(pmif_arb); @@ -101,7 +95,7 @@ for (int i = 0; i < ARRAY_SIZE(key_protect_setting); i++) { entry = &key_protect_setting[i]; - mt6363_write16(entry->addr, lock ? 0 : entry->val); + mt6363_write8(entry->addr, lock ? 0 : entry->val); } printk(BIOS_INFO, "%s done\n", __func__); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0a7c0d2fa1f93a55731b4b58923d6f80a4c4be89 Gerrit-Change-Number: 86034 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add unmask eint event for bootblock
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Chhao Chang, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84025?usp=email ) Change subject: soc/mediatek/mt8196: Add unmask eint event for bootblock ...................................................................... Patch Set 17: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84025/comment/4077cc19_ac5a3507?us… : PS17, Line 12: ' " https://review.coreboot.org/c/coreboot/+/84025/comment/483d5011_9b60cfe9?us… : PS17, Line 12: ' " https://review.coreboot.org/c/coreboot/+/84025/comment/db67b42b_9c7d2a33?us… : PS17, Line 16: 31709620 Wrong bug? File src/soc/mediatek/common/include/soc/eint_event.h: https://review.coreboot.org/c/coreboot/+/84025/comment/e00d8dca_694a9b4d?us… : PS17, Line 17: struct eint_info { : uintptr_t base; : unsigned int eint_num; : }; > It has nothing to do with the type of IC. I uploaded CB:86033 to do the refactoring for you. Please take a look. Chhao, if that looks good to you, please rebase this onto that patch. You'll need to add src/soc/mediatek/mt8196/eint_event_info.c with content: ``` /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include <soc/addressmap.h> #include <soc/eint_event.h> const struct eint_event_info eint_event[] = { {EINT_E_BASE, 75}, {EINT_S_BASE, 29}, {EINT_W_BASE, 58}, {EINT_N_BASE, 47}, {EINT_C_BASE, 25}, {}, }; ``` File src/soc/mediatek/mt8196/bootblock.c: https://review.coreboot.org/c/coreboot/+/84025/comment/d2632799_17c8f366?us… : PS17, Line 9: #include <soc/eint_event.h> sort -- To view, visit https://review.coreboot.org/c/coreboot/+/84025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3 Gerrit-Change-Number: 84025 Gerrit-PatchSet: 17 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 10:12:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek: Allow specifying multiple EINT base registers
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Yidi Lin. Yu-Ping Wu has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/86033?usp=email ) Change subject: soc/mediatek: Allow specifying multiple EINT base registers ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/common/eint_event_info.c: https://review.coreboot.org/c/coreboot/+/86033/comment/2ca2cd90_4163c68f?us… : PS1, Line 7: 224 This comes from `7*32`. -- To view, visit https://review.coreboot.org/c/coreboot/+/86033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86fd3109c9ff72f33b9fea45587d012b003a34ba Gerrit-Change-Number: 86033 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 10:08:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek: Allow specifying multiple EINT base registers
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86033?usp=email ) Change subject: soc/mediatek: Allow specifying multiple EINT base registers ...................................................................... soc/mediatek: Allow specifying multiple EINT base registers Unlike MT8186/MT8188/MT8192/MT8195, MT8196 has 5 EINT base registers, each with a different number of EINT bits. In preparation for the upcoming MT8196 EINT unmasking support, replace the `eint_event_reg` struct (which has a hardcoded register number) with an array `eint_event` to specify the EINT base register(s). BUG=none TEST=emerge-geralt coreboot BRANCH=none Change-Id: I86fd3109c9ff72f33b9fea45587d012b003a34ba Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/common/eint_event.c A src/soc/mediatek/common/eint_event_info.c M src/soc/mediatek/common/include/soc/eint_event.h M src/soc/mediatek/mt8186/Makefile.mk M src/soc/mediatek/mt8188/Makefile.mk M src/soc/mediatek/mt8192/Makefile.mk M src/soc/mediatek/mt8195/Makefile.mk 7 files changed, 44 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/86033/1 diff --git a/src/soc/mediatek/common/eint_event.c b/src/soc/mediatek/common/eint_event.c index b3538a1..6e44b37 100644 --- a/src/soc/mediatek/common/eint_event.c +++ b/src/soc/mediatek/common/eint_event.c @@ -1,10 +1,30 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/bsd/helpers.h> +#include <device/mmio.h> #include <soc/eint_event.h> +#include <types.h> + +/* EINT reg_base + 0x880 is eint_event_mask_clr register with access type W1C. */ +#define EINT_EVENT_MASK_CLR_OFFSET 0x880 + +#define EINT_VALUE 0xFFFFFFFF + +static void enable_eint_event(const struct eint_event_info *event) +{ + uint32_t *reg = (uint32_t *)(event->reg_base + EINT_EVENT_MASK_CLR_OFFSET); + size_t port = DIV_ROUND_UP(event->eint_num, sizeof(*reg) * BITS_PER_BYTE); + int i; + + for (i = 0; i < port; i++) + write32p(reg[i], EINT_VALUE); +} void unmask_eint_event_mask(void) { - int i; - for (i = 0; i < ARRAY_SIZE(mtk_eint_event->eint_event_mask_clr); i++) - write32(&mtk_eint_event->eint_event_mask_clr[i], 0xffffffff); + const struct eint_event_info *event = &eint_event[0]; + while (event->reg_base && event->eint_num) { + enable_eint_event(event); + event++; + } } diff --git a/src/soc/mediatek/common/eint_event_info.c b/src/soc/mediatek/common/eint_event_info.c new file mode 100644 index 0000000..706cca8 --- /dev/null +++ b/src/soc/mediatek/common/eint_event_info.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <soc/addressmap.h> +#include <soc/eint_event.h> + +const struct eint_event_info eint_event[] = { + { EINT_BASE, 224 }, + {}, +}; diff --git a/src/soc/mediatek/common/include/soc/eint_event.h b/src/soc/mediatek/common/include/soc/eint_event.h index 6d544b4..eab51ed 100644 --- a/src/soc/mediatek/common/include/soc/eint_event.h +++ b/src/soc/mediatek/common/include/soc/eint_event.h @@ -3,18 +3,18 @@ #ifndef SOC_MEDIATEK_COMMON_EINT_EVENT_H #define SOC_MEDIATEK_COMMON_EINT_EVENT_H -#include <device/mmio.h> -#include <soc/addressmap.h> +#include <stddef.h> +#include <stdint.h> -/* eint event mask clear register */ -struct eint_event_reg { - uint32_t eint_event_mask_clr[7]; +struct eint_event_info { + uintptr_t reg_base; + size_t eint_num; }; -/* eint_base + 0x880 is eint_event_mask_clr register with access type W1C. */ -static struct eint_event_reg *const mtk_eint_event = (void *)(EINT_BASE + 0x880); +/* An element { 0, 0 } indicates the end of array. */ +extern const struct eint_event_info eint_event[]; -/* unmask eint event, eint can wakeup by spm */ +/* Unmask eint event, which can be waken up by SPM. */ void unmask_eint_event_mask(void); #endif diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk index 0d44c2e..c4a3f21 100644 --- a/src/soc/mediatek/mt8186/Makefile.mk +++ b/src/soc/mediatek/mt8186/Makefile.mk @@ -12,7 +12,7 @@ all-y += ../common/uart.c bootblock-y += bootblock.c -bootblock-y += ../common/eint_event.c +bootblock-y += ../common/eint_event.c ../common/eint_event_info.c bootblock-y += gic.c bootblock-y += ../common/lastbus_v1.c bootblock-y += ../common/mmu_operations.c diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk index 2f1a0f5..2c8379e 100644 --- a/src/soc/mediatek/mt8188/Makefile.mk +++ b/src/soc/mediatek/mt8188/Makefile.mk @@ -10,7 +10,7 @@ all-y += ../common/uart.c bootblock-y += ../common/bootblock.c bootblock.c -bootblock-y += ../common/eint_event.c +bootblock-y += ../common/eint_event.c ../common/eint_event_info.c bootblock-y += ../common/lastbus_v2.c lastbus.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/tracker.c ../common/tracker_v2.c diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk index 1c4baa8..b2c3ced 100644 --- a/src/soc/mediatek/mt8192/Makefile.mk +++ b/src/soc/mediatek/mt8192/Makefile.mk @@ -10,7 +10,7 @@ all-y += ../common/uart.c bootblock-y += bootblock.c -bootblock-y += ../common/eint_event.c +bootblock-y += ../common/eint_event.c ../common/eint_event_info.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/tracker.c ../common/tracker_v2.c diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index 7c3d3f4..ecc6965 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -11,7 +11,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/early_init.c -bootblock-y += ../common/eint_event.c +bootblock-y += ../common/eint_event.c ../common/eint_event_info.c bootblock-y += ../common/mmu_operations.c bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c bootblock-y += ../common/pll.c pll.c -- To view, visit https://review.coreboot.org/c/coreboot/+/86033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86fd3109c9ff72f33b9fea45587d012b003a34ba Gerrit-Change-Number: 86033 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86027?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra ...................................................................... soc/mediatek/mt8196: Add GCE ddren sel control to mminfra MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction ACK from SPM: 0, non-SPM: 0x1. In MT8196, SPM has masked all the DDR request, so this setting should be set to non-SPM whenever mminfra power on every time. Otherwise, GCE will hang when accessing DRAM. BUG=b:379039600 TEST=boot up ok, GCE can access DRAM countinuosly Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Signed-off-by: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/include/soc/mminfra.h M src/soc/mediatek/mt8196/mminfra.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/86027/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Gerrit-Change-Number: 86027 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Bill XIE (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Keith Hui. Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 1: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/94b8cd65_79772840?us… : PS1, Line 67: gpio5 |= 0x20; > The overridetree could be why. […] After commenting out "drq 0xf4 = 0xfc" for GPIO5 in overridetree.cb, no device can be detected under PCIe pcie_rp4 (00:00:1c.3) any more regardless of whether a card is present on PCIEX1_2, and LDN 0x09 becomes idx 30 ... f4 f5 ... val ff ... 8f a8 ... def 00 ... ff 00 ... when a card is present, and idx 30 ... f4 f5 ... val ff ... 8f 88 ... def 00 ... ff 00 ... when not. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 10:02:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[L] Change in coreboot[main]: mainboard/hp: Add ProBook 450 G3
by Nicholas Sudsgaard (Code Review) 17 Jan '25

17 Jan '25

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83433?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mainboard/hp: Add ProBook 450 G3 ...................................................................... mainboard/hp: Add ProBook 450 G3 Linux support is pretty good, as there are only minor issues and some are not related to firmware. On the other hand, Windows support is experimental and is currently not recommended to use. See `Documentation/mainboard/hp/probook_450_g3.md` for details about tested features and known issues. Change-Id: Ic1cee48b4b187ac8b5fcda099a99956658821920 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M Documentation/mainboard/hp/hp_sure_start.md A Documentation/mainboard/hp/probook_450_g3.md A Documentation/mainboard/hp/probook_450_g3_chip_location.jpg A Documentation/mainboard/hp/probook_450_g3_flash_visualization.png M Documentation/mainboard/index.md A src/mainboard/hp/probook_450_g3/Kconfig A src/mainboard/hp/probook_450_g3/Kconfig.name A src/mainboard/hp/probook_450_g3/Makefile.mk A src/mainboard/hp/probook_450_g3/acpi/ec.asl A src/mainboard/hp/probook_450_g3/acpi/superio.asl A src/mainboard/hp/probook_450_g3/board_info.txt A src/mainboard/hp/probook_450_g3/data.vbt A src/mainboard/hp/probook_450_g3/devicetree.cb A src/mainboard/hp/probook_450_g3/dsdt.asl A src/mainboard/hp/probook_450_g3/gma-mainboard.ads A src/mainboard/hp/probook_450_g3/gpio.h A src/mainboard/hp/probook_450_g3/hda_verb.c A src/mainboard/hp/probook_450_g3/ramstage.c A src/mainboard/hp/probook_450_g3/romstage.c 19 files changed, 739 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/83433/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/83433?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic1cee48b4b187ac8b5fcda099a99956658821920 Gerrit-Change-Number: 83433 Gerrit-PatchSet: 18 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[M] Change in coreboot[main]: soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/86028?usp=email ) Change subject: soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/common/dp/dptx.c: https://review.coreboot.org/c/coreboot/+/86028/comment/615b6178_0d43130c?us… : PS4, Line 507: dptx_video_enable(mtk_dp, true); > return 0; Apparently I'm over-confident of my coding. 😞 -- To view, visit https://review.coreboot.org/c/coreboot/+/86028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c Gerrit-Change-Number: 86028 Gerrit-PatchSet: 5 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 09:18:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86028?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow ...................................................................... soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow In the current eDP initialization flow, eDP is configured and enabled before display data pipe (DDP) initialization. The init flow is wrong, because eDP should be enabled only after DDP is correctly set up. The wrong flow may lead to garbage display between enabling eDP and configuring DDP. To fix the problem, the dptx_video_enable(true) call needs to be moved after mtk_ddp_mode_set(). Introduce a new API mtk_edp_enable() for eDP enablement, to be separated from the existing mtk_edp_init(). The fixed eDP init flow is: mtk_edp_init -> mtk_ddp_mode_set -> mtk_edp_enable. Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/common/display.c M src/soc/mediatek/common/dp/dptx.c M src/soc/mediatek/common/dp/include/soc/dptx_common.h 3 files changed, 35 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/86028/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c Gerrit-Change-Number: 86028 Gerrit-PatchSet: 5 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek: Correct value's data type to u8 in dptx.
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85948?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek: Correct value's data type to u8 in dptx. ...................................................................... soc/mediatek: Correct value's data type to u8 in dptx. TEST=build pass BUG=b:343351631 Change-Id: I60bbb2c37811655692a5a8cd9f942fed4ead8abb Signed-off-by: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/dp/dptx_hal.c M src/soc/mediatek/common/dp/dptx_hal_common.c M src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h 3 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/85948/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85948?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60bbb2c37811655692a5a8cd9f942fed4ead8abb Gerrit-Change-Number: 85948 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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