coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85949?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add eDP driver ...................................................................... soc/mediatek/mt8196: Add eDP driver Add eDP driver to adjust training flow and turn off PHY power before PHY configuration to prevent potential link traning failures. TEST=check edp training pass and show log: EQ training pass BUG=b:343351631 Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Signed-off-by: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/dp/include/soc/dptx_common.h M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/dp_intf.c A src/soc/mediatek/mt8196/dptx.c A src/soc/mediatek/mt8196/dptx_hal.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/dp_intf.h A src/soc/mediatek/mt8196/include/soc/dptx.h A src/soc/mediatek/mt8196/include/soc/dptx_hal.h A src/soc/mediatek/mt8196/include/soc/dptx_reg.h 10 files changed, 1,493 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85949/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Gerrit-Change-Number: 85949 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/mediatek: Correct value's data type to u8 in dptx.
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85948?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek: Correct value's data type to u8 in dptx. ...................................................................... soc/mediatek: Correct value's data type to u8 in dptx. TEST=build pass BUG=b:343351631 Change-Id: I60bbb2c37811655692a5a8cd9f942fed4ead8abb Signed-off-by: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/dp/dptx_hal.c M src/soc/mediatek/common/dp/dptx_hal_common.c M src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h 3 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/85948/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85948?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60bbb2c37811655692a5a8cd9f942fed4ead8abb Gerrit-Change-Number: 85948 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 2: (21 comments) File src/soc/mediatek/mt8196/include/soc/mt6685_rtc.h: https://review.coreboot.org/c/coreboot/+/85978/comment/72a236cf_04679303?us… : PS2, Line 84: /* : * Complete the RTC initialization process, : * setting of related registers : */ `/* Complete the RTC initialization process and register settings. */` File src/soc/mediatek/mt8196/include/soc/rtc.h: https://review.coreboot.org/c/coreboot/+/85978/comment/89890d8f_e85f3a62?us… : PS2, Line 58: WATCH_INIT If this means "stopwatch_init", please use a more descriptive name. How about `BBPU_RELOAD_TIMEOUT_US`? https://review.coreboot.org/c/coreboot/+/85978/comment/0512b00c_b1fc7af4?us… : PS2, Line 59: WAIT_EOSC_CHECK_CLK_RDY_TIME_US `EOSC_CHECK_CLK_TIMEOUT_US` https://review.coreboot.org/c/coreboot/+/85978/comment/d9d2d48d_26b8f2ea?us… : PS2, Line 60: RETRY_MAX_TIME `RECOVERY_RETRY_COUNT` File src/soc/mediatek/mt8196/include/soc/rtc.h: https://review.coreboot.org/c/coreboot/+/85978/comment/73f3250a_ecc615d5?us… : PS1, Line 18: RTC_BBPU_PWREN = BIT(0), > Regarding the problem of the header file RTC_COMMON. […] Keep this open until resolved. File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/e6a1ea0a_121c683b?us… : PS1, Line 148: freq[2] > will update Please answer Yidi's question here in the Gerrit comment. https://review.coreboot.org/c/coreboot/+/85978/comment/73d35939_817f4c1d?us… : PS1, Line 417: > Done not done File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/4920993d_b027cedc?us… : PS2, Line 101: ERROR: get frequency `FQMTR read` https://review.coreboot.org/c/coreboot/+/85978/comment/436de4bd_1e1e7a15?us… : PS2, Line 105: 26M/32K = 794 `26MHz / 23K = (26 * 10^6) / (23 * 1024) ~= 794` https://review.coreboot.org/c/coreboot/+/85978/comment/bd221d13_f7821e07?us… : PS2, Line 139: You removed the wrong blank line. I think this function should have 3 groups separated by blank lines. Each group contains ``` config_interface(...); udelay(100); /* Comment */ result-xxx = ...; ``` Does that make sense to you? https://review.coreboot.org/c/coreboot/+/85978/comment/1f6012c2_75a2211c?us… : PS2, Line 325: rtc_powerkey_init(); : : if (!rtc_write_trigger()) : return false; `rtc_powerkey_init` already contains `rtc_write_trigger`. Change this to ``` if (!rtc_powerkey_init()) return false; ``` https://review.coreboot.org/c/coreboot/+/85978/comment/13dd5be5_fe84ab9f?us… : PS2, Line 340: rtc_powerkey_init(); : if (!rtc_write_trigger()) : return false; ``` if (!rtc_powerkey_init()) return false; ``` https://review.coreboot.org/c/coreboot/+/85978/comment/1122e8c2_c445c08b?us… : PS2, Line 358: rtc_init_after_recovery > align or move to above line move to above line https://review.coreboot.org/c/coreboot/+/85978/comment/989bbf4f_9e831e29?us… : PS2, Line 375: wrritten written https://review.coreboot.org/c/coreboot/+/85978/comment/3fcf476d_1062d182?us… : PS2, Line 388: rtc_powerkey_init(); By changing the 2 `rtc_write` calls to `rtc_powerkey_init`, there will be an extra `rtc_write_trigger` call. Please confirm if the behavior is correct. https://review.coreboot.org/c/coreboot/+/85978/comment/5b05d356_1bc5460e?us… : PS2, Line 391: wrritten written https://review.coreboot.org/c/coreboot/+/85978/comment/d37b1979_98fcb057?us… : PS2, Line 414: need `needs to` https://review.coreboot.org/c/coreboot/+/85978/comment/3b107b33_7a1b6909?us… : PS2, Line 415: rtc_powerkey_init(); : : if (!rtc_write_trigger()) { `if (!rtc_powerkey_init()) {` https://review.coreboot.org/c/coreboot/+/85978/comment/66bf9afb_40f35524?us… : PS2, Line 419: rtc_write_trigger `rtc_powerkey_init failed` https://review.coreboot.org/c/coreboot/+/85978/comment/78e09049_db29c39b?us… : PS2, Line 425: failed https://review.coreboot.org/c/coreboot/+/85978/comment/088d679a_c2dd58f6?us… : PS2, Line 504: Check clock source are match with 32K exist `Check if clock sources match existing 32K` Does my rewording make sense to you? -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 08:34:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: tree: Use boolean for deep_s{3,5}_enable_{ac,dc}
by Erik van den Bogaert (Code Review) 17 Jan '25

17 Jan '25

Erik van den Bogaert has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86020?usp=email ) Change subject: tree: Use boolean for deep_s{3,5}_enable_{ac,dc} ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1621e98e7925b140c608f893a6680c9384bac2f0 Gerrit-Change-Number: 86020 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 17 Jan 2025 08:32:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: tree: Switch to C23
by Elyes Haouas (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Felix Singer, Jakub Czapiga, Julius Werner, Martin L Roth. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86012?usp=email ) Change subject: tree: Switch to C23 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > It's not an Jenkins issue, rather an issue in our build system. […] should we revert commit 84347d0b4598 and commit 7bcec7a2efc4 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/86012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4b2184e5c57143b11e3cc433d09d74a83028420 Gerrit-Change-Number: 86012 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 17 Jan 2025 08:10:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8196/mt_thermal_sram_init.c: https://review.coreboot.org/c/coreboot/+/86017/comment/85d1e41e_81423e05?us… : PS2, Line 32: int i = 0; : uint32_t pattern = 0xffffffff; : uint32_t *buff = (uint32_t *)THERMAL_STAT_SRAM_BASE; : for (i = 0; i < THERMAL_STAT_SRAM_LEN / 4; i++) { : *buff = pattern; : buff++; : } > > Would it be better to align the same style with thermal_cls_sram() function? […] I'm fine either way. I was just providing an alternative to the current code. -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 08:05:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow
by Yidi Lin (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/86028?usp=email ) Change subject: soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/common/dp/dptx.c: https://review.coreboot.org/c/coreboot/+/86028/comment/a98f689f_292ab7c1?us… : PS4, Line 507: dptx_video_enable(mtk_dp, true); return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/86028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c Gerrit-Change-Number: 86028 Gerrit-PatchSet: 4 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 07:59:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rauru: Run mtk-fsp in romstage
by Yu-Ping Wu (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86015?usp=email ) Change subject: mb/google/rauru: Run mtk-fsp in romstage ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id223152e0bda71e99e72b34c91fea8f8841e824b Gerrit-Change-Number: 86015 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 07:56:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in romstage
by Yu-Ping Wu (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86014?usp=email ) Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in romstage ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8196/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/86014/comment/2cb191ab_919ae1ac?us… : PS2, Line 60: FSP_INIT_CODE > The symbol is conflict with one in the ramstage, right ? […] Right. Even if this compiles, it's better to have separate `FSP_ROMSTAGE_INIT_CODE` and `FSP_RAMSTAGE_INIT_CODE`. -- To view, visit https://review.coreboot.org/c/coreboot/+/86014?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73710227e6d9e3f0c717e17db0cc798265eb1f72 Gerrit-Change-Number: 86014 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 07:56:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage
by Yu-Ping Wu (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86013?usp=email ) Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage ...................................................................... Patch Set 2: (2 comments) File src/soc/mediatek/common/include/soc/memlayout.h: https://review.coreboot.org/c/coreboot/+/86013/comment/930d5618_eb5e71f2?us… : PS2, Line 16: #define FSP_INIT_CODE(addr, size) \ > I mean "below" DRAM_DMA. And rename to `FSP_RAMSTAGE_INIT_CODE`. File src/soc/mediatek/mt8196/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/86013/comment/d3857b59_9cf342a9?us… : PS2, Line 67: FSP_INIT_CODE FSP_RAMSTAGE_INIT_CODE -- To view, visit https://review.coreboot.org/c/coreboot/+/86013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21 Gerrit-Change-Number: 86013 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 07:55:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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coreboot-gerrit January 2025