coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Zhaoqing Jiu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, Zhaoqing Jiu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86017?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... soc/mediatek/mt8196: Add thermal driver Add thermal driver to support LVTS (Low Voltage Thermal Sensor). TEST=Check temperatures read from each sensors. BUG=b:317009620 Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/thermal.h A src/soc/mediatek/mt8196/include/soc/thermal_internal.h A src/soc/mediatek/mt8196/thermal.c A src/soc/mediatek/mt8196/thermal_sram.c 7 files changed, 1,036 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/86017/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86013?usp=email ) Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86013/comment/ba82431c_f95f5633?us… : PS2, Line 9: MediaTek firmware support package (mtk-fsp) contains blob that include: > ``` […] Done File src/soc/mediatek/common/include/soc/memlayout.h: https://review.coreboot.org/c/coreboot/+/86013/comment/d69922da_8b2e27f3?us… : PS2, Line 16: #define FSP_INIT_CODE(addr, size) \ > And rename to `FSP_RAMSTAGE_INIT_CODE`. Done File src/soc/mediatek/mt8196/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/86013/comment/492c3f39_091ab905?us… : PS2, Line 67: FSP_INIT_CODE > FSP_RAMSTAGE_INIT_CODE Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21 Gerrit-Change-Number: 86013 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 10:34:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in romstage
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86014?usp=email ) Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in romstage ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8196/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/86014/comment/5f6f63d4_6ca091a0?us… : PS2, Line 60: FSP_INIT_CODE > Right. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86014?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73710227e6d9e3f0c717e17db0cc798265eb1f72 Gerrit-Change-Number: 86014 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 10:34:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in romstage
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86014?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in romstage ...................................................................... soc/mediatek/mt8196: Add mtk-fsp loader in romstage Reserve 64KB memory at 0x02140000 for mtk_fsp_romstage.elf. BUG=b:373797027 TEST=build pass Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Change-Id: I73710227e6d9e3f0c717e17db0cc798265eb1f72 --- M src/soc/mediatek/common/include/soc/memlayout.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/memlayout.ld 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/86014/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86014?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73710227e6d9e3f0c717e17db0cc798265eb1f72 Gerrit-Change-Number: 86014 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86013?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage ...................................................................... soc/mediatek/mt8196: Add mtk-fsp loader in ramstage MediaTek firmware support package (mtk-fsp) contains romstage and ramstage blobs. Add support for the ramstage blob, which includes: - UFS mphy settings. - DPAC (Device Access Permission Control) settings. - MMinfra (Multimedia Infrastrucutre) settings. - SMPU (Security Memory Protection Unit) settings. - Advanced CPU frequency control. BUG=b:373797027 TEST=build pass, boot ok. Load and run mtk_fsp with following logs: [INFO ] CBFS: Found 'fallback/mtk_fsp_ramstage' @0xfca00 size 0x263d in mcache @0xfffdd5a0 [DEBUG] read SPI 0x4fea88 0x263d: 773 us, 12663 KB/s, 101.304 Mbps [INFO ] VB2:vb2_digest_init() 9789 bytes, hash algo 2, HW acceleration enabled [INFO ] _start: MediaTek FSP_RAMSTAGE interface version: 1.0 [INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_ramstage at phase 0x50 done Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/memlayout.h M src/soc/mediatek/common/include/soc/mtk_fsp_common.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/memlayout.ld M src/soc/mediatek/mt8196/soc.c 5 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/86013/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21 Gerrit-Change-Number: 86013 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: mb/lenovo/x131e: Clean up USB configurations
by Patrick Rudolph (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui. Patrick Rudolph has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85944?usp=email ) Change subject: mb/lenovo/x131e: Clean up USB configurations ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85944?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bdc9a188b2baa2207aaccb46821b58f97ff7da6 Gerrit-Change-Number: 85944 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 10:21:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
by Jason-jh Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Jason-jh Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86027?usp=email ) Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86027/comment/b91d6f3d_6015d4ae?us… : PS1, Line 10: WLA > What is WLA ? Done https://review.coreboot.org/c/coreboot/+/86027/comment/a4165e8f_9c3d27db?us… : PS1, Line 12: power > whenever MMINFRA is powering on. Done https://review.coreboot.org/c/coreboot/+/86027/comment/8a7321cd_50978329?us… : PS1, Line 13: get hang > hang Done https://review.coreboot.org/c/coreboot/+/86027/comment/3f1816c3_50298fa5?us… : PS1, Line 16: TEST=Build pass > The issue looks serious. The TEST should not be build pass. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Gerrit-Change-Number: 86027 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 10:20:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
by Jason-jh Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Jason-jh Lin has uploaded a new patch set (#3) to the change originally created by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86027?usp=email ) Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra ...................................................................... soc/mediatek/mt8196: Add GCE ddren sel control to mminfra MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction ACK from SPM: 0, non-SPM: 0x1. In MT8196, SPM has masked all the DDR request, so this setting should be set to non-SPM whenever mminfra is powering on. Otherwise, GCE will hang when accessing DRAM. BUG=b:379039600 TEST=boot up ok, GCE can access DRAM countinuosly Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Signed-off-by: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/include/soc/mminfra.h M src/soc/mediatek/mt8196/mminfra.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/86027/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Gerrit-Change-Number: 86027 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/mediatek: Correct value's data type to u8 in dptx.
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85948?usp=email ) Change subject: soc/mediatek: Correct value's data type to u8 in dptx. ...................................................................... Patch Set 4: Code-Review+2 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85948/comment/86d3eeaa_ca5f9b56?us… : PS4, Line 6: > `Subject line should not end with a period.` Please fix. File src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h: https://review.coreboot.org/c/coreboot/+/85948/comment/7ec20a37_9a725235?us… : PS2, Line 87: int > Update? Done https://review.coreboot.org/c/coreboot/+/85948/comment/a93d71ed_16f4d7e7?us… : PS2, Line 103: int > And this, which comes from `mtk_dp->rx_cap[1]`, which is u8. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85948?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60bbb2c37811655692a5a8cd9f942fed4ead8abb Gerrit-Change-Number: 85948 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 10:18:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek: Modify MT6685 pmic driver
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86035?usp=email ) Change subject: soc/mediatek: Modify MT6685 pmic driver ...................................................................... soc/mediatek: Modify MT6685 pmic driver Use mt6685_write8 instead of mt6685_write16 when setting the protect key, only need 1 byte needs to be written to the register each time. TEST=Build pass. BUG=b:388666377 Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com> Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3 --- M src/soc/mediatek/common/mt6685.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/86035/1 diff --git a/src/soc/mediatek/common/mt6685.c b/src/soc/mediatek/common/mt6685.c index 7d17556..71ef476 100644 --- a/src/soc/mediatek/common/mt6685.c +++ b/src/soc/mediatek/common/mt6685.c @@ -74,7 +74,7 @@ static void mt6685_unlock(bool unlock) { for (int i = 0; i < ARRAY_SIZE(key_protect_setting); i++) - mt6685_write16(key_protect_setting[i].addr, + mt6685_write8(key_protect_setting[i].addr, unlock ? key_protect_setting[i].val : 0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3 Gerrit-Change-Number: 86035 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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