coreboot-gerrit January 2025

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[M] Change in coreboot[main]: [DO NOT MERGE]: Split PSP binaries to get 32M flash
by Maximilian Brune (Code Review) 17 Jan '25

17 Jan '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86036?usp=email ) Change subject: [DO NOT MERGE]: Split PSP binaries to get 32M flash ...................................................................... [DO NOT MERGE]: Split PSP binaries to get 32M flash This patch essentially moves the PSP binaries into the 16M part of the flash that is not accessible by the host (at least by default). Since the host doesn't need to read the PSP binaries we can save some megabytes on the 16M part of the flash that is accessible by the host. It adds seperate FMAP region which can be used to decide the placement of the PSP binaries on the flash. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I88488bfdca7ef8f848ffbab9c68670d8f375e90d --- M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.mk M util/amdfwtool/amdfwtool.c M util/amdfwtool/opts.c 4 files changed, 65 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/86036/1 diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 68a1b6f..d023101 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -94,6 +94,11 @@ if SOC_AMD_GLINDA +config AMDFW_SPLIT + bool + default y if COREBOOT_ROMSIZE_KB_32768 + select X86_CUSTOM_BOOTMEDIA + config CHIPSET_DEVICETREE string default "soc/amd/glinda/chipset.cb" diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk index 7f48581..5205910 100644 --- a/src/soc/amd/glinda/Makefile.mk +++ b/src/soc/amd/glinda/Makefile.mk @@ -131,6 +131,24 @@ APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE +ifeq ($(CONFIG_AMDFW_SPLIT),y) +regions-for-file-apu/amdfw=AMDFW +$(info region-amdfw $(call regions-for-file,apu/amdfw)) + +FMAP_AMDFW_BODY_LOCATION=$(call get_fmap_value,FMAP_SECTION_AMDFWBODY_START) +FMAP_AMDFW_BODY_PSP_LOCATION=$(call get_fmap_value,FMAP_SECTION_AMDFWBODY_PSP_START) + +OPT_AMDFW_BODY_LOCATION=$(call add_opt_prefix, $(FMAP_AMDFW_BODY_LOCATION), --body-location) +OPT_AMDFW_BODY_PSP_LOCATION=$(call add_opt_prefix, $(FMAP_AMDFW_BODY_PSP_LOCATION), --body-psp-location) + +$(obj)/amdfw.rom.body-psp: $(obj)/amdfw.rom +$(call add_intermediate, add_amdfwbody_psp, $(obj)/amdfw.rom.body-psp) + $(CBFSTOOL) $(obj)/coreboot.pre write -r AMDFWBODY_PSP -f $(obj)/amdfw.rom.body-psp --fill-upward +$(obj)/amdfw.rom.body: $(obj)/amdfw.rom +$(call add_intermediate, add_amdfwbody, $(obj)/amdfw.rom.body) + $(CBFSTOOL) $(obj)/coreboot.pre write -r AMDFWBODY -f $(obj)/amdfw.rom.body --fill-upward +endif # CONFIG_AMDFW_SPLIT + ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) # type = 0x6B - PSP Shared memory location ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) @@ -230,7 +248,9 @@ $(OPT_EFS_SPI_MICRON_FLAG) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ - $(OPT_RECOVERY_AB_SINGLE_COPY) + $(OPT_RECOVERY_AB_SINGLE_COPY) \ + $(OPT_AMDFW_BODY_PSP_LOCATION) \ + $(OPT_AMDFW_BODY_LOCATION) \ $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(PSP_VERSTAGE_FILE) \ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 9c6615c..798993d 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -969,6 +969,8 @@ ctx->current_table = current_table_save; } +static ssize_t body_psp_size = 0; //TODO put into context + static void integrate_psp_firmwares(context *ctx, amd_fw_entry *fw_table, uint32_t cookie, @@ -1023,6 +1025,13 @@ ctx->current_table = BUFF_TO_RUN_MODE(*ctx, pspdir, AMD_ADDR_REL_BIOS); adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); + uintptr_t saved_table_ptr = ctx->current; + if (cb_config->efs_location != cb_config->body_location) { + set_current_pointer(ctx, cb_config->body_psp_location + body_psp_size); + adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); + printf("before: %d\n", ctx->current); + } + for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) { if (!(fw_table[i].level & level)) continue; @@ -1118,6 +1127,10 @@ } } + if (cb_config->efs_location != cb_config->body_location) { + body_psp_size = ctx->current - cb_config->body_psp_location; + set_current_pointer(ctx, saved_table_ptr); + } fill_dir_header(pspdir, count, ctx); ctx->current_table = current_table_save; } @@ -1881,11 +1894,19 @@ ssize_t bytes; bytes = write_body(cb_config.output, BUFF_OFFSET(ctx, cb_config.body_location), - ctx.current - cb_config.body_location); + ctx.current - cb_config.body_location, ".body"); if (bytes != ctx.current - cb_config.body_location) { fprintf(stderr, "Error: Writing body\n"); retval = 1; } + + printf("body_psp_offset: %d\n", cb_config.body_psp_location); + printf("body_psp_size: %ld\n", body_psp_size); + bytes = write_body(cb_config.output, BUFF_OFFSET(ctx, cb_config.body_psp_location), body_psp_size, ".body-psp"); + if (bytes != body_psp_size) { + fprintf(stderr, "Error: Writing body psp\n"); + retval = 1; + } } if (cb_config.manifest_file) { diff --git a/util/amdfwtool/opts.c b/util/amdfwtool/opts.c index 62bbc97..0c07294 100644 --- a/util/amdfwtool/opts.c +++ b/util/amdfwtool/opts.c @@ -55,6 +55,7 @@ AMDFW_OPT_OUTPUT, AMDFW_OPT_FLASHSIZE, AMDFW_OPT_LOCATION, + AMDFW_OPT_PSP_LOCATION, AMDFW_OPT_ANYWHERE, AMDFW_OPT_SHAREDMEM, AMDFW_OPT_SHAREDMEM_SIZE, @@ -120,6 +121,7 @@ {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, {"body-location", required_argument, 0, AMDFW_OPT_BODY_LOCATION }, + {"body-psp-location", required_argument, 0, AMDFW_OPT_PSP_LOCATION }, // location of PSP firmware blobs (PSP directory still resides in body-location) /* other */ {"output", required_argument, 0, AMDFW_OPT_OUTPUT }, {"flashsize", required_argument, 0, AMDFW_OPT_FLASHSIZE }, @@ -611,7 +613,14 @@ retval = 1; } break; - + case AMDFW_OPT_PSP_LOCATION: + cb_config->body_psp_location = (uint32_t)strtoul(optarg, &tmp, 16); + if (*tmp != '\0') { + fprintf(stderr, "Error: Body PSP Location specified" + " incorrectly (%s)\n\n", optarg); + retval = 1; + } + break; default: break; } @@ -659,6 +668,10 @@ fprintf(stderr, "Error: Body location outside of ROM.\n\n"); return 1; } + if (cb_config->body_psp_location && cb_config->body_psp_location > ctx->rom_size) { + fprintf(stderr, "Error: Body PSP location outside of ROM.\n\n"); + return 1; + } if (!cb_config->efs_location && cb_config->body_location) { fprintf(stderr, "Error AMDFW body location specified without EFS location.\n"); @@ -724,9 +737,9 @@ printf(" AMDFWTOOL Using firmware directory location of address: 0x%08x", cb_config->efs_location); - if (cb_config->body_location != cb_config->efs_location) - printf(" with a split body at: 0x%08x\n", cb_config->body_location); - else + //if (cb_config->body_location != cb_config->efs_location) + // printf(" with a split body at: 0x%08x\n", cb_config->body_location); + //else printf("\n"); if (retval) { -- To view, visit https://review.coreboot.org/c/coreboot/+/86036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I88488bfdca7ef8f848ffbab9c68670d8f375e90d Gerrit-Change-Number: 86036 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/mt8196/thermal.c: https://review.coreboot.org/c/coreboot/+/86017/comment/d60be1b1_5a1d0054?us… : PS4, Line 324: op_cali[LVTS_AP_CONTROLLER0] = temp[5] & GENMASK(29, 24) >> 24; > > `Possible precedence defect with mask then right shift - may need parentheses` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 11:50:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: util/cbfstool: Remove existing file for add-int command
by Kapil Porwal (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Nicholas Chin. Kapil Porwal has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/86009?usp=email ) Change subject: util/cbfstool: Remove existing file for add-int command ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a0ac409fc9b91a4f7c0c35650875d6211ac2b25 Gerrit-Change-Number: 86009 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 11:50:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, Zhaoqing Jiu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86017?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... soc/mediatek/mt8196: Add thermal driver Add thermal driver to support LVTS (Low Voltage Thermal Sensor). TEST=Check temperatures read from each sensors. BUG=b:317009620 Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/thermal.h A src/soc/mediatek/mt8196/include/soc/thermal_internal.h A src/soc/mediatek/mt8196/thermal.c A src/soc/mediatek/mt8196/thermal_sram.c 7 files changed, 1,033 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/86017/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, agogo. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... Patch Set 9: (1 comment) File src/soc/mediatek/mt8196/mcupm.c: https://review.coreboot.org/c/coreboot/+/85888/comment/e3445b86_0b9dc300?us… : PS6, Line 21: "[EB_SPMC] Polling MCU_PORT_SET_R0_0 timeout, %#x\n", > Sorry to re-open again. No, it’s an error message and not a debug message. […] Agogo, please modify the code based on Paul's suggestion. -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 11:20:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85949?usp=email ) Change subject: soc/mediatek/mt8196: Add eDP driver ...................................................................... Patch Set 4: (11 comments) File src/soc/mediatek/mt8196/dp_intf.c: https://review.coreboot.org/c/coreboot/+/85949/comment/a29f5ec6_3fcdb5b3?us… : PS2, Line 91: 0x20 > Done not done https://review.coreboot.org/c/coreboot/+/85949/comment/4a3b716d_e8a8fdfc?us… : PS2, Line 99: gs_level > Done not done https://review.coreboot.org/c/coreboot/+/85949/comment/558a564c_70b28a91?us… : PS2, Line 162: 0x8000 > Done not done https://review.coreboot.org/c/coreboot/+/85949/comment/a725cef6_fa644d8f?us… : PS2, Line 198: mtk_dvo_power_on > Done Then can we rename this to `mtk_dpintf_power_on` for consistency? File src/soc/mediatek/mt8196/dptx.c: https://review.coreboot.org/c/coreboot/+/85949/comment/0a0bc373_7d554dce?us… : PS2, Line 257: mtk_dp->train_info.linkrate = (linkrate >= mtk_dp->train_info.sys_max_linkrate) ? > Done Not done. In PS4 you're still setting `mtk_dp->train_info.linkrate` here. https://review.coreboot.org/c/coreboot/+/85949/comment/c88cbd5d_e2b9e8ed?us… : PS2, Line 372: write32p(MMSYS1_CONFIG_BASE + MMSYS1_CG_CLR0, 0xFFFFFFFF); : write32p(MMSYS1_CONFIG_BASE + MMSYS1_CG_CLR1, 0x00040000); > Done So, could you answer my question? Do we need to set the same register twice? File src/soc/mediatek/mt8196/dptx_hal.c: https://review.coreboot.org/c/coreboot/+/85949/comment/a2726af1_9002114a?us… : PS2, Line 52: switch (out_format) { > Done Not done. Please define a local variable `u32 val`. https://review.coreboot.org/c/coreboot/+/85949/comment/2db36043_30024981?us… : PS2, Line 146: switch (value) { > Done Not done. Please define a local variable `u32 val`. https://review.coreboot.org/c/coreboot/+/85949/comment/5b89ab17_feefaf04?us… : PS2, Line 307: mtk_edp_hal_reset_swing_pre_emphasis > Done Yes, I know these 2 functions are different. I'm asking if we can name the functions better. Does it make sense to rename this function to `dptx_hal_reset_swing_preemphasis`? File src/soc/mediatek/mt8196/include/soc/dp_intf.h: https://review.coreboot.org/c/coreboot/+/85949/comment/659e697c_eb415d39?us… : PS2, Line 199: gs_level > Done not done File src/soc/mediatek/mt8196/include/soc/dptx_hal.h: https://review.coreboot.org/c/coreboot/+/85949/comment/54123b85_9b3b445e?us… : PS2, Line 38: void mtk_edp_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp); : void mtk_edp_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable); : void mtk_edp_set_swing_pre_emphasis > Done So, you think `mtk_dp_` makes better sense than `dptx_hal_`? Why? -- To view, visit https://review.coreboot.org/c/coreboot/+/85949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Gerrit-Change-Number: 85949 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 11:18:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, Zhaoqing Jiu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86017?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... soc/mediatek/mt8196: Add thermal driver Add thermal driver to support LVTS (Low Voltage Thermal Sensor). TEST=Check temperatures read from each sensors. BUG=b:317009620 Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/thermal.h A src/soc/mediatek/mt8196/include/soc/thermal_internal.h A src/soc/mediatek/mt8196/thermal.c A src/soc/mediatek/mt8196/thermal_sram.c 7 files changed, 1,033 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/86017/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: mb/google/volteer/variants/drobit: fix power_limits_config
by Paul Menzel (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Ariel Chang, Ingo Reitz, Nick Vaccaro, Paul Yang, Wayne3 Wang. Paul Menzel has posted comments on this change by Ingo Reitz. ( https://review.coreboot.org/c/coreboot/+/86026?usp=email ) Change subject: mb/google/volteer/variants/drobit: fix power_limits_config ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86026/comment/f9f30018_dd296389?us… : PS4, Line 9: Drobit shows little power usage and very low clock speeds under load, : despite being at very low temperatures. It turns out that : power_limits_config is set to the lower end of the dptf power limit : ranges as opposed to baseboard and other variants. This seems to : prevent the device from using the intended power limits. > i was unable to find any documentation on the changed values, but from what i observed the pl1 max v […] Understood. Thank you for your quick follow-ups. -- To view, visit https://review.coreboot.org/c/coreboot/+/86026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0478c713b51db4972e7d93ec597a30fa885c22b Gerrit-Change-Number: 86026 Gerrit-PatchSet: 6 Gerrit-Owner: Ingo Reitz <9l(a)9lo.re> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Attention: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ingo Reitz <9l(a)9lo.re> Gerrit-Comment-Date: Fri, 17 Jan 2025 11:09:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Ingo Reitz <9l(a)9lo.re>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in romstage
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

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