coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param
by Mario Scheithauer (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Johannes Hahn, Uwe Poeche, Werner Zeh. Mario Scheithauer has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/86068?usp=email ) Change subject: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5 Gerrit-Change-Number: 86068 Gerrit-PatchSet: 3 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 06:27:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/google/brya: Create pujjoniru variant
by Qinghong Zeng (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Subrata Banik. Qinghong Zeng has posted comments on this change by Qinghong Zeng. ( https://review.coreboot.org/c/coreboot/+/85844?usp=email ) Change subject: mb/google/brya: Create pujjoniru variant ...................................................................... Patch Set 11: (3 comments) File src/mainboard/google/brya/variants/pujjoniru/Makefile.mk: https://review.coreboot.org/c/coreboot/+/85844/comment/1f087413_4d2a8ab4?us… : PS10, Line 2: bootblock-y += gpio.c > please use one empty line between header and next line Done File src/mainboard/google/brya/variants/pujjoniru/gpio.c: https://review.coreboot.org/c/coreboot/+/85844/comment/6a6873f0_4d5529c2?us… : PS10, Line 183: > empty line Done File src/mainboard/google/brya/variants/pujjoniru/variant.c: https://review.coreboot.org/c/coreboot/+/85844/comment/e0236a45_d60ef7d2?us… : PS10, Line 17: if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || fw_config_probe(FW_CONFIG(WIFI, WIFI_UNKNOWN))) { > isn't this line need a line break (> 96 col)? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0 Gerrit-Change-Number: 85844 Gerrit-PatchSet: 11 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-CC: Cindy Lu <luyi8(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 06:22:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param
by Johannes Hahn (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Mario Scheithauer, Uwe Poeche, Werner Zeh. Johannes Hahn has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/86068?usp=email ) Change subject: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86068/comment/f4941abd_3e0545aa?us… : PS2, Line 12: ba > typo Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5 Gerrit-Change-Number: 86068 Gerrit-PatchSet: 3 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 06:20:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Uwe Poeche <uwe.poeche(a)siemens.com>

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[XS] Change in coreboot[main]: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param
by Johannes Hahn (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Johannes Hahn, Mario Scheithauer, Uwe Poeche, Werner Zeh. Hello Intel coreboot Reviewers, Mario Scheithauer, Uwe Poeche, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86068?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Mario Scheithauer, Code-Review+1 by Uwe Poeche, Verified+1 by build bot (Jenkins) Change subject: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param ...................................................................... soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param According to Intel's recommendation for Time Coordinated Computing (TCC) the FSP-S parameter PchLegacyIoLowLatency should be set to 'Enabled' in order to promote low latencies on the PCH. With the previous setting 'Disabled' low latencies on the PCH for I/O operations are not enhanced. Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5 Signed-off-by: Johannes Hahn <johannes-hahn(a)siemens.com> --- M src/soc/intel/elkhartlake/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/86068/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5 Gerrit-Change-Number: 86068 Gerrit-PatchSet: 3 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>

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[L] Change in coreboot[main]: mb/google/brya: Create pujjoniru variant
by hualin wei (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Qinghong Zeng, Subrata Banik. hualin wei has posted comments on this change by Qinghong Zeng. ( https://review.coreboot.org/c/coreboot/+/85844?usp=email ) Change subject: mb/google/brya: Create pujjoniru variant ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0 Gerrit-Change-Number: 85844 Gerrit-PatchSet: 11 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-CC: Cindy Lu <luyi8(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 06:17:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param
by Uwe Poeche (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Johannes Hahn, Mario Scheithauer, Werner Zeh. Uwe Poeche has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/86068?usp=email ) Change subject: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86068/comment/e37bc424_ce4078a1?us… : PS2, Line 12: ba typo -- To view, visit https://review.coreboot.org/c/coreboot/+/86068?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5 Gerrit-Change-Number: 86068 Gerrit-PatchSet: 2 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 06:16:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/google/brya: Create pujjoniru variant
by Qinghong Zeng (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Qinghong Zeng, Subrata Banik, hualin wei. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Subrata Banik, build bot (Jenkins), hualin wei, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85844?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+1 by hualin wei, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: mb/google/brya: Create pujjoniru variant ...................................................................... mb/google/brya: Create pujjoniru variant Create the pujjoniru variant of the nissa reference board by copying the template files to a new directory named for the variant. And based on schematics PujjoNiru_C5_CHROME_TWL_SCH_MB_V1_1225A.pdf update devicetree settings. (Auto-Generated by create_coreboot_variant.sh version 4.5.0) BUG=b:386221423 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJONIRU Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0 Signed-off-by: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/pujjoniru/Makefile.mk A src/mainboard/google/brya/variants/pujjoniru/gpio.c A src/mainboard/google/brya/variants/pujjoniru/include/variant/ec.h A src/mainboard/google/brya/variants/pujjoniru/include/variant/gpio.h A src/mainboard/google/brya/variants/pujjoniru/memory/Makefile.mk A src/mainboard/google/brya/variants/pujjoniru/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/pujjoniru/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/pujjoniru/overridetree.cb A src/mainboard/google/brya/variants/pujjoniru/variant.c 11 files changed, 898 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/85844/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/85844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0 Gerrit-Change-Number: 85844 Gerrit-PatchSet: 11 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-CC: Cindy Lu <luyi8(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Enable vcore DVFS in romstage
by Yu-Ping Wu (Code Review) 21 Jan '25

21 Jan '25

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add vcore DVFS settings
by Yu-Ping Wu (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86070?usp=email ) Change subject: soc/mediatek/mt8196: Add vcore DVFS settings ...................................................................... Patch Set 1: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86070/comment/ae38b968_6ee99ad6?us… : PS1, Line 9: so that https://review.coreboot.org/c/coreboot/+/86070/comment/7325aee7_bcb0a5f1?us… : PS1, Line 9: tinsys `tinysys`? https://review.coreboot.org/c/coreboot/+/86070/comment/39a410a5_b38b211a?us… : PS1, Line 9: ccore `vcore`? File src/soc/mediatek/mt8196/include/soc/mtk_vcore_opp.h: https://review.coreboot.org/c/coreboot/+/86070/comment/2e449364_c6d52695?us… : PS1, Line 8: Explain what "opp" means. https://review.coreboot.org/c/coreboot/+/86070/comment/b8acb4ff_c6d29098?us… : PS1, Line 9: extern remove File src/soc/mediatek/mt8196/mtk_vcore_opp.c: PS1: Drop `mtk_` from the file name. Does it make sense to rename this to `dvfsrc.c`? -- To view, visit https://review.coreboot.org/c/coreboot/+/86070?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d3e1d6ea648af938d41a5c9461cdd2972371177 Gerrit-Change-Number: 86070 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 06:06:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/lenovo/x131e: Clean up USB configurations
by Elyes Haouas (Code Review) 21 Jan '25

21 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85944?usp=email ) Change subject: mb/lenovo/x131e: Clean up USB configurations ...................................................................... mb/lenovo/x131e: Clean up USB configurations As of commit a911b7584820 ("mb/*: Remove old USB configurations from SNB/bd82x6x boards") USB configurations are drawn exclusively from devicetree. The old copy carried by early_init.c should have been removed back then. Since it has nothing else, drop the whole file. Remove xhci_overcurrent_mapping as it is now derived from usb_port_config. According to schematics only the first two ports are wired for xHCI and both goes to OC0#. Remove OC pin assignment from disabled third port so the (former) xhci_overcurrent_mapping can be derived correctly. Also adjust xhci_switchable_ports and superspeed_capable_ports to match. Thanks to Patrick Rudolph for the information. Change-Id: I6bdc9a188b2baa2207aaccb46821b58f97ff7da6 Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85944 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/x131e/Makefile.mk M src/mainboard/lenovo/x131e/devicetree.cb D src/mainboard/lenovo/x131e/early_init.c 3 files changed, 3 insertions(+), 26 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/mainboard/lenovo/x131e/Makefile.mk b/src/mainboard/lenovo/x131e/Makefile.mk index e4b6fbf..7611194 100644 --- a/src/mainboard/lenovo/x131e/Makefile.mk +++ b/src/mainboard/lenovo/x131e/Makefile.mk @@ -4,5 +4,3 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index b74e78f..dfd11d5 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -40,13 +40,12 @@ register "gen3_dec" = "0x000c0701" register "gen4_dec" = "0x000c06a1" - register "xhci_switchable_ports" = "0xf" - register "superspeed_capable_ports" = "0xf" - register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x3" + register "superspeed_capable_ports" = "0x3" register "usb_port_config" = "{ {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ - {0, 0, 0}, + {0, 0, -1}, {1, 1, -1}, /* P3: Camera (no OC) */ {1, 0, -1}, /* P4: WLAN (no OC) */ {1, 0, -1}, /* P5: WWAN (no OC) */ diff --git a/src/mainboard/lenovo/x131e/early_init.c b/src/mainboard/lenovo/x131e/early_init.c deleted file mode 100644 index 410dea6..0000000 --- a/src/mainboard/lenovo/x131e/early_init.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ - {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ - {0, 0, 0}, - {1, 1, -1}, /* P3: Camera (no OC) */ - {1, 0, -1}, /* P4: WLAN (no OC) */ - {1, 0, -1}, /* P5: WWAN (no OC) */ - {0, 0, 0}, - {0, 0, 0}, - {0, 0, 0}, - {1, 1, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ - {0, 0, 0}, - {0, 0, 0}, - {0, 0, 0}, - {1, 0, -1}, /* P13: Bluetooth (no OC) */ -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85944?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bdc9a188b2baa2207aaccb46821b58f97ff7da6 Gerrit-Change-Number: 85944 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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