coreboot-gerrit January 2025

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[S] Change in coreboot[main]: mb/google/brya/var/dirks: Generate SPD ID for supported parts
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85970?usp=email ) Change subject: mb/google/brya/var/dirks: Generate SPD ID for supported parts ...................................................................... mb/google/brya/var/dirks: Generate SPD ID for supported parts Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. 1. MT62F1G32D4DR-031 WT:B (Mircon) 2. MT62F512M32D2DR-031 WT:B (Mircon) 3. H9JCNNNBK3MLYR-N6E (Hynix) 4. K3LKLKL0EM-MGCN (Samsung) 5. K3LKBKB0BM-MGCP (Samsung) 6. H9JCNNNCP3MLYR-N6E (Hynix) 7. K3KL8L80CM-MGCT (Samsung) 8. H58G56BK8BX068 (Hynix) BUG=b:388117663 TEST=Run part_id_gen tool and check the generated files. Change-Id: I969b91bb38c69738b442feee60e68a6efdba85d2 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85970 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/dirks/memory/Makefile.mk M src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt 3 files changed, 30 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved Ivy Jian: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk b/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk index eace2e4..2d0d1bb 100644 --- a/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk @@ -1,5 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/dirks/memory/ src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-5.hex # ID = 2(0b0010) Parts = K3LKLKL0EM-MGCN +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 3(0b0011) Parts = K3LKBKB0BM-MGCP +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 4(0b0100) Parts = K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 5(0b0101) Parts = H58G56BK8BX068 diff --git a/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt index fa24790..c10bbb7 100644 --- a/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt @@ -1 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/dirks/memory/ src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt + DRAM Part Name ID to assign +MT62F1G32D4DR-031 WT:B 0 (0000) +MT62F512M32D2DR-031 WT:B 1 (0001) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3LKLKL0EM-MGCN 2 (0010) +K3LKBKB0BM-MGCP 3 (0011) +H9JCNNNCP3MLYR-N6E 0 (0000) +K3KL8L80CM-MGCT 4 (0100) +H58G56BK8BX068 5 (0101) diff --git a/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt index 2499005..2c18a19 100644 --- a/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt @@ -9,3 +9,11 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +MT62F1G32D4DR-031 WT:B +MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +K3LKLKL0EM-MGCN +K3LKBKB0BM-MGCP +H9JCNNNCP3MLYR-N6E +K3KL8L80CM-MGCT +H58G56BK8BX068 -- To view, visit https://review.coreboot.org/c/coreboot/+/85970?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I969b91bb38c69738b442feee60e68a6efdba85d2 Gerrit-Change-Number: 85970 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/brya/var/dirks: Generate SPD ID for supported parts
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: David Wu, Dinesh Gehlot, Ivy Jian, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85970?usp=email ) Change subject: mb/google/brya/var/dirks: Generate SPD ID for supported parts ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85970?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I969b91bb38c69738b442feee60e68a6efdba85d2 Gerrit-Change-Number: 85970 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 21 Jan 2025 04:22:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/nissa: Create dirks variant
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85947?usp=email ) Change subject: mb/google/nissa: Create dirks variant ...................................................................... mb/google/nissa: Create dirks variant Create the dirks variant of nissa reference board by copying the template files to a new directory named for the variant. The dirks variant is a twinlake platform. BUG=b:389391653 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_DIRKS Change-Id: I57ffb6025ee2115fa558668dc685a1970fc738d0 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85947 Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/dirks/include/variant/ec.h A src/mainboard/google/brya/variants/dirks/include/variant/gpio.h A src/mainboard/google/brya/variants/dirks/memory/Makefile.mk A src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/dirks/overridetree.cb 8 files changed, 50 insertions(+), 0 deletions(-) Approvals: Jayvik Desai: Looks good to me, approved Subrata Banik: Looks good to me, approved Dtrain Hsu: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index e4f563e..2968007 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -219,6 +219,10 @@ select INTEL_GMA_HAVE_VBT select SOC_INTEL_RAPTORLAKE +config BOARD_GOOGLE_DIRKS + select BOARD_GOOGLE_BASEBOARD_NISSA + select SOC_INTEL_TWINLAKE + config BOARD_GOOGLE_DOCHI select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_WIFI_SAR if CHROMEOS @@ -738,6 +742,7 @@ default 0x0 if BOARD_GOOGLE_CRAASK default 0x0 if BOARD_GOOGLE_CRAASKOV default 0x1 if BOARD_GOOGLE_CROTA + default 0x0 if BOARD_GOOGLE_DIRKS default 0x1 if BOARD_GOOGLE_DOCHI default 0x0 if BOARD_GOOGLE_DOMIKA default 0x1 if BOARD_GOOGLE_FELWINTER @@ -817,6 +822,7 @@ default 13 if BOARD_GOOGLE_CRAASK default 13 if BOARD_GOOGLE_CRAASKOV default 13 if BOARD_GOOGLE_CROTA + default 13 if BOARD_GOOGLE_DIRKS default 13 if BOARD_GOOGLE_DOCHI default 13 if BOARD_GOOGLE_DOMIKA default 13 if BOARD_GOOGLE_FELWINTER @@ -900,6 +906,7 @@ default "Craask" if BOARD_GOOGLE_CRAASK default "Craaskov" if BOARD_GOOGLE_CRAASKOV default "Crota" if BOARD_GOOGLE_CROTA + default "Dirks" if BOARD_GOOGLE_DIRKS default "Dochi" if BOARD_GOOGLE_DOCHI default "Domika" if BOARD_GOOGLE_DOMIKA default "Felwinter" if BOARD_GOOGLE_FELWINTER @@ -972,6 +979,7 @@ default "craask" if BOARD_GOOGLE_CRAASK default "craaskov" if BOARD_GOOGLE_CRAASKOV default "crota" if BOARD_GOOGLE_CROTA + default "dirks" if BOARD_GOOGLE_DIRKS default "dochi" if BOARD_GOOGLE_DOCHI default "yavilla" if BOARD_GOOGLE_DOMIKA default "felwinter" if BOARD_GOOGLE_FELWINTER diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 7dd82d0..7108474 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -38,6 +38,9 @@ config BOARD_GOOGLE_CROTA bool "-> Crota" +config BOARD_GOOGLE_DIRKS + bool "-> Dirks" + config BOARD_GOOGLE_DOCHI bool "-> Dochi" diff --git a/src/mainboard/google/brya/variants/dirks/include/variant/ec.h b/src/mainboard/google/brya/variants/dirks/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/dirks/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/dirks/include/variant/gpio.h b/src/mainboard/google/brya/variants/dirks/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirks/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk b/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirks/memory/Makefile.mk @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirks/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt new file mode 100644 index 0000000..2499005 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirks/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/85947?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57ffb6025ee2115fa558668dc685a1970fc738d0 Gerrit-Change-Number: 85947 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable SAGv
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85272?usp=email ) Change subject: mb/google/fatcat: Enable SAGv ...................................................................... mb/google/fatcat: Enable SAGv Enable SaGv support for fatcat BUG=None BRANCH=None TEST=Boot fatcat with SAGv enabled and verify in fsp debug logs Change-Id: I340f4951fd33deadaac53edd30e2cf6bfc2a750b Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85272 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index b9dcbbd..ec87353 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -30,6 +30,9 @@ register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2 register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 + # Enable SAGv + register "sagv" = "SAGV_ENABLED" + # Enable s0ix register "s0ix_enable" = "false" -- To view, visit https://review.coreboot.org/c/coreboot/+/85272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I340f4951fd33deadaac53edd30e2cf6bfc2a750b Gerrit-Change-Number: 85272 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/google/brya: Create pujjoniru variant
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Qinghong Zeng. Subrata Banik has posted comments on this change by Qinghong Zeng. ( https://review.coreboot.org/c/coreboot/+/85844?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/brya: Create pujjoniru variant ...................................................................... Patch Set 10: (3 comments) File src/mainboard/google/brya/variants/pujjoniru/Makefile.mk: https://review.coreboot.org/c/coreboot/+/85844/comment/c39e8dc2_09ef108d?us… : PS10, Line 2: bootblock-y += gpio.c please use one empty line between header and next line File src/mainboard/google/brya/variants/pujjoniru/gpio.c: https://review.coreboot.org/c/coreboot/+/85844/comment/91386952_ac1a0c78?us… : PS10, Line 183: empty line File src/mainboard/google/brya/variants/pujjoniru/variant.c: https://review.coreboot.org/c/coreboot/+/85844/comment/7a5b96a9_ad4c9a7f?us… : PS10, Line 17: if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || fw_config_probe(FW_CONFIG(WIFI, WIFI_UNKNOWN))) { isn't this line need a line break (> 96 col)? -- To view, visit https://review.coreboot.org/c/coreboot/+/85844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0 Gerrit-Change-Number: 85844 Gerrit-PatchSet: 10 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-CC: Cindy Lu <luyi8(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 04:21:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/google/brya: Create pujjoniru variant
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Qinghong Zeng. Subrata Banik has posted comments on this change by Qinghong Zeng. ( https://review.coreboot.org/c/coreboot/+/85844?usp=email ) Change subject: mb/google/brya: Create pujjoniru variant ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85844?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0 Gerrit-Change-Number: 85844 Gerrit-PatchSet: 10 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-CC: Cindy Lu <luyi8(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 04:15:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Modify the felino config for probing TPM...
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85965?usp=email ) Change subject: mb/google/fatcat/var/felino: Modify the felino config for probing TPM I2C ...................................................................... mb/google/fatcat/var/felino: Modify the felino config for probing TPM I2C Modify the configuration to detect TPM I2C correctly. BUG=b:388982526 TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino Change-Id: I093c0bad181f133e601f3270de68c0848f847ccf Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85965 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/felino/gpio.c M src/mainboard/google/fatcat/variants/felino/overridetree.cb 3 files changed, 14 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Weimin Wu: Looks good to me, but someone else must approve Jayvik Desai: Looks good to me, approved Dtrain Hsu: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index f408c0b..e82081d 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -118,6 +118,7 @@ hex default 0x03 if BOARD_GOOGLE_MODEL_FATCAT default 0x01 if BOARD_GOOGLE_FRANCKA + default 0x01 if BOARD_GOOGLE_FELINO config HAVE_SLP_S0_GATE def_bool n diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c index 645746f..6c75a41 100644 --- a/src/mainboard/google/fatcat/variants/felino/gpio.c +++ b/src/mainboard/google/fatcat/variants/felino/gpio.c @@ -278,7 +278,7 @@ /* GPP_F14: NC */ PAD_NC(GPP_F14, NONE), /* GPP_F15: GSC_PCH_INT_ODL */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_GPI_APIC(GPP_F15, NONE, PLTRST, LEVEL, INVERT), /* GPP_F16: NC */ PAD_NC(GPP_F16, NONE), /* GPP_F17: NC */ @@ -399,12 +399,12 @@ /* GPP_H09: UART0_BUF_TXD */ PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), - /* GPP_H06: I2C3_SDA_PSS */ - PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), - /* GPP_H07: I2C3_SCL_PSS */ - PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), - /* GPP_D15: SPI_TPM_INT_N */ - PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT), + /* GPP_H21: PCH_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22: PCH_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* GPP_F15: SPI_TPM_INT_N */ + PAD_CFG_GPI_APIC(GPP_F15, NONE, PLTRST, LEVEL, INVERT), }; /* Pad configuration in romstage */ diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb index 1f3d07b..28072d5 100644 --- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb @@ -47,6 +47,12 @@ [DDI_PORT_A] = DDI_ENABLE_HPD, }" + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/85965?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I093c0bad181f133e601f3270de68c0848f847ccf Gerrit-Change-Number: 85965 Gerrit-PatchSet: 4 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Update LAN settings for EVT
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Kenneth Chan, Tarun. Subrata Banik has posted comments on this change by Kenneth Chan. ( https://review.coreboot.org/c/coreboot/+/86072?usp=email ) Change subject: mb/google/rex/var/kanix: Update LAN settings for EVT ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8be74c601a536f1aa932dd6c14ae3f5068d0a7f Gerrit-Change-Number: 86072 Gerrit-PatchSet: 3 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 04:14:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Rename mtk_pwrsel.* to pwrsel.*
by Yidi Lin (Code Review) 21 Jan '25

21 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86059?usp=email ) Change subject: soc/mediatek/mt8196: Rename mtk_pwrsel.* to pwrsel.* ...................................................................... soc/mediatek/mt8196: Rename mtk_pwrsel.* to pwrsel.* As the mtk_pwrsel.{c,h} files are already under the soc/mediatek directory, drop the file name prefix "mtk_" from them. BUG=b:317009620 TEST=none Change-Id: I28131d44067c33b5d8682a85cc8a73fc42604de3 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86059 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rauru/romstage.c M src/soc/mediatek/mt8196/Makefile.mk R src/soc/mediatek/mt8196/include/soc/pwrsel.h R src/soc/mediatek/mt8196/pwrsel.c 4 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index 32c8a61..7677995 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -10,10 +10,10 @@ #include <soc/mt6373.h> #include <soc/mt6685.h> #include <soc/mtk_fsp.h> -#include <soc/mtk_pwrsel.h> #include <soc/pcie.h> #include <soc/pll.h> #include <soc/pmif.h> +#include <soc/pwrsel.h> #include <soc/srclken_rc.h> static void raise_little_cpu_freq(void) diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 0ef442f..c12d7b0 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -41,7 +41,7 @@ romstage-y += ../common/mt6373.c mt6373.c romstage-y += ../common/mt6685.c mt6685.c romstage-y += ../common/mtk_fsp.c -romstage-y += mtk_pwrsel.c +romstage-y += pwrsel.c romstage-y += ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif.c pmif_init.c romstage-y += pmif_spmi.c diff --git a/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h b/src/soc/mediatek/mt8196/include/soc/pwrsel.h similarity index 74% rename from src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h rename to src/soc/mediatek/mt8196/include/soc/pwrsel.h index 327735e..7928ff9 100644 --- a/src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h +++ b/src/soc/mediatek/mt8196/include/soc/pwrsel.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ -#ifndef __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ -#define __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ +#ifndef __SOC_MEDIATEK_MT8196_PWRSEL__ +#define __SOC_MEDIATEK_MT8196_PWRSEL__ #include <soc/addressmap.h> @@ -15,4 +15,4 @@ void pwrsel_init(void); -#endif /* end of __SOC_MEDIATEK_MT8196_MTK_PWRSEL__ */ +#endif /* end of __SOC_MEDIATEK_MT8196_PWRSEL__ */ diff --git a/src/soc/mediatek/mt8196/mtk_pwrsel.c b/src/soc/mediatek/mt8196/pwrsel.c similarity index 95% rename from src/soc/mediatek/mt8196/mtk_pwrsel.c rename to src/soc/mediatek/mt8196/pwrsel.c index b1cb528..9a4a574 100644 --- a/src/soc/mediatek/mt8196/mtk_pwrsel.c +++ b/src/soc/mediatek/mt8196/pwrsel.c @@ -2,7 +2,7 @@ #include <console/console.h> #include <device/mmio.h> -#include <soc/mtk_pwrsel.h> +#include <soc/pwrsel.h> static void cpu_pwrsel_init(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/86059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28131d44067c33b5d8682a85cc8a73fc42604de3 Gerrit-Change-Number: 86059 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Shunxi Zhang (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin. Shunxi Zhang has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/mt8196/include/soc/rtc.h: https://review.coreboot.org/c/coreboot/+/85978/comment/dbdfbc8d_7920f16c?us… : PS1, Line 18: RTC_BBPU_PWREN = BIT(0), > Given the limited time we have, Yidi meant to revert mt6685_hw.h, mt6685_rtc_hw. […] How to deal with mt6685_rtc.h ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 03:59:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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