coreboot-gerrit January 2025

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[S] Change in coreboot[main]: mb/lenovo/x131e: Clean up USB configurations
by Elyes Haouas (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui. Elyes Haouas has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85944?usp=email ) Change subject: mb/lenovo/x131e: Clean up USB configurations ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85944?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bdc9a188b2baa2207aaccb46821b58f97ff7da6 Gerrit-Change-Number: 85944 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 05:02:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/lenovo/t530: Remove old USB configurations
by Elyes Haouas (Code Review) 21 Jan '25

21 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85943?usp=email ) Change subject: mb/lenovo/t530: Remove old USB configurations ...................................................................... mb/lenovo/t530: Remove old USB configurations As of commit a911b7584820 ("mb/*: Remove old USB configurations from SNB/bd82x6x boards") USB configurations are drawn exclusively from devicetree. These stuff should have been removed then. Drop romstage.c from both variants that only carries the old USB configurations and xhci_overcurrent_mapping devicetree setting that is now derived from usb_port_config (they match). Change-Id: I1a5d57ae9e3788e0c7788013c6fe387ec83efcf2 Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85943 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/t530/Makefile.mk M src/mainboard/lenovo/t530/devicetree.cb D src/mainboard/lenovo/t530/variants/t530/romstage.c D src/mainboard/lenovo/t530/variants/w530/romstage.c 4 files changed, 0 insertions(+), 42 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/lenovo/t530/Makefile.mk b/src/mainboard/lenovo/t530/Makefile.mk index a3b838b..69ef088 100644 --- a/src/mainboard/lenovo/t530/Makefile.mk +++ b/src/mainboard/lenovo/t530/Makefile.mk @@ -2,7 +2,6 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c -romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 4673aba..305a47e 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -46,7 +46,6 @@ register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" - register "xhci_overcurrent_mapping" = "0x04000201" register "docking_supported" = "true" diff --git a/src/mainboard/lenovo/t530/variants/t530/romstage.c b/src/mainboard/lenovo/t530/variants/t530/romstage.c deleted file mode 100644 index 2290bce..0000000 --- a/src/mainboard/lenovo/t530/variants/t530/romstage.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ - { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ - { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */ - { 1, 1, -1 }, /* P3: WWAN slot, no OC */ - { 1, 1, 2 }, /* P4: yellow USB, OC 2 */ - { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 1, 2, -1 }, /* P7: docking, no OC */ - { 1, 0, -1 }, /* P8: smart card reader, no OC */ - { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 0, -1 }, /* P11: bluetooth, no OC. */ - { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/ - { 1, 1, -1 }, /* P13: camera, no OC */ -}; diff --git a/src/mainboard/lenovo/t530/variants/w530/romstage.c b/src/mainboard/lenovo/t530/variants/w530/romstage.c deleted file mode 100644 index 7458d1a..0000000 --- a/src/mainboard/lenovo/t530/variants/w530/romstage.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ - { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ - { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */ - { 1, 1, -1 }, /* P3: WWAN slot, no OC */ - { 1, 1, 2 }, /* P4: yellow USB, OC 2 */ - { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */ - { 1, 0, -1 }, /* P6: color sensor, no OC */ - { 1, 2, -1 }, /* P7: docking, no OC */ - { 1, 0, -1 }, /* P8: smart card reader, no OC */ - { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 0, -1 }, /* P11: bluetooth, no OC. */ - { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/ - { 1, 1, -1 }, /* P13: camera, no OC */ -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85943?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a5d57ae9e3788e0c7788013c6fe387ec83efcf2 Gerrit-Change-Number: 85943 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/lenovo/t530: Remove old USB configurations
by Elyes Haouas (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui. Elyes Haouas has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85943?usp=email ) Change subject: mb/lenovo/t530: Remove old USB configurations ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85943?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a5d57ae9e3788e0c7788013c6fe387ec83efcf2 Gerrit-Change-Number: 85943 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 05:01:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping
by Elyes Haouas (Code Review) 21 Jan '25

21 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85922?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping ...................................................................... sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping As xHCI ports 1-4 and OC pins 0-3 are all shared with EHCI, xhci_overcurrent_mapping should never deviate from the USB 2 (EHCI) overcurrent mapping specified in the USB port config in the devicetree. Get the mapping from EHCI and free mainboards from specifying it separately. A Ghidra inspection of MRC binary indicates it is doing the same. After this patch xhci_overcurrent_mapping becomes redundant and will be removed in a follow-up. Change-Id: Iab30a07c8df223e4053c5f28df5e5ed926f278f7 Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85922 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/usb_xhci.c 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: Elyes Haouas: Looks good to me, but someone else must approve Jérémy Compostella: Looks good to me, but someone else must approve build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index f71a505..358d107 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -7,6 +7,7 @@ #include "pch.h" #include <device/pci_ehci.h> #include <device/pci_ops.h> +#include <southbridge/intel/common/rcba.h> #include "chip.h" static void usb_xhci_init(struct device *dev) @@ -16,8 +17,8 @@ printk(BIOS_DEBUG, "XHCI: Setting up controller.. "); - if (config->xhci_overcurrent_mapping) - pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping); + reg32 = RCBA32(USBOCM1) & 0x0f0f0f0f; + pci_write_config32(dev, XOCM, reg32); /* lock overcurrent map */ pci_or_config32(dev, 0x44, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/85922?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab30a07c8df223e4053c5f28df5e5ed926f278f7 Gerrit-Change-Number: 85922 Gerrit-PatchSet: 5 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/rauru: Enable vcore DVFS in romstage
by Jarried Lin (Code Review) 21 Jan '25

21 Jan '25

Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86071?usp=email ) Change subject: mb/google/rauru: Enable vcore DVFS in romstage ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/86071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idcd9754c1974f1d6fdb26d7c6af1e2863cb724f7 Gerrit-Change-Number: 86071 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 21 Jan 2025 04:52:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add vcore DVFS settings
by Jarried Lin (Code Review) 21 Jan '25

21 Jan '25

Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86070?usp=email ) Change subject: soc/mediatek/mt8196: Add vcore DVFS settings ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/86070?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d3e1d6ea648af938d41a5c9461cdd2972371177 Gerrit-Change-Number: 86070 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 21 Jan 2025 04:52:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Yidi Lin (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 6: (1 comment) File src/soc/mediatek/mt8196/include/soc/rtc.h: https://review.coreboot.org/c/coreboot/+/85978/comment/91f2ed2e_bf39a1f9?us… : PS1, Line 18: RTC_BBPU_PWREN = BIT(0), > How to deal with mt6685_rtc. […] Checkout PS5 and overwritten mt6685_hw.h, mt6685_rtc_hw.h with PS2 version. -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 04:37:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Julius Werner, Jérémy Compostella, Nicholas Chin, Swift Geek (Sebastian Grzywna). Subrata Banik has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 16 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 04:25:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Update eMMC DLL settings
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86016?usp=email ) Change subject: mb/trulo/var/uldrenite: Update eMMC DLL settings ...................................................................... mb/trulo/var/uldrenite: Update eMMC DLL settings Based on Intel eMMC tuning result, update eMMC DLL settings. BUG=b:388438199 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I276ebbfc29e3899cbacdc2353648017a3fa5b8a6 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86016 Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved Jayvik Desai: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index e5c98c4..f7ff776 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -26,7 +26,7 @@ # Refer to EDS-Vol2-42.3.8. # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x311b" # EMMC TX DATA Delay 2 # Refer to EDS-Vol2-42.3.9. @@ -34,7 +34,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C282928" # EMMC RX CMD/DATA Delay 1 # Refer to EDS-Vol2-42.3.10. @@ -42,7 +42,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C19593B" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-42.3.12. @@ -53,13 +53,13 @@ # 11: Reserved # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10026" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-42.3.11. # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01313" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86016?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I276ebbfc29e3899cbacdc2353648017a3fa5b8a6 Gerrit-Change-Number: 86016 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/var/trulo: Remove touchscreen definitions
by Subrata Banik (Code Review) 21 Jan '25

21 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85893?usp=email ) Change subject: mb/google/var/trulo: Remove touchscreen definitions ...................................................................... mb/google/var/trulo: Remove touchscreen definitions Remove touchscreen definitions for Trulo since it doesn't have any. Additionally, disable unused I2C controller 5. BUG=none TEST=Build trulo firmware image Change-Id: If9d00ebf6165449d96f9337f313ee83262507ab4 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85893 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/trulo/gpio.c M src/mainboard/google/brya/variants/trulo/overridetree.cb 2 files changed, 9 insertions(+), 43 deletions(-) Approvals: Jayvik Desai: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Dtrain Hsu: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c index 8f0ad94..c813154 100644 --- a/src/mainboard/google/brya/variants/trulo/gpio.c +++ b/src/mainboard/google/brya/variants/trulo/gpio.c @@ -44,8 +44,8 @@ PAD_NC(GPP_A19, NONE), /* A20 : NC */ PAD_NC(GPP_A20, NONE), - /* A21 : DDPC_CTRLCLK ==> TCHSCR_REPORT_EN */ - PAD_CFG_GPO(GPP_A21, 0, DEEP), + /* A21 : NC */ + PAD_NC(GPP_A21, NONE), /* A22 : GPP_A22 ==> TPM_PIRQ# */ PAD_CFG_GPI(GPP_A22, NONE, DEEP), /* A23 : GPP_A23 ==> NC */ @@ -147,10 +147,10 @@ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* D14 : UART0_ISH_TX_DBG_RX */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), - /* D15 : GPP_D15 ==> SOC_TS_I2C_RST# */ - PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG), - /* D16 : ISH_UART0_CTS# ==> SOC_TS_I2C_INT# */ - PAD_CFG_GPI_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* D15 : NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : NC */ + PAD_NC(GPP_D16, NONE), /* D17 : NC */ PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* D18 : NC */ @@ -192,8 +192,8 @@ PAD_NC(GPP_E15, NONE), /* E16 : NC */ PAD_NC(GPP_E16, NONE), - /* E17 : GPP_E17 ==> SOC_TS_PWR_EN */ - PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG), + /* E17 : NC */ + PAD_NC(GPP_E17, NONE), /* E18 : NC */ PAD_NC(GPP_E18, NONE), /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ @@ -432,11 +432,6 @@ /* Fill romstage gpio configuration */ static const struct pad_config romstage_gpio_table[] = { - /* Enable touchscreen, hold in reset */ - /* E17 : GPP_E17 ==> SOC_TS_PWR_EN */ - PAD_CFG_GPO(GPP_E17, 1, DEEP), - /* D15 : GPP_D15 ==> SOC_TS_I2C_RST# */ - PAD_CFG_GPO(GPP_D15, 0, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index d135db0..5374666 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -122,7 +122,7 @@ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" register "serial_io_gspi_mode" = "{ @@ -148,7 +148,6 @@ #| | required to set up a BAR | #| | for TPM communication | #| I2C1 | Trackpad | - #| I2C5 | Touchscreen | #+-------------------+---------------------------+ register "common_soc_config" = "{ .i2c[0] = { @@ -170,15 +169,6 @@ .sda_hold = 7, } }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 158, - .scl_hcnt = 79, - .sda_hold = 7, - } - }, }" device domain 0 on @@ -470,25 +460,6 @@ device i2c 15 on end end end #I2C1 - device ref i2c5 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN9004"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.detect" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "20" - register "generic.reset_off_delay_ms" = "2" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)" - register "generic.enable_delay_ms" = "1" - register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)" - register "generic.stop_delay_ms" = "150" - register "generic.stop_off_delay_ms" = "2" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 10 on end - end - end #I2C5 device ref heci1 on end device ref emmc on probe STORAGE STORAGE_UNKNOWN -- To view, visit https://review.coreboot.org/c/coreboot/+/85893?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9d00ebf6165449d96f9337f313ee83262507ab4 Gerrit-Change-Number: 85893 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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