coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Correct USB port configuration for cameras
by Sean Rhodes (Code Review) 21 Jan '25

21 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86064?usp=email ) Change subject: mb/starlabs/starlite_adl: Correct USB port configuration for cameras ...................................................................... Patch Set 5: (1 comment) File src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c: https://review.coreboot.org/c/coreboot/+/86064/comment/4ba97d14_b5cfb002?us… : PS4, Line 60: Webcam > ```suggestion […] Fix applied. -- To view, visit https://review.coreboot.org/c/coreboot/+/86064?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2d8698394de69af53489e3a08c7fe7b4f2fbc07 Gerrit-Change-Number: 86064 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 21 Jan 2025 08:47:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Correct USB Port comments
by Sean Rhodes (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86063?usp=email ) Change subject: mb/starlabs/starlite_adl: Correct USB Port comments ...................................................................... Patch Set 2: (5 comments) Patchset: PS1: > might as well fix the ACPI entries as well 😊 Done File src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb: https://review.coreboot.org/c/coreboot/+/86063/comment/9aaf8eb0_66ca7639?us… : PS1, Line 75: Top > ```suggestion […] Fix applied. https://review.coreboot.org/c/coreboot/+/86063/comment/2444e13d_fa691c08?us… : PS1, Line 81: Top > ```suggestion […] Fix applied. https://review.coreboot.org/c/coreboot/+/86063/comment/31ca7002_882e7503?us… : PS1, Line 87: Bottom > ```suggestion […] Fix applied. https://review.coreboot.org/c/coreboot/+/86063/comment/1fd4beab_4fa4e10d?us… : PS1, Line 93: Bottom > ```suggestion […] Fix applied. -- To view, visit https://review.coreboot.org/c/coreboot/+/86063?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd46cd7e633f37e57213fffee4f70a7262894100 Gerrit-Change-Number: 86063 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 08:47:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85690?usp=email ) Change subject: soc/intel/meteorlake: Change the maximum C state to C8 ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Based on what you said on CB:84622, I think we need patches for Tiger, Sky, Jasper, Cannon, Panther and Elkhart too? -- To view, visit https://review.coreboot.org/c/coreboot/+/85690?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7de1220b0e26aa9dcca71e58caf17a0f168e7b24 Gerrit-Change-Number: 85690 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 08:46:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/alderlake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Matt DeVillier, Michał Żygowski, Nick Vaccaro, Paul Menzel, Subrata Banik. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84622?usp=email ) Change subject: soc/intel/alderlake: Change the maximum C state to C8 ...................................................................... Patch Set 7: (1 comment) Patchset: PS5: > looks like we can resolve this per Jeremy's reply? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb3e4d34361c8ac25ef144c0d1cda9f801ed0c54 Gerrit-Change-Number: 84622 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 21 Jan 2025 08:44:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Michał Żygowski, Nick Vaccaro, Paul Menzel, Sean Rhodes. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84622?usp=email ) Change subject: soc/intel/alderlake: Change the maximum C state to C8 ...................................................................... Patch Set 7: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84622/comment/29ce0e03_d2e2db23?us… : PS6, Line 9: Change the maximum C state allowed when S0ix isn't used to C8 : to solve the following error: : MWAIT C-state 0x33 not supported by HW (0x1010) > Without reading the diff, I would have thought you decrease it from C10 or so to C8. […] Done https://review.coreboot.org/c/coreboot/+/84622/comment/807cddce_3c5588b6?us… : PS6, Line 11: MWAIT C-state 0x33 not supported by HW (0x1010) > Also, maybe say, that the error is shown because of the substate: […] Google says the S is "Server Class" https://review.coreboot.org/c/coreboot/+/84622/comment/eab82019_fdedba4c?us… : PS6, Line 13: Tested on `starbook_adl` with Ubuntu 24.04 by booting, and : performing multiple S3 cycles. > Did you check with PowerTOP or turbostat if C8 was reached before and is now? It is reached File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/84622/comment/b710f0e2_26ba5737?us… : PS6, Line 107: C_STATE_C8 > Also, excuse my ignorance, why can’t C10 be used? The page *Package C-States* [1] does not say anyth […] AFAIK, it's just that you need S0ix enabled to reach C10 - oould be a specific reason, but it's not known to me! -- To view, visit https://review.coreboot.org/c/coreboot/+/84622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb3e4d34361c8ac25ef144c0d1cda9f801ed0c54 Gerrit-Change-Number: 84622 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 21 Jan 2025 08:44:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Change the maximum C state to C8
by Sean Rhodes (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Michał Żygowski, Nick Vaccaro, Sean Rhodes. Hello Dinesh Gehlot, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84622?usp=email to look at the new patch set (#7). Change subject: soc/intel/alderlake: Change the maximum C state to C8 ...................................................................... soc/intel/alderlake: Change the maximum C state to C8 Change the maximum C state allowed when S0ix isn't used to C8 from C7S to solve the following error: MWAIT C-state 0x33 not supported by HW (0x1010) Tested on `starbook_adl` with Ubuntu 24.04 by booting, and performing multiple S3 cycles. Change-Id: Idb3e4d34361c8ac25ef144c0d1cda9f801ed0c54 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/alderlake/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/84622/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/84622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb3e4d34361c8ac25ef144c0d1cda9f801ed0c54 Gerrit-Change-Number: 84622 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Remove superfluous preprocessor argument
by Sean Rhodes (Code Review) 21 Jan '25

21 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84621?usp=email ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Remove superfluous preprocessor argument ...................................................................... soc/intel/alderlake: Remove superfluous preprocessor argument The if statement is repeated so merge it into one block. Change-Id: I92f6d1b0a7fed4730f11e572b076f5dfdb91d96f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84621 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/alderlake/acpi/pcie.asl 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Jayvik Desai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/acpi/pcie.asl b/src/soc/intel/alderlake/acpi/pcie.asl index 414ced2..f37c168 100644 --- a/src/soc/intel/alderlake/acpi/pcie.asl +++ b/src/soc/intel/alderlake/acpi/pcie.asl @@ -310,9 +310,7 @@ { Name (_ADR, 0x00060000) } -#endif -#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) Device (PEG1) { Name (_ADR, 0x00060002) -- To view, visit https://review.coreboot.org/c/coreboot/+/84621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92f6d1b0a7fed4730f11e572b076f5dfdb91d96f Gerrit-Change-Number: 84621 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Remove superfluous preprocessor argument
by Sean Rhodes (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Nick Vaccaro, Paul Menzel, Subrata Banik. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84621?usp=email ) Change subject: soc/intel/alderlake: Remove superfluous preprocessor argument ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84621/comment/284e7bd7_573b4896?us… : PS7, Line 7: compiler > preprocessor? ;-) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92f6d1b0a7fed4730f11e572b076f5dfdb91d96f Gerrit-Change-Number: 84621 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 21 Jan 2025 08:38:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Remove superfluous preprocessor argument
by Sean Rhodes (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Nick Vaccaro, Sean Rhodes, Subrata Banik. Hello Dinesh Gehlot, Elyes Haouas, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84621?usp=email to look at the new patch set (#8). Change subject: soc/intel/alderlake: Remove superfluous preprocessor argument ...................................................................... soc/intel/alderlake: Remove superfluous preprocessor argument The if statement is repeated so merge it into one block. Change-Id: I92f6d1b0a7fed4730f11e572b076f5dfdb91d96f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/alderlake/acpi/pcie.asl 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/84621/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/84621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92f6d1b0a7fed4730f11e572b076f5dfdb91d96f Gerrit-Change-Number: 84621 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: CFR: Add min/max/step values and hex display flag for number options
by Angel Pons (Code Review) 21 Jan '25

21 Jan '25

Attention is currently required from: Filip Brozovic, Matt DeVillier, Sean Rhodes. Angel Pons has posted comments on this change by Filip Brozovic. ( https://review.coreboot.org/c/coreboot/+/86039?usp=email ) Change subject: CFR: Add min/max/step values and hex display flag for number options ...................................................................... Patch Set 3: (1 comment) File src/commonlib/include/commonlib/cfr.h: https://review.coreboot.org/c/coreboot/+/86039/comment/d30c9277_c94ffd82?us… : PS2, Line 139: uint32_t min; : uint32_t max; : uint32_t step; > Should we add a fixed version number to the header in coreboot, change `lb_cfr_numeric_option` to ad […] Yes, though the main idea of a CFR version number is to prevent parsing incompatible data structures, i.e. if the version number doesn't match, don't even try to parse anything. It's simpler than supporting multiple versions, and everything should be using the latest version anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/86039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e70f1430fb1911f1ad974832f8abfe76f928ac3 Gerrit-Change-Number: 86039 Gerrit-PatchSet: 3 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Comment-Date: Tue, 21 Jan 2025 08:27:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Filip Brozovic <fbrozovic(a)gmail.com>

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coreboot-gerrit January 2025