Attention is currently required from: Felix Singer, Nick Vaccaro.
Hello Felix Singer, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84348?usp=email
to look at the new patch set (#4).
Change subject: mb/google/volteer: Fix USB port definitions
......................................................................
mb/google/volteer: Fix USB port definitions
Commit bc8f5405b542 ("tgl mainboards: Move usb{2,3}_ports settings into
XHCI device scope") not only moved the USB port definitions under the
XHCI device reference, but also combined multiple register definitions.
In doing so, it broke the inheritance from the baseboard, since the
variant overridetree registers now replaced the entire usb2_ports/
usb3_ports structs, rather than replacing individual array elements
therein. This resulted in any USB ports inherited from the baseboard
and not overridden by the variant being non-function as they were
not included in the resulting combined devicetree.
To fix this, return to overriding individual array elements in the
usb2/3_ports structs.
TEST=build/boot google/drobit. Verify all USB ports present and
functional. Verify mainboard/static.c in built shows all ports.
Change-Id: I54921fa4ecf594a1ecbcfa7c45e5d745d4a95652
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/mainboard/google/volteer/variants/chronicler/overridetree.cb
M src/mainboard/google/volteer/variants/collis/overridetree.cb
M src/mainboard/google/volteer/variants/copano/overridetree.cb
M src/mainboard/google/volteer/variants/delbin/overridetree.cb
M src/mainboard/google/volteer/variants/drobit/overridetree.cb
M src/mainboard/google/volteer/variants/eldrid/overridetree.cb
M src/mainboard/google/volteer/variants/elemi/overridetree.cb
M src/mainboard/google/volteer/variants/halvor/overridetree.cb
M src/mainboard/google/volteer/variants/lindar/overridetree.cb
M src/mainboard/google/volteer/variants/malefor/overridetree.cb
M src/mainboard/google/volteer/variants/terrador/overridetree.cb
M src/mainboard/google/volteer/variants/todor/overridetree.cb
M src/mainboard/google/volteer/variants/voema/overridetree.cb
M src/mainboard/google/volteer/variants/volet/overridetree.cb
M src/mainboard/google/volteer/variants/voxel/overridetree.cb
16 files changed, 99 insertions(+), 143 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/84348/4
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Change subject: Makefile.mk: Add c-ccopts to LTO linking
......................................................................
Patch Set 5: Code-Review+2
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Cliff Huang has uploaded a new patch set (#122) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake-up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
4. PTL replaces DMI3 with SAF to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE guard check is added in northbridge.asl
5. include GPIO ASL that supports new pinctrl schema.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
A src/soc/intel/pantherlake/acpi/gpio.asl
A src/soc/intel/pantherlake/acpi/hda.asl
A src/soc/intel/pantherlake/acpi/pcie.asl
A src/soc/intel/pantherlake/acpi/serialio.asl
A src/soc/intel/pantherlake/acpi/southbridge.asl
A src/soc/intel/pantherlake/acpi/tcss.asl
A src/soc/intel/pantherlake/acpi/tcss_dma.asl
A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
A src/soc/intel/pantherlake/acpi/tcss_xhci.asl
A src/soc/intel/pantherlake/acpi/xhci.asl
12 files changed, 3,193 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/122
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Attention is currently required from: Matt DeVillier.
Peter Marheine has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84300?usp=email )
Change subject: ec/google/chromeec: Ensure pre-CR50 devices use "short" battery strings
......................................................................
Patch Set 2: Code-Review+1
(2 comments)
Patchset:
PS1:
> verified patch set 2 on google/lulu
Acknowledged
File src/ec/google/chromeec/acpi/battery.asl:
https://review.coreboot.org/c/coreboot/+/84300/comment/3b0db33f_5c845c11?us… :
PS1, Line 174: #if CONFIG(TPM_GOOGLE_CR50) || CONFIG(TPM_GOOGLE_TI50)
> agreed, can do that once we agree that these guards are the least-worst way to work around the probl […]
Done
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Change subject: soc/mt6366: Work around GCC LTO build
......................................................................
Patch Set 8:
(3 comments)
Patchset:
PS5:
> could you please report to gcc if it hasn't already been done?
+1, have you tried to isolate this and report it to GCC?
File src/soc/mediatek/mt8186/mt6366.c:
https://review.coreboot.org/c/coreboot/+/84208/comment/52e1961c_3b2b50d0?us… :
PS8, Line 10: #define NO_BUILDTIME_ASSERT
It looks like this is only a problem with very specific assert statements, so if we do want to hack around it (which generally doesn't sit that well with me, but I guess as long as it's only this one file that's okay (though somewhat odd)), shouldn't we rather add new macros that only disable it for that specific statement rather than for a whole file at a time (e.g. ASSERT_LTO_WORKAROUND(...))?
File src/vendorcode/amd/pi/00670F00/Porting.h:
https://review.coreboot.org/c/coreboot/+/84208/comment/c1db0ad4_0959c29b?us… :
PS8, Line 47: _PORTING_H_
Isn't this a header guard? I think you should leave it in place and just define NO_BUILDTIME_ASSERT in addition to it.
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Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim.
Cliff Huang has uploaded a new patch set (#121) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake-up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
4. PTL replaces DMI3 with SAF to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE guard check is added in northbridge.asl
5. include GPIO ASL that supports new pinctrl schema.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
A src/soc/intel/pantherlake/acpi/gpio.asl
A src/soc/intel/pantherlake/acpi/hda.asl
A src/soc/intel/pantherlake/acpi/pcie.asl
A src/soc/intel/pantherlake/acpi/serialio.asl
A src/soc/intel/pantherlake/acpi/southbridge.asl
A src/soc/intel/pantherlake/acpi/tcss.asl
A src/soc/intel/pantherlake/acpi/tcss_dma.asl
A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
A src/soc/intel/pantherlake/acpi/tcss_xhci.asl
A src/soc/intel/pantherlake/acpi/xhci.asl
12 files changed, 2,919 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/121
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Attention is currently required from: Felix Singer, Nick Vaccaro.
Hello Felix Singer, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84348?usp=email
to look at the new patch set (#3).
Change subject: mb/google/volteer: Fix USB port definitions
......................................................................
mb/google/volteer: Fix USB port definitions
Commit bc8f5405b542 ("tgl mainboards: Move usb{2,3}_ports settings into
XHCI device scope") not only moved the USB port definitions under the
XHCI device reference, but also combined multiple register definitions.
In doing so, it broke the inheritance from the baseboard, since the
variant overridetree registers now replaced the entire usb2_ports/
usb3_ports structs, rather than replacing individual array elements
therein. This resulted in any USB ports inherited from the baseboard
and not overridden by the variant being non-function as they were
not included in the resulting combined devicetree.
To fix this, return to overriding individual array elements in the
usb2/3_ports structs.
TEST=build/boot google/drobit. Verify all USB ports present and
functional. Verify mainboard/static.c in built shows all ports.
Change-Id: I54921fa4ecf594a1ecbcfa7c45e5d745d4a95652
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/mainboard/google/volteer/variants/chronicler/overridetree.cb
M src/mainboard/google/volteer/variants/collis/overridetree.cb
M src/mainboard/google/volteer/variants/copano/overridetree.cb
M src/mainboard/google/volteer/variants/delbin/overridetree.cb
M src/mainboard/google/volteer/variants/drobit/overridetree.cb
M src/mainboard/google/volteer/variants/eldrid/overridetree.cb
M src/mainboard/google/volteer/variants/elemi/overridetree.cb
M src/mainboard/google/volteer/variants/halvor/overridetree.cb
M src/mainboard/google/volteer/variants/lindar/overridetree.cb
M src/mainboard/google/volteer/variants/malefor/overridetree.cb
M src/mainboard/google/volteer/variants/terrador/overridetree.cb
M src/mainboard/google/volteer/variants/todor/overridetree.cb
M src/mainboard/google/volteer/variants/voema/overridetree.cb
M src/mainboard/google/volteer/variants/volet/overridetree.cb
M src/mainboard/google/volteer/variants/voxel/overridetree.cb
16 files changed, 101 insertions(+), 141 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/84348/3
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