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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake-up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
4. PTL replaces DMI3 with SAF to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE guard check is added in northbridge.asl
5. include GPIO ASL that supports new pinctrl schema.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
---
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
M src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
A src/soc/intel/pantherlake/acpi/gpio.asl
A src/soc/intel/pantherlake/acpi/hda.asl
A src/soc/intel/pantherlake/acpi/pcie.asl
A src/soc/intel/pantherlake/acpi/serialio.asl
A src/soc/intel/pantherlake/acpi/southbridge.asl
A src/soc/intel/pantherlake/acpi/tcss.asl
A src/soc/intel/pantherlake/acpi/tcss_dma.asl
A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
A src/soc/intel/pantherlake/acpi/tcss_xhci.asl
A src/soc/intel/pantherlake/acpi/xhci.asl
13 files changed, 2,923 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/118
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Cliff Huang has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84332?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
Patch Set 10:
(1 comment)
File src/soc/intel/pantherlake/chip.c:
https://review.coreboot.org/c/coreboot/+/84332/comment/5e47e9a2_8884badf?us… :
PS10, Line 21: #include <soc/p2sb.h>
need include soc/itss.h. Please see https://review.coreboot.org/c/coreboot/+/84183
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 117:
(12 comments)
File src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/9cb0e098_4c16f85d?us… :
PS104, Line 3: #define R_ICLK_PCR_CAMERA1 0x8000
: #define B_ICLK_PCR_FREQUENCY 0x1
: #define B_ICLK_PCR_REQUEST 0x2
:
> can you please point me at the EDS section to compare the bit-field? […]
I add TASK 16 for TODO itme in https://partnerissuetracker.corp.google.com/issues/357011633 for IMGCLKOUT[n] register descritpion.
File src/soc/intel/pantherlake/acpi/southbridge.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/2edf4be2_4c641a18?us… :
PS81, Line 11: #if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
> > I am not familiar with this but start looking into this. […]
will need new romstage patch and then change ASL.
File src/soc/intel/pantherlake/acpi/southbridge.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/846e2196_e1fbf1d1?us… :
PS104, Line 5: #include <soc/itss.h>
> please follow https://review.coreboot. […]
Done
File src/soc/intel/pantherlake/acpi/tcss.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/2db278c7_d5cb14cf?us… :
PS104, Line 396: /*OperationRegion (IOMR, SystemMemory, IOM_BASE_ADDR, 0x100)*/
> do we need this ?
Done
https://review.coreboot.org/c/coreboot/+/83772/comment/a86462f6_8f3f3333?us… :
PS104, Line 779: If (TRE2 == 1) {
> same
Done
https://review.coreboot.org/c/coreboot/+/83772/comment/b25cbdc9_a761f19c?us… :
PS104, Line 809: If (TRE3 == 1) {
> again same problem, this PTL code is so old that you need to rebase to apply latest code changes. […]
Done
File src/soc/intel/pantherlake/acpi/tcss.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/971807ff_11f2015c?us… :
PS105, Line 32: #define MCHBAR_TCSS_DEVEN_OFFSET 0x7090
> this offset needs to be changed to 0x73a8
Done
File src/soc/intel/pantherlake/acpi/tcss_dma.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/9fd96047_2e40a916?us… :
PS104, Line 13: 0xC8
> use smallcase `0xc8`
apply this to all TCSS ASL files
File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/0c17f18d_d5132ec7?us… :
PS23, Line 56: 0xBAC
> > Subrata, I browsed across the ASL files and check how the Field under OperationRegion are written, […]
okay. following this CL: https://review.coreboot.org/c/coreboot/+/78163/10/src/soc/intel/meteorlake/…
File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/64a05401_d0c21f8a?us… :
PS104, Line 22: Offset (0x5B),
> we don't need this line
Done
https://review.coreboot.org/c/coreboot/+/83772/comment/4776bb25_b482e060?us… :
PS104, Line 15: Offset(0x5A), /* SLSTS[7:0] - Slot Status Register */
: ABPX, 1, /* 0, Attention Button Pressed */
: , 2,
: PDCX, 1, /* 3, Presence Detect Changed */
: , 2,
: PDSX, 1, /* 6, Presence Detect State */
: , 1,
: Offset (0x5B),
: DLSC, 1, /* 8, Data Link Layer State Changed */
> why not this? […]
sure. based on the EDS register description, Slot Status (SLSTS) – Offset 5a is 16bit long.
https://review.coreboot.org/c/coreboot/+/83772/comment/86a04158_f94a410c?us… :
PS104, Line 24: Offset(0x60), /* RSTS - Root Status Register */
: Offset(0x62),
> why not […]
sure. this is preferred as 0x60 register is 32-bit wide.
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Change subject: tgl mainboards: Move usb{2,3}_ports settings into XHCI device scope
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
this breaks many USB ports for google/volteer as the baseboard port definitions are no longer inherited by the variant. Fix in CB:84348
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Change subject: [WIP] superio/ite: Add support for IT8625E
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> IT8625E is an Embedded Controller. It should run its own FW from a separate flash. […]
This makes sense, it's a modern chip with s0ix capability. Is there anything else under LDN0?
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Change subject: lib/jpeg: return string (not int) error messages
......................................................................
Patch Set 5:
(1 comment)
File src/lib/bootsplash.c:
https://review.coreboot.org/c/coreboot/+/84341/comment/eacc8d35_10fe43a5?us… :
PS5, Line 26: bootsplash.jpg
May look odd, but it actually carries information, i.e. that we are looking
for a file with that particular name. So I'd prefer to keep it.
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