Attention is currently required from: Kapil Porwal, Pranava Y N, Saurabh Mishra, Subrata Banik.
Jérémy Compostella has uploaded a new patch set (#11) to the change originally created by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84332?usp=email )
The following approvals got outdated and were removed:
Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I61930726ad0c765bfa1d72c5df893262be884834
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/acpi.c
A src/soc/intel/pantherlake/chip.c
M src/soc/intel/pantherlake/chip.h
M src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/cpu.c
A src/soc/intel/pantherlake/crashlog.c
A src/soc/intel/pantherlake/cse_telemetry.c
A src/soc/intel/pantherlake/elog.c
A src/soc/intel/pantherlake/finalize.c
A src/soc/intel/pantherlake/fsp_params.c
A src/soc/intel/pantherlake/gspi.c
A src/soc/intel/pantherlake/i2c.c
A src/soc/intel/pantherlake/include/soc/cpu.h
A src/soc/intel/pantherlake/include/soc/crashlog.h
A src/soc/intel/pantherlake/include/soc/dptf.h
M src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/irq.h
A src/soc/intel/pantherlake/include/soc/nvs.h
M src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pcie.h
M src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/ramstage.h
A src/soc/intel/pantherlake/include/soc/serialio.h
M src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/include/soc/tcss.h
A src/soc/intel/pantherlake/include/soc/usb.h
A src/soc/intel/pantherlake/lockdown.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/pcie_rp.c
A src/soc/intel/pantherlake/pmc.c
A src/soc/intel/pantherlake/pmutil.c
A src/soc/intel/pantherlake/retimer.c
A src/soc/intel/pantherlake/smihandler.c
A src/soc/intel/pantherlake/soundwire.c
A src/soc/intel/pantherlake/spi.c
A src/soc/intel/pantherlake/systemagent.c
A src/soc/intel/pantherlake/tcss.c
A src/soc/intel/pantherlake/uart.c
A src/soc/intel/pantherlake/xhci.c
41 files changed, 3,692 insertions(+), 110 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/84332/11
--
To view, visit https://review.coreboot.org/c/coreboot/+/84332?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I61930726ad0c765bfa1d72c5df893262be884834
Gerrit-Change-Number: 84332
Gerrit-PatchSet: 11
Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com>
Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com>
Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>
Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim.
Jérémy Compostella has uploaded a new patch set (#123) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake-up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
4. PTL replaces DMI3 with SAF to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE guard check is added in northbridge.asl
5. include GPIO ASL that supports new pinctrl schema.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
A src/soc/intel/pantherlake/acpi/gpio.asl
A src/soc/intel/pantherlake/acpi/hda.asl
A src/soc/intel/pantherlake/acpi/pcie.asl
A src/soc/intel/pantherlake/acpi/serialio.asl
A src/soc/intel/pantherlake/acpi/southbridge.asl
A src/soc/intel/pantherlake/acpi/tcss.asl
A src/soc/intel/pantherlake/acpi/tcss_dma.asl
A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
A src/soc/intel/pantherlake/acpi/tcss_xhci.asl
A src/soc/intel/pantherlake/acpi/xhci.asl
12 files changed, 3,192 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/123
--
To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Gerrit-Change-Number: 83772
Gerrit-PatchSet: 123
Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com>
Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com>
Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com>
Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com>
Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com>
Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com>
Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com>
Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>
Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com>
Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com>
Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>
Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>
Attention is currently required from: David Wu, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj.
Eric Lai has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/84339?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/google/nissa/var/riven: enable WIFI SAR
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/riven/variant.c:
https://review.coreboot.org/c/coreboot/+/84339/comment/12b2aff2_40d9c273?us… :
PS3, Line 10: if (fw_config_probe(FW_CONFIG(WIFI_TYPE, WIFI_CNVI)) &&
Suggest use fw_config_get_field to get the value and combine the value. Code should like this:
uint64_t type = fw_config_get_field(WIFI_TYPE)
uint64_t sar_id = fw_config_get_field(WIFI_SAR_ID)
static char filename[20];
snprintf(filename, sizeof(filename), "wifi_sar_%lld.hex", type << 3 | sar_id);
--
To view, visit https://review.coreboot.org/c/coreboot/+/84339?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I647d64a008991a7a20791b2c87ea6308af6bb82e
Gerrit-Change-Number: 84339
Gerrit-PatchSet: 3
Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Jayvik Desai <jayvik(a)google.com>
Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com>
Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com>
Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Comment-Date: Fri, 13 Sep 2024 02:26:12 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Attention is currently required from: Hung-Te Lin, Kiwi Liu, Paul Menzel, Yidi Lin, Yu-Ping Wu.
Mengqi Zhang has uploaded a new patch set (#14) to the change originally created by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )
Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400kHz
......................................................................
soc/mediatek/common: Reduce eMMC clock frequency to 400kHz
Mediatek SoCs start operating at eMMC clock around 2MHz right after
power-on. In JEDEC spec, eMMC clock needs under 400kHz.
When we need to set a clock output frequency, we actually set a
frequency division value. Originally, we set the source clock
frequency to 50MHz, the target frequency to 400KHz, and the frequency
division value to 125. However, the actual source clock frequency is
400MHz, so the final actual output is 400MHz/125=3.2MHz.
So we correct source clock frequency to 400MHz for eMMC output clock of 400KHz.
BUG=b:356578805
TEST=test boot ok; measure eMMC clock ok
Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Signed-off-by: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Signed-off-by: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/common/msdc.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84298/14
--
To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Gerrit-Change-Number: 84298
Gerrit-PatchSet: 14
Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Gerrit-Attention: Yidi Lin <yidilin(a)google.com>
Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>
Attention is currently required from: Hung-Te Lin, Kiwi Liu, Paul Menzel, Yidi Lin, Yu-Ping Wu.
Mengqi Zhang has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )
Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
......................................................................
Patch Set 13:
(1 comment)
File src/soc/mediatek/common/msdc.c:
https://review.coreboot.org/c/coreboot/+/84298/comment/94f3158f_cf3d16a8?us… :
PS9, Line 432: host->src_hz = 400 * 1000 * 1000;
> Mengqi, thank you for the explanation. Please also update the summary then. Maybe: […]
@yidilin@google.com
Yes and Yes.
@hungte@chromium.org
In previous mediatek-chromebook projects, MSDC source clock is 400MHz. And we have no plans to change it in future projects.
@paulepanter@mailbox.org
I will update this in commit message.
--
To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Gerrit-Change-Number: 84298
Gerrit-PatchSet: 13
Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Gerrit-Attention: Yidi Lin <yidilin(a)google.com>
Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Comment-Date: Fri, 13 Sep 2024 01:56:41 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org>
Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>
Comment-In-Reply-To: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Comment-In-Reply-To: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>
Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>
Attention is currently required from: Matt DeVillier, Nick Vaccaro.
Felix Singer has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84348?usp=email )
Change subject: mb/google/volteer: Fix USB port definitions
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
File src/mainboard/google/volteer/variants/copano/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/84348/comment/1fa1f6d4_4054b343?us… :
PS4, Line 269: USB
missing double quotes here
--
To view, visit https://review.coreboot.org/c/coreboot/+/84348?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I54921fa4ecf594a1ecbcfa7c45e5d745d4a95652
Gerrit-Change-Number: 84348
Gerrit-PatchSet: 4
Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Comment-Date: Fri, 13 Sep 2024 00:59:40 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Attention is currently required from: Hung-Te Lin, Mengqi Zhang, Paul Menzel, Yidi Lin, Yu-Ping Wu.
Kiwi Liu has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )
Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
......................................................................
Patch Set 13:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/f4b5f7af_3f66e14e?us… :
PS12, Line 11: When we need to set a clock output frequency, we actually set a frequency division value. Originally, we set the source clock frequency to 50MHz, the target frequency to 400KHz, and the frequency division value to 125. However, the actual source clock frequency is 400MHz, so the final actual output is 400MHz/125=3.2MHz. When we set the source clock frequency correctly, we can get the correct frequency division value, and then get the correct clock output.
> Please add a blank line between paragraphs, and re-flow it for 72 characters per line.
Done
--
To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Gerrit-Change-Number: 84298
Gerrit-PatchSet: 13
Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Gerrit-Attention: Yidi Lin <yidilin(a)google.com>
Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Comment-Date: Fri, 13 Sep 2024 00:33:10 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>
Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Yidi Lin, Yu-Ping Wu.
Hello Hung-Te Lin, Mengqi Zhang, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84298?usp=email
to look at the new patch set (#13).
Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
......................................................................
soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
Mediatek SoCs start operating at eMMC clock around 2 MHz right after
power-on. In JEDEC spec, eMMC clock needs under 400 kHz.
When we need to set a clock output frequency, we actually set a
frequency division value. Originally, we set the source clock
frequency to 50MHz, the target frequency to 400KHz, and the frequency
division value to 125. However, the actual source clock frequency is
400MHz, so the final actual output is 400MHz/125=3.2MHz. When we set
the source clock frequency correctly, we can get the correct frequency
division value, and then get the correct clock output.
BUG=b:356578805
TEST=test boot ok; measure eMMC clock ok
Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Signed-off-by: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Signed-off-by: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/common/msdc.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84298/13
--
To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Gerrit-Change-Number: 84298
Gerrit-PatchSet: 13
Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com>
Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com>
Gerrit-Attention: Yidi Lin <yidilin(a)google.com>
Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>