coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/mediatek/common: Reduce eMMC clock frequency to 400kHz
by Mengqi Zhang (Code Review) 13 Sep '24

13 Sep '24

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Paul Menzel, Yidi Lin. Mengqi Zhang has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email ) Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400kHz ...................................................................... Patch Set 14: (1 comment) File src/soc/mediatek/common/msdc.c: https://review.coreboot.org/c/coreboot/+/84298/comment/62b41a33_c679e4bf?us… : PS12, Line 353: msdc_debug("sclk: %d\n", sclk); > can you attach this log to the commit message ? (before and after the patch) before patch: [DEBUG] sclk: 390625 after patch: [DEBUG] sclk: 400000 I think this log is not the key point. The variable sclk represents the output frequency value calculated after the source clock frequency is divided. You can refer to the code in lines 338 and 339 for the specific calculation method. Let's take the before patch log as an example. hclk = 50MHz, clock = 400KHz, so div = 32, sclk = (50MHz / 4) / 32 = 390625Hz. What ultimately changes the output clock frequency is the div. You can refer to the code in lines 347 and 348. div = 32(before patch) div = 250(after patch) div related register description: MMC/SD card clock divider The register field controls clock frequency of serial clock on MMC/SD bus 12'h0: msdc_ck = msdc_src_ck * 1/2 others: msdc_ck = msdc_src_ck * 1/(4 * value) So after patch, output clock frequency is 400M / (4 * 250) = 400KHz -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 14 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 13 Sep 2024 06:42:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/common: Reduce eMMC clock frequency to 400kHz
by Yu-Ping Wu (Code Review) 13 Sep '24

13 Sep '24

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email ) Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400kHz ...................................................................... Patch Set 14: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84298/comment/b30fa093_19012e22?us… : PS14, Line 13: he frequency : division value to 125 > and get the division value 125. I don't think the origin code will give us the 125 value due to the division rounding error. ``` div = DIV_ROUND_UP(hclk, clock * 4) = DIV_ROUND_UP(50M / (400K * 4)) = DIV_ROUND_UP(31.25) = 32 ``` So the division value will be `div` * 4 = 128. -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 14 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 13 Sep 2024 06:39:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: mb/google/brox/var/lotso: Update cpu power limits
by Kun Liu (Code Review) 13 Sep '24

13 Sep '24

Attention is currently required from: Dengwu Yu, Jian Tong, Karthik Ramasubramanian, Subrata Banik, wen zhang. Kun Liu has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/84202?usp=email ) Change subject: mb/google/brox/var/lotso: Update cpu power limits ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84202?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928 Gerrit-Change-Number: 84202 Gerrit-PatchSet: 6 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 13 Sep 2024 06:29:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brox/var/lotso: Update cpu power limits
by Jian Tong (Code Review) 13 Sep '24

13 Sep '24

Attention is currently required from: Dengwu Yu, Karthik Ramasubramanian, Kun Liu, Subrata Banik, wen zhang. Hello Dengwu Yu, Karthik Ramasubramanian, Kun Liu, Subrata Banik, build bot (Jenkins), wen zhang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84202?usp=email to look at the new patch set (#6). Change subject: mb/google/brox/var/lotso: Update cpu power limits ...................................................................... mb/google/brox/var/lotso: Update cpu power limits When battery not persent, limit PL4 to 40. Base on: https://review.coreboot.org/c/coreboot/+/83752 AC+DC/DC: PL1=15W PL2=25W PL4=114W AC ONLY: PL1=15W PL2=25W PL4=40W BUG=b:355094551 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928 Signed-off-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/variants/lotso/Makefile.mk M src/mainboard/google/brox/variants/lotso/overridetree.cb A src/mainboard/google/brox/variants/lotso/ramstage.c 4 files changed, 47 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/84202/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84202?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928 Gerrit-Change-Number: 84202 Gerrit-PatchSet: 6 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 13 Sep '24

13 Sep '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84332?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 11: Code-Review+2 (1 comment) Patchset: PS11: > Putting +2 back after rebase, fixing some alphabetical minor issues and re-testing. Still good to go. as uploader, you can't give CR+2 of your own code. -- To view, visit https://review.coreboot.org/c/coreboot/+/84332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I61930726ad0c765bfa1d72c5df893262be884834 Gerrit-Change-Number: 84332 Gerrit-PatchSet: 11 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 13 Sep 2024 06:04:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Subrata Banik (Code Review) 13 Sep '24

13 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... Patch Set 123: (7 comments) File src/soc/intel/common/block/acpi/acpi/northbridge.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/1f01ead4_301804e7?us… : PS104, Line 284: Name (_UID, 1) > move this ASL to new CL: […] Acknowledged File src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/fbe5d2fb_40d45bae?us… : PS104, Line 3: #define R_ICLK_PCR_CAMERA1 0x8000 : #define B_ICLK_PCR_FREQUENCY 0x1 : #define B_ICLK_PCR_REQUEST 0x2 : > I add TASK 16 for TODO itme in https://partnerissuetracker.corp.google. […] Acknowledged File src/soc/intel/pantherlake/acpi/southbridge.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/6602a70e_23d59723?us… : PS81, Line 11: #if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB) > Subrata, I don't quite follow. The CL 84138 you mentioned contains changes removing soc/itss.h. I don't see any change for related marco guarding. if SOC_INTEL_COMMON_BLOCK_IOE_P2SB is default set to true for PTL SOC then what is the point of keeping `#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)` while adding `#include <soc/intel/common/acpi/ioe_pcr.asl>`? isn't the case is always true when PTL SOC selects SOC_INTEL_COMMON_BLOCK_IOE_P2SB unconditionally. Therefore, asked to remove this guarding File src/soc/intel/pantherlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/db993258_466278c2?us… : PS123, Line 216: Sleep (100) why we need static delay, this will impact the sleep_resume time KPI which is 500ms. Please file a bug to continue to have discussion. I don't think we need to issue static delay. At kernel space the delays should be like inherited delays. https://review.coreboot.org/c/coreboot/+/83772/comment/41ee22b4_c49e1656?us… : PS123, Line 218: If (CondRefOf (\_SB.PCI0.TXHC)) { : /* Invoke PCIe root ports wake event handler */ : \_SB.PCI0.TRP0.HPEV() : } : /* Check Root Port 0 for a Hot Plug Event if the port is enabled */ : If (((\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP0.HPSX)) { : If (\_SB.PCI0.TRP0.PDCX) { : /* Clear all status bits */ : \_SB.PCI0.TRP0.PDCX = 1 : \_SB.PCI0.TRP0.HPSX = 1 : /* : * Intercept Presence Detect Changed interrupt and make sure : * the L0s is disabled on empty slots. : */ : If (!\_SB.PCI0.TRP0.PDSX) { : /* : * The PCIe slot is empty, so disable L0s on hot unplug. : */ : \_SB.PCI0.TRP0.L0SE = 0 : } : /* Performs proper notification to the OS. */ : Notify (\_SB.PCI0.TRP0, 0) : } Else { : /* False event. Clear Hot-Plug status, then exit. */ : \_SB.PCI0.TRP0.HPSX = 1 : } : } please create helper function and call into w/o adding implementation for each RP here. File src/soc/intel/pantherlake/acpi/tcss_dma.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/7b9e46cc_b7d8e602?us… : PS104, Line 22: Offset (0xFF), : DMAD, 8 /* 31:24 DMA Active Delay */ > I add TASK 17 for TODO item in https://partnerissuetracker.corp.google. […] Acknowledged File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/c4e04463_23022f87?us… : PS123, Line 236: } please leave one space before -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 123 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 13 Sep 2024 06:02:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/common/block/acpi/exclude DMI fixed memory range if no DMI
by Subrata Banik (Code Review) 13 Sep '24

13 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84349?usp=email ) Change subject: soc/intel/common/block/acpi/exclude DMI fixed memory range if no DMI ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Please submit this CL without rebasing into the PTL recipe. -- To view, visit https://review.coreboot.org/c/coreboot/+/84349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d Gerrit-Change-Number: 84349 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 13 Sep 2024 05:52:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/common/block/acpi/exclude DMI fixed memory range if no DMI
by Subrata Banik (Code Review) 13 Sep '24

13 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84349?usp=email ) Change subject: soc/intel/common/block/acpi/exclude DMI fixed memory range if no DMI ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/acpi/acpi/northbridge.asl: https://review.coreboot.org/c/coreboot/+/84349/comment/1a9c64a6_6cda2baa?us… : PS3, Line 294: #if DMI_BASE_SIZE != 0 nit ``` #if DMI_BASE_SIZE ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d Gerrit-Change-Number: 84349 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 13 Sep 2024 05:51:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines
by Subrata Banik (Code Review) 13 Sep '24

13 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email ) Change subject: soc/intel/ptl: Add GPE1 defines ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/pantherlake/include/soc/gpe.h: https://review.coreboot.org/c/coreboot/+/84297/comment/7caf9a3c_9a191598?us… : PS4, Line 30: 146 > GPE1[0] starts from 0x80 (i.e. 128 dec) CNVI_BT_PME_B0 is bit 18, 128 + 18 = 146 (0x92), corresponding to _L92 events. I believe you are trying to put GPE1 after GPE0 standard register which ends at 127 and then considering GPE1[0] at 128 ? if yes, which we need to create virtual indexing when HW doesn't suggests something that obvious -- To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 Gerrit-Change-Number: 84297 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 13 Sep 2024 05:48:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/mt6366: Work around GCC LTO build
by Yu-Ping Wu (Code Review) 13 Sep '24

13 Sep '24

Attention is currently required from: Arthur Heymans, Cliff Huang, Elyes Haouas, Hung-Te Lin, Julius Werner, Jérémy Compostella, Lance Zhao, Tim Wawrzynczak, Yidi Lin. Yu-Ping Wu has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84208?usp=email ) Change subject: soc/mt6366: Work around GCC LTO build ...................................................................... Patch Set 8: (1 comment) File src/soc/mediatek/mt8186/mt6366.c: https://review.coreboot.org/c/coreboot/+/84208/comment/51c9b13b_cd18dea0?us… : PS8, Line 10: #define NO_BUILDTIME_ASSERT > It looks like this is only a problem with very specific assert statements, so if we do want to hack […] Code like ``` assert(vddq_uv >= 530000); ASSERT_LTO_WORKAROUND(vddq_uv <= 680000); ``` seems pretty weird and inconsistent, and the `ASSERT_LTO_WORKAROUND` solution doesn't seem robust. For now, only the 2nd call needs to be workarounded because there's some other code that sets the voltage to be greater than 680000 for a non-VDDQ regulator type. That means, future code changes (outside this file) are likely to break the 1st assert call with LTO, and when that happens we'll also need to change it to `ASSERT_LTO_WORKAROUND`. Therefore I'd prefer defining `NO_BUILDTIME_ASSERT` for the whole file, to avoid any potential future issues. -- To view, visit https://review.coreboot.org/c/coreboot/+/84208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e Gerrit-Change-Number: 84208 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 13 Sep 2024 04:45:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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coreboot-gerrit September 2024