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Change subject: soc/intel/ptl: Add GPE1 defines
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/pantherlake/include/soc/gpe.h:
https://review.coreboot.org/c/coreboot/+/84297/comment/0c2acd7b_3cd7308e?us… :
PS4, Line 30: 146
> looks great. will work on new patchset based on this tmr.
do you think we can decouple GPE1 changes from base PTL Cls ? i know there is still plan to enable GPE1 for fatcat. Hence, can we create a separate CL to push GPE1 changes slowly and focus on landing SOC/Fatcat CLs?
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Change subject: soc/mediatek/common: Correct src clk frq to 400 MHz for eMMMC clk of 400 kHz
......................................................................
Patch Set 15:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/76326f5f_129960dd?us… :
PS15, Line 7: Correct src clk frq to 400 MHz for eMMMC clk
: of 400 kHz
Looks like it's too long. How about `Correct eMMC src clk frequency to 400 MHz`?
File src/soc/mediatek/common/msdc.c:
https://review.coreboot.org/c/coreboot/+/84298/comment/bdac5a6a_2a7efa52?us… :
PS15, Line 432: 400 * 1000 * 1000
400 * MHz
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Change subject: soc/intel/ptl: Add GPE1 defines
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/pantherlake/include/soc/gpe.h:
https://review.coreboot.org/c/coreboot/+/84297/comment/c0a3cdb0_1cd74821?us… :
PS4, Line 30: 146
> > 18 is the bit 18 defined in GPE1_STS_31_0 (0x10) and GPE1_EN_31_0 (0x1C) registers. […]
looks great. will work on new patchset based on this tmr.
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Change subject: soc/intel/ptl: Add GPE1 defines
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/pantherlake/include/soc/gpe.h:
https://review.coreboot.org/c/coreboot/+/84297/comment/b7f02175_99588e26?us… :
PS4, Line 30: 146
> 18 is the bit 18 defined in GPE1_STS_31_0 (0x10) and GPE1_EN_31_0 (0x1C) registers.
>
> 0x80 is GPE0_REG_MAX x sizeof(uint32_t) x 8
i understand that it's bit number but not everyone has EDS access. Hence,
better would be
```
#define GPE_1_0 0
#define GPE_1_1 1
#define GPE_1_2 3
#define GEP1_OFFSET(blk, n) (GPE_START_NUM + (blk) * 32 + (n))
#define CNVI_BT_PME_B0 18
#define GPE1_CNVI_BT_PME_B0 GEP1_OFFSET(GPE_1_0, CNVI_BT_PME_B0)
```
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Change subject: mb/google/corsola: Make compatible with MT8186T by modifing skuid
......................................................................
Patch Set 2:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84342/comment/e33e06d6_120d1655?us… :
PS2, Line 7: Make compatible with MT8186T by modifing skuid
Distinguish MT8186T's SKU ID from MT8186
https://review.coreboot.org/c/coreboot/+/84342/comment/cf380fb8_c4b822c1?us… :
PS2, Line 9: skuid
SKU ID
https://review.coreboot.org/c/coreboot/+/84342/comment/b943c8d6_1f0e4569?us… :
PS2, Line 11: coreboot will pass skuid to kernel by 0x7ffffffe,
: so kernel can get the corresponded dts file for system boot.
change the SKU ID to 0x7ffffffe, so that the correct dts file will be selected by the payload.
File src/mainboard/google/corsola/boardid.c:
https://review.coreboot.org/c/coreboot/+/84342/comment/358ad979_dfe75eb8?us… :
PS2, Line 16: /* Define compatible sku_id value */
remove
https://review.coreboot.org/c/coreboot/+/84342/comment/23be00ba_ae9c647f?us… :
PS2, Line 17: CROS_SKU_COM
CROS_SKU_UNPROVISIONED_MT8186T
https://review.coreboot.org/c/coreboot/+/84342/comment/d0bcb5c5_e3364144?us… :
PS2, Line 132: BOARD_GOOGLE_STEELIX
The 0x7FFFFFFE value should be applied to all MT8186T boards, not just steelix. Please rewrite the code as:
```
if (cached_sku_code == CROS_SKU_UNPROVISIONED) {
printk(BIOS_WARNING, "Unprovisioned SKU code from EC: %s\n");
if (get_cpu_id() == MTK_CPU_ID_MT8186T) {
/* Distinguish MT8186T from MT8186 to select different device trees
in the payload. */
cached_sku_code = CROS_SKU_UNPROVISIONED_MT8186T;
} else if (CONFIG(BOARD_GOOGLE_STARYU_COMMON)) {
/* Reserve last 4 bits to report PANEL_ID */
cached_sku_code = 0x7FFFFFF0UL | panel_id();
}
} else if (cached_sku_code == CROS_SKU_UNKNOWN) {
printk(BIOS_WARNING, "Failed to get SKU code from EC\n");
cached_sku_code = (get_adc_index...
}
```
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Change subject: soc/intel/ptl: Add GPE1 defines
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/pantherlake/include/soc/gpe.h:
https://review.coreboot.org/c/coreboot/+/84297/comment/771f3f7d_c1040356?us… :
PS4, Line 30: 146
> with block number: […]
18 is the bit 18 defined in GPE1_STS_31_0 (0x10) and GPE1_EN_31_0 (0x1C) registers.
0x80 is GPE0_REG_MAX x sizeof(uint32_t) x 8
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Change subject: mb/google/brox/var/lotso: Update cpu power limits
......................................................................
Patch Set 6:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84202/comment/3f2f28d7_f667105f?us… :
PS6, Line 9: persent
present
https://review.coreboot.org/c/coreboot/+/84202/comment/cb4f15ef_f6876cd9?us… :
PS6, Line 9: limit PL4 to 40
… increase limit from 9 to 40
https://review.coreboot.org/c/coreboot/+/84202/comment/e3da9cdb_6c2035f8?us… :
PS6, Line 10: Base on: https://review.coreboot.org/c/coreboot/+/83752
Please summarize the change-set, and once it’s commit, also add the git commit hash and summary.
https://review.coreboot.org/c/coreboot/+/84202/comment/c62f776e_f78cfc32?us… :
PS6, Line 10: Base
Base*d*
https://review.coreboot.org/c/coreboot/+/84202/comment/fa8c0387_b1449b4c?us… :
PS6, Line 21:
What is the source for this data?
https://review.coreboot.org/c/coreboot/+/84202/comment/2af06586_26efc673?us… :
PS6, Line 23: TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Should runtime tests be done?
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Change subject: soc/intel/ptl: Add GPE1 defines
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/pantherlake/include/soc/gpe.h:
https://review.coreboot.org/c/coreboot/+/84297/comment/225a7b37_3eb8ee48?us… :
PS4, Line 30: 146
> with block number:
>
> #define GEP1_BIT(blk, n) (GPE_START_NUM + (blk) * 32 + (n))
>
> #define GPE1_CNVI_BT_PME_B0 GPE1_BIT(0, 18) // 146 -> _L92
> ...
if you are passing BLK and `N` then that has to be a further macro and not magic number `18`, otherwise no one will able to understand what does 18 mean here.
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