coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/brox/var/lotso: Update cpu power limits
by Paul Menzel (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Dengwu Yu, Jian Tong, Karthik Ramasubramanian, Subrata Banik, wen zhang. Paul Menzel has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/84202?usp=email ) Change subject: mb/google/brox/var/lotso: Update cpu power limits ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84202/comment/584848ac_3a74c4b3?us… : PS8, Line 10: form from -- To view, visit https://review.coreboot.org/c/coreboot/+/84202?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928 Gerrit-Change-Number: 84202 Gerrit-PatchSet: 8 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: wen zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 14 Sep 2024 06:15:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/corsola: Make compatible with MT8186T by modifing skuid
by Paul Menzel (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Hung-Te Lin, Knox Chiou, Yang Wu, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/84342?usp=email ) Change subject: mb/google/corsola: Make compatible with MT8186T by modifing skuid ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84342/comment/26147984_cc6cf993?us… : PS2, Line 10: corresponded corresponding https://review.coreboot.org/c/coreboot/+/84342/comment/0f683fa8_8940d4fe?us… : PS2, Line 15: 1.Pre-flashed 0x7fffffff and boot OS. : 2.Check OS boot normally by 0x7ffffffe. It’d be great if you put a space after the “bullet”. -- To view, visit https://review.coreboot.org/c/coreboot/+/84342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91306d3abd508e104851916882fb36a4fd302036 Gerrit-Change-Number: 84342 Gerrit-PatchSet: 2 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Knox Chiou <knoxchiou(a)google.com> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Knox Chiou <knoxchiou(a)google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 14 Sep 2024 06:14:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: ec/google/chromeec: Optimize battery string readout with caching
by Paul Menzel (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Forest Mittelberg, Peter Marheine, Subrata Banik. Paul Menzel has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84354?usp=email ) Change subject: ec/google/chromeec: Optimize battery string readout with caching ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Awesome work! -- To view, visit https://review.coreboot.org/c/coreboot/+/84354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ae5b5e618f20335f3d344811a97f1416df529e Gerrit-Change-Number: 84354 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sat, 14 Sep 2024 06:12:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines
by Paul Menzel (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N. Paul Menzel has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email ) Change subject: soc/intel/ptl: Add GPE1 defines ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/pantherlake/include/soc/pm.h: PS9: Split the reformatting out into a separate commit? -- To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 Gerrit-Change-Number: 84297 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 14 Sep 2024 06:10:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines
by Paul Menzel (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N. Paul Menzel has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email ) Change subject: soc/intel/ptl: Add GPE1 defines ...................................................................... Patch Set 9: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84297/comment/5908610b_9ffc0b15?us… : PS9, Line 7: Add GPE1 defines Maybe: > Define GPE1 macros https://review.coreboot.org/c/coreboot/+/84297/comment/761fda57_3c4a1b40?us… : PS9, Line 9: defines for GPE number for additional STD GPE0 in PTL : defines for GPE number for GPE1 : defines for GPE1 bits Please elaborate more before this is submitted. https://review.coreboot.org/c/coreboot/+/84297/comment/44490cb4_42ad4738?us… : PS9, Line 12: STD standard? https://review.coreboot.org/c/coreboot/+/84297/comment/b7466cd9_785a149e?us… : PS9, Line 12: NOTE: All GEP1 bits are STD GPE bits. Shouldn’t this then go into some common directory? -- To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 Gerrit-Change-Number: 84297 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 14 Sep 2024 06:09:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brask/var/bujia: Fix PSYS voltage setting
by Paul Menzel (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Shon Wang. Paul Menzel has posted comments on this change by Shon Wang. ( https://review.coreboot.org/c/coreboot/+/84333?usp=email ) Change subject: mb/google/brask/var/bujia: Fix PSYS voltage setting ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84333/comment/b587991a_81a15574?us… : PS3, Line 2: Shon Please use your full name. git config --global user.name "Your Name" https://review.coreboot.org/c/coreboot/+/84333/comment/3811c7c0_4afe7b21?us… : PS3, Line 15: TEST= cbmem -c | grep -i PsysPmax What is the output before and after? -- To view, visit https://review.coreboot.org/c/coreboot/+/84333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I848c92752b7a7b53f47c6296aad0bdda20e9b0bd Gerrit-Change-Number: 84333 Gerrit-PatchSet: 3 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sat, 14 Sep 2024 06:05:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Subrata Banik (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... Patch Set 125: (2 comments) File src/soc/intel/pantherlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/1b608292_2121174e?us… : PS123, Line 218: If (CondRefOf (\_SB.PCI0.TXHC)) { : /* Invoke PCIe root ports wake event handler */ : \_SB.PCI0.TRP0.HPEV() : } : /* Check Root Port 0 for a Hot Plug Event if the port is enabled */ : If (((\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP0.HPSX)) { : If (\_SB.PCI0.TRP0.PDCX) { : /* Clear all status bits */ : \_SB.PCI0.TRP0.PDCX = 1 : \_SB.PCI0.TRP0.HPSX = 1 : /* : * Intercept Presence Detect Changed interrupt and make sure : * the L0s is disabled on empty slots. : */ : If (!\_SB.PCI0.TRP0.PDSX) { : /* : * The PCIe slot is empty, so disable L0s on hot unplug. : */ : \_SB.PCI0.TRP0.L0SE = 0 : } : /* Performs proper notification to the OS. */ : Notify (\_SB.PCI0.TRP0, 0) : } Else { : /* False event. Clear Hot-Plug status, then exit. */ : \_SB.PCI0.TRP0.HPSX = 1 : } : } > defer GPE1 related changes from upstream. Acknowledged File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/7c2acf4e_fdc0f7b2?us… : PS104, Line 32: Offset (0x404), : LSOE, 1, : LNSE, 1, > I haven't got response yet, so it this as TODO in https://partnerissuetracker.corp.google. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 125 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 14 Sep 2024 05:53:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Subrata Banik (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Felix Held, Hannah Williams, Jamie Ryu. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 21: (1 comment) File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/84104/comment/806d5a23_678261a5?us… : PS11, Line 241: gpe0_mask > > @subratabanik@google.com I do not see use case for pmc_enable_std_gpe and pmc_disable_std_gpe. Where is this going be used? I think we just need to be able to disable all GPE0 and GPE1 bits and also clear all of them from Coreboot boot sequence. > > Can we just have pmc_disable_all_gpe and remove pmc_enable_std_gpe and pmc_disable_std_gpe? > > > isn't `pmc_enable_std_gpe` also part of the pmc_disable_all_gpe? (ideally that should be the flow). I agree with you that we are not calling pmc_enable_std_gpe/pmc_disable_std_gpe today in BIOS flow. But those are useful APIs to be used while debugging the issue. As per my suggestion above, I have extended the GPE0 PMC_B0/Hot_Plug/PCI_exp status to GPE1 events. @cliff.huang@intel.com, can you please implement soc_pmc_enable_std_gpe1 as suggested in my snippt ? we don't need to expose any weak function IMO. Also as discussed please move those code outside PTL initial patch train -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 21 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 14 Sep 2024 05:52:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hannah Williams <hannah.williams(a)intel.com> Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines
by Subrata Banik (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email ) Change subject: soc/intel/ptl: Add GPE1 defines ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/pantherlake/include/soc/pm.h: https://review.coreboot.org/c/coreboot/+/84297/comment/b9af8404_0e0793f0?us… : PS9, Line 133: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) we can drop this CPP. Anyway this is part of the SoC code and no harm if we define those bit-field without actually using it -- To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 Gerrit-Change-Number: 84297 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 14 Sep 2024 05:50:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Add RTS522A vdd ctrl by gpio
by Jian Tong (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Jian Tong, Kun Liu. Hello Kun Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84254?usp=email to look at the new patch set (#4). Change subject: mb/google/brox/var/lotso: Add RTS522A vdd ctrl by gpio ...................................................................... mb/google/brox/var/lotso: Add RTS522A vdd ctrl by gpio For next DVT build, hw add this power ctrl. BUG=b:359409425 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: Id256b3a94d3c8ed6f6832d63ecc74c2438c7d15a Signed-off-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brox/variants/lotso/gpio.c M src/mainboard/google/brox/variants/lotso/overridetree.cb 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/84254/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id256b3a94d3c8ed6f6832d63ecc74c2438c7d15a Gerrit-Change-Number: 84254 Gerrit-PatchSet: 4 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>

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coreboot-gerrit September 2024