Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84359?usp=email )
Change subject: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds
......................................................................
mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds
Selecting this option for non-ChromeOS builds significantly impacts
boot time negatively and breaks USB detection in edk2 payload.
TEST=build/boot google/maglia, verify boot time normal and USB
detection working as expected with multiple devices connected.
Change-Id: I53be4befe9a04bdaece21f40f93af6599baa7e0b
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/dedede/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/84359/1
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 46beebc..de53131 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -36,7 +36,6 @@
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_JASPERLAKE
- select SOC_INTEL_CRASHLOG
select SPI_FLASH_SMM
config BOARD_GOOGLE_AWASUKI
@@ -288,6 +287,7 @@
select GBB_FLAG_FORCE_DEV_BOOT_ALTFW
select GBB_FLAG_FORCE_MANUAL_RECOVERY
select HAS_RECOVERY_MRC_CACHE
+ select SOC_INTEL_CRASHLOG
select VBOOT_EARLY_EC_SYNC
select VBOOT_LID_SWITCH
--
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Gerrit-MessageType: newchange
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Gerrit-Change-Id: I53be4befe9a04bdaece21f40f93af6599baa7e0b
Gerrit-Change-Number: 84359
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84354?usp=email )
Change subject: ec/google/chromeec: Optimize battery string readout with caching
......................................................................
ec/google/chromeec: Optimize battery string readout with caching
This commit refactors the long battery string implementation to include
caching of the EC response for battery information (model, serial, and
manufacturer).
This optimization reduces resume time by approximately 63ms by
minimizing communication overhead between the AP and EC.
BUG=b:366338622
TEST=Verified on google/tivviks_ufs:
* Long battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled.
* Short battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n.
Change-Id: I32ae5b5e618f20335f3d344811a97f1416df529e
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84354
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Caveh Jalali <caveh(a)chromium.org>
---
M src/ec/google/chromeec/acpi/battery.asl
1 file changed, 58 insertions(+), 17 deletions(-)
Approvals:
Matt DeVillier: Looks good to me, approved
build bot (Jenkins): Verified
Caveh Jalali: Looks good to me, but someone else must approve
Paul Menzel: Looks good to me, but someone else must approve
diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl
index 30fe0fc..7d52088 100644
--- a/src/ec/google/chromeec/acpi/battery.asl
+++ b/src/ec/google/chromeec/acpi/battery.asl
@@ -60,6 +60,14 @@
#else
Name(BRSS, 0x0)
#endif
+// Cached battery string response indicator
+Name(BRI1, 0)
+Name(BRI2, 0)
+Name(BRI3, 0)
+// Cached battery string response data to save suspend-resume time
+Name(BRS1, Buffer(32) {0})
+Name(BRS2, Buffer(32) {0})
+Name(BRS3, Buffer(32) {0})
// Read extended battery strings from the selected battery.
// Arg0 = string index
//
@@ -82,11 +90,27 @@
Method(BRSX, 1, Serialized)
{
// It doesn't make sense to read the FIFO support indicator.
- if (Arg0 == 0)
+ if (Arg0 == 0 || Arg0 > 3)
{
Return ("")
}
+ // Check if response is already cached
+ If (Arg0 == 1 && BRI1 == 1)
+ {
+ Return (BRS1) /* battery model name */
+ }
+
+ If (Arg0 == 2 && BRI2 == 1)
+ {
+ Return (BRS2) /* battery serial number */
+ }
+
+ If (Arg0 == 3 && BRI3 == 1)
+ {
+ Return (BRS3) /* battery manufacturer's name */
+ }
+
If (BRSS == 0xff)
{
// Write 0 to BSRF to read back a support indicator; nonzero and
@@ -109,34 +133,51 @@
{
If (Arg0 == 1)
{
- Return (ToString (Concatenate (BMOD, 0)))
+ Local0 = ToString (Concatenate (BMOD, 0))
}
ElseIf (Arg0 == 2)
{
- Return (ToString (Concatenate (BSER, 0)))
+ Local0 = ToString (Concatenate (BSER, 0))
}
ElseIf (Arg0 == 3)
{
- Return (ToString (Concatenate (BMFG, 0)))
+ Local0 = ToString (Concatenate (BMFG, 0))
}
- Else
+ }
+ Else
+ {
+ // Select requested parameter to read
+ BSRF = Arg0
+
+ // Read to end of string, or up to a reasonable maximum length. Reads of
+ // BSRF consume bytes from the FIFO, so take care to read it only once
+ // per byte of data.
+ Local0 = ""
+ Local1 = BSRF
+ While (Local1 != 0 && SizeOf (Local0) < 32)
{
- Return ("")
+ Local0 = Concatenate (Local0, ToString (Local1))
+ Local1 = BSRF
}
}
- // Select requested parameter to read
- BSRF = Arg0
-
- // Read to end of string, or up to a reasonable maximum length. Reads of
- // BSRF consume bytes from the FIFO, so take care to read it only once
- // per byte of data.
- Local0 = ""
- Local1 = BSRF
- While (Local1 != 0 && SizeOf (Local0) < 32)
+ // Store the result in the cache
+ If (Arg0 == 1)
{
- Local0 = Concatenate (Local0, ToString (Local1))
- Local1 = BSRF
+ BRS1 = Local0
+ BRI1 = 1
+ }
+
+ If (Arg0 == 2)
+ {
+ BRS2 = Local0
+ BRI2 = 1
+ }
+
+ If (Arg0 == 3)
+ {
+ BRS3 = Local0
+ BRI3 = 1
}
Return (Local0)
--
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Gerrit-MessageType: merged
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Gerrit-Change-Id: I32ae5b5e618f20335f3d344811a97f1416df529e
Gerrit-Change-Number: 84354
Gerrit-PatchSet: 2
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org>
Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com>
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84352?usp=email )
Change subject: ec/google/chromeec: Add option to control reading long battery strings
......................................................................
ec/google/chromeec: Add option to control reading long battery strings
Older ChromeOS devices (pre-CR50) do not support reading long battery
strings. This commit adds a Kconfig option,
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING, to enable or disable this
feature.
This allows devices with TPM_GOOGLE (CR50/TI50) to read and display
long battery strings, while older devices like google/link, wolf, samus,
and chell will continue to display only the first 8 characters.
This change ensures compatibility with older devices while enabling
the display of complete battery information on newer platforms.
BUG=b:366338622
TEST=Verified on google/tivviks_ufs:
* Long battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled.
* Short battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n.
Change-Id: I7859809278b7e926bbe8beb1a0a9e12c7e6c220d
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84352
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Caveh Jalali <caveh(a)chromium.org>
---
M src/ec/google/chromeec/Kconfig
M src/ec/google/chromeec/acpi/battery.asl
2 files changed, 19 insertions(+), 1 deletion(-)
Approvals:
Caveh Jalali: Looks good to me, but someone else must approve
Matt DeVillier: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 7a8777f..f0418ff 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -152,6 +152,21 @@
help
Put the fan in auto mode at boot.
+config EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING
+ depends on TPM_GOOGLE
+ bool
+ default y
+ help
+ The Chrome EC currently supports two ways to read battery strings on
+ ACPI platforms:
+
+ * Read up to 8 bytes from EC shared memory BMFG, BMOD, ...
+ * Send a EC_CMD_BATTERY_GET_STATIC host command and read longer strings as a response.
+
+ Select this config to support readout of longer battery strings.
+
+ If unsure, say N.
+
endif # EC_GOOGLE_CHROMEEC
source "src/ec/google/chromeec/*/Kconfig"
diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl
index f5047cb..30fe0fc 100644
--- a/src/ec/google/chromeec/acpi/battery.asl
+++ b/src/ec/google/chromeec/acpi/battery.asl
@@ -54,9 +54,12 @@
Return (Local0)
}
+#if CONFIG(EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING)
// Cached flag for BSRF FIFO readout support from EC.
Name(BRSS, 0xff)
-
+#else
+Name(BRSS, 0x0)
+#endif
// Read extended battery strings from the selected battery.
// Arg0 = string index
//
--
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Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
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Attention is currently required from: Lean Sheng Tan, Martin L Roth, Matt DeVillier, Sean Rhodes.
Benjamin Doron has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84353?usp=email )
Change subject: payloads/edk2: Fix image alignment
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
A while back, this was broken on, I believe, MinPlatform. From memory, I didn't have the ability to investigate then, I only had in-memory debug logging. While we have different modules, in general, this has the potential to break things because page alignment enables the use of NX. So, has this been tested, and generally, with which features enabled?
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yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email )
Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
......................................................................
Patch Set 25:
(5 comments)
File src/soc/intel/snowridge/chip.c:
https://review.coreboot.org/c/coreboot/+/83321/comment/94086692_7b65b240?us… :
PS15, Line 323: res = new_resource(dev, IOINDEX_SUBTRACTIVE(index++, 0));
> domain non-legacy IO/MMIO ranges should be regarded as non-subtractive
The `IOINDEX_SUBTRACTIVE` are used in `pci_domain_read_resources()` in `src/device/pci_device.c`, should we follow with it?
https://review.coreboot.org/c/coreboot/+/83321/comment/b296be68_c3a0e46a?us… :
PS15, Line 418: }
> will the common pci codes do this again?
I searched the whole source tree, but there is no explicit setting of SERR. `src/device/pci_device.c` has a strange comment sayiny `v3 has command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR)`, but I don't know what it means.
https://review.coreboot.org/c/coreboot/+/83321/comment/59040e25_7f3e514c?us… :
PS15, Line 434:
> in SNR, are there both south cluster PCIe and north cluster PCIe? […]
SNR south cluster is on domain 0, with device function number >= 6.
File src/soc/intel/snowridge/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/83321/comment/71847f16_3eb7f080?us… :
PS15, Line 108: const FSP_SMBIOS_MEMORY_INFO *fsp_smbios_memory_info;
> to declare variable along with using will help the readability of the codes.
Done
File src/soc/intel/snowridge/systemagent.c:
https://review.coreboot.org/c/coreboot/+/83321/comment/fe23a08f_2bace14e?us… :
PS15, Line 32: void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt)
> The parameter in the declaration is resource_cnt, but all the SoC implementations renamed it to inde […]
Done
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Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick.
Hello Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83321?usp=email
to look at the new patch set (#26).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
......................................................................
soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
Tested-by: Vasiliy Khoruzhick <vasilykh(a)arista.com>
---
M 3rdparty/fsp
A src/soc/intel/snowridge/Kconfig
A src/soc/intel/snowridge/Makefile.mk
A src/soc/intel/snowridge/acpi.c
A src/soc/intel/snowridge/acpi/hostbridges.asl
A src/soc/intel/snowridge/acpi/ith.asl
A src/soc/intel/snowridge/acpi/lpc.asl
A src/soc/intel/snowridge/acpi/pch_irqs.asl
A src/soc/intel/snowridge/acpi/pci_irqs.asl
A src/soc/intel/snowridge/acpi/pcie.asl
A src/soc/intel/snowridge/acpi/pcie_port.asl
A src/soc/intel/snowridge/acpi/pmc.asl
A src/soc/intel/snowridge/acpi/sata0.asl
A src/soc/intel/snowridge/acpi/sata2.asl
A src/soc/intel/snowridge/acpi/smbus.asl
A src/soc/intel/snowridge/acpi/southcluster.asl
A src/soc/intel/snowridge/acpi/uncore.asl
A src/soc/intel/snowridge/bootblock/bootblock.c
A src/soc/intel/snowridge/bootblock/bootblock.h
A src/soc/intel/snowridge/bootblock/early_uart_init.c
A src/soc/intel/snowridge/chip.c
A src/soc/intel/snowridge/chip.h
A src/soc/intel/snowridge/common/fsp_hob.c
A src/soc/intel/snowridge/common/fsp_hob.h
A src/soc/intel/snowridge/common/gpio.c
A src/soc/intel/snowridge/common/hob_display.c
A src/soc/intel/snowridge/common/kti_cache.c
A src/soc/intel/snowridge/common/kti_cache.h
A src/soc/intel/snowridge/common/pmclib.c
A src/soc/intel/snowridge/common/reset.c
A src/soc/intel/snowridge/common/spi.c
A src/soc/intel/snowridge/common/systemagent_early.c
A src/soc/intel/snowridge/common/uart8250mem.c
A src/soc/intel/snowridge/common/uart8250mem.h
A src/soc/intel/snowridge/common/upd_display.c
A src/soc/intel/snowridge/cpu.c
A src/soc/intel/snowridge/finalize.c
A src/soc/intel/snowridge/heci.c
A src/soc/intel/snowridge/hob_iiouds.h
A src/soc/intel/snowridge/hqm.c
A src/soc/intel/snowridge/include/soc/acpi.h
A src/soc/intel/snowridge/include/soc/cpu.h
A src/soc/intel/snowridge/include/soc/gpio.h
A src/soc/intel/snowridge/include/soc/gpio_defs.h
A src/soc/intel/snowridge/include/soc/gpio_snr.h
A src/soc/intel/snowridge/include/soc/iomap.h
A src/soc/intel/snowridge/include/soc/irq.h
A src/soc/intel/snowridge/include/soc/itss.h
A src/soc/intel/snowridge/include/soc/lpc.h
A src/soc/intel/snowridge/include/soc/msr.h
A src/soc/intel/snowridge/include/soc/nvs.h
A src/soc/intel/snowridge/include/soc/p2sb.h
A src/soc/intel/snowridge/include/soc/pci_devs.h
A src/soc/intel/snowridge/include/soc/pci_ids.h
A src/soc/intel/snowridge/include/soc/pcr_gpmr.h
A src/soc/intel/snowridge/include/soc/pcr_ids.h
A src/soc/intel/snowridge/include/soc/pm.h
A src/soc/intel/snowridge/include/soc/pmc.h
A src/soc/intel/snowridge/include/soc/sata.h
A src/soc/intel/snowridge/include/soc/smbus.h
A src/soc/intel/snowridge/include/soc/soc_chip.h
A src/soc/intel/snowridge/include/soc/systemagent.h
A src/soc/intel/snowridge/lockdown.c
A src/soc/intel/snowridge/lpc.c
A src/soc/intel/snowridge/memmap.c
A src/soc/intel/snowridge/nis.c
A src/soc/intel/snowridge/qat.c
A src/soc/intel/snowridge/ramstage.h
A src/soc/intel/snowridge/romstage/gpio_snr.c
A src/soc/intel/snowridge/romstage/romstage.c
A src/soc/intel/snowridge/sata.c
A src/soc/intel/snowridge/smihandler.c
A src/soc/intel/snowridge/sriov.c
A src/soc/intel/snowridge/systemagent.c
74 files changed, 5,862 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/26
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Change subject: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
......................................................................
mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
A src/mainboard/intel/frost_creek/Kconfig
A src/mainboard/intel/frost_creek/Kconfig.name
A src/mainboard/intel/frost_creek/Makefile.mk
A src/mainboard/intel/frost_creek/acpi/platform.asl
A src/mainboard/intel/frost_creek/acpi_tables.c
A src/mainboard/intel/frost_creek/board.fmd
A src/mainboard/intel/frost_creek/board_id.c
A src/mainboard/intel/frost_creek/board_id.h
A src/mainboard/intel/frost_creek/board_info.txt
A src/mainboard/intel/frost_creek/devicetree.cb
A src/mainboard/intel/frost_creek/dsdt.asl
A src/mainboard/intel/frost_creek/gpio.inc
A src/mainboard/intel/frost_creek/ramstage.c
A src/mainboard/intel/frost_creek/ramstage.h
A src/mainboard/intel/frost_creek/romstage.c
A src/mainboard/intel/frost_creek/romstage.h
16 files changed, 669 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/83322/28
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Angel Pons has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/80333?usp=email )
Change subject: device/azalia: Rework azalia verb tables
......................................................................
Patch Set 22:
(1 comment)
Patchset:
PS21:
> There is probably some clever way to automatic at least some of this work. […]
I've done some serious refactoring in Sandy/Ivy Bridge native raminit in the past. Because RAM initialisation depends on so many factors (mainboard, CPU, DIMMs, temperature...), boot-testing will never catch all possible regressions. If I had done my changes in one go (like this commit), no one would be able to review it.
Instead of that, I decided to take on a different route: https://review.coreboot.org/q/hashtag:"iosav-api" is what I ended up doing. It's a bit hard to follow, but my thought process is:
```
1. coreboot has reproducible builds, in the form of `make BUILD_TIMELESS=1`
2. changes to source code do not always result in changes to machine code
3. introducing and eliminating macros (if done right) will be reproducible
4. reviewing a reproducible change is easier (coreboot.rom does not change)
5. it is nearly impossible to review complex bulk changes to magic numbers
6. wrapping/unwrapping magic values using macros is typically reproducible
7. changing how these magic values are used is *NOT* reproducible, sadly
8. updating a macro definition is easier to review than bulk magic changes
9. using more commits has some overhead, but eases reviewing each commit
```
The result is a patch train that does the following (more or less):
```
1. wrap magic numbers (e.g. HDA verbs) in scaffolding macros, reproducible
2. update the implementation and the scaffolding macros, *NOT* reproducible
3. get rid of all the temporary scaffolding macros from code, reproducible
```
This way, non-reproducible changes can be pretty short (so easier to review), and huge changes are reproducible (knowing that the coreboot.rom is identical allows focusing on other aspects).
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Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/corsola/boardid.c:
https://review.coreboot.org/c/coreboot/+/84342/comment/d3fa99a0_0f0e1883?us… :
PS2, Line 132: BOARD_GOOGLE_STEELIX
> Actually, Squirtle only has one DTS file, so the SKU ID 0xfffffffe would also work for it. […]
We will update `0xfffffffe` to the compatible strings and also config.star , like we do for Steelix's [config.star](https://chrome-internal-review.googlesource.com/c/chromeos/pro…, for Voltorb and Squirtle.
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Attention is currently required from: Hung-Te Lin, Knox Chiou, Paul Menzel, Xinxiong Xu, Yang Wu, Yidi Lin.
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
......................................................................
mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
For MT8186, factory pre-flashed 0x7fffffff as default SKUD ID and kernel
can load the corresponding dts file. To make MT8186T functional on
0x7fffffff devices, change the SKU ID to 0x7ffffffe, so that the correct
dts file will be selected by the payload.
BUG=b:365730137
TEST=1. Pre-flashed 0x7fffffff and boot OS.
2. Check OS boot normally by 0x7ffffffe.
BRANCH=corsola
Change-Id: I91306d3abd508e104851916882fb36a4fd302036
Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/corsola/boardid.c
1 file changed, 11 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/84342/4
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