coreboot-gerrit September 2024

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[M] Change in coreboot[main]: util/amdfwtool: Add binaries
by Maximilian Brune (Code Review) 15 Sep '24

15 Sep '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84373?usp=email ) Change subject: util/amdfwtool: Add binaries ...................................................................... util/amdfwtool: Add binaries Change-Id: I78d7a9dba71de557e0a9a885d8561eea1f4191ef Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 3 files changed, 130 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/84373/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 7f17b71..22a641e 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -171,13 +171,13 @@ .generate_manifest = true }, { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 | PSP_LVL2_AB, - .skip_hashing = true }, + { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 | PSP_LVL2_AB, .skip_hashing = true }, + { .type = AMD_FW_PSP_TEEIPKEY, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB, .skip_hashing = true }, { .type = AMD_FW_ABL_PUBKEY, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_BOOT_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, @@ -187,6 +187,7 @@ { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_HW_IPCFG, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_HW_IPCFG, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_HW_IPCFG, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, @@ -226,7 +227,8 @@ { .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_MSMU, .subprog=0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_MSMU, .subprog=1, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_MPIO, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH | PSP_LVL2_AB }, @@ -235,6 +237,7 @@ .generate_manifest = true }, { .type = AMD_RIB, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_RIB, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_RIB, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_MPDMA_TF, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, { .type = AMD_FW_GMI3_PHY, .level = PSP_BOTH | PSP_BOTH_AB }, @@ -242,18 +245,32 @@ { .type = AMD_FW_AMF_SRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_AMF_DRAM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_AMF_DRAM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_MFD_MPM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_MFD_MPM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_FCFG_TABLE, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_AMF_WLAN, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_AMF_WLAN, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_AMF_WLAN, .inst = 2, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_AMF_WLAN, .inst = 3, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_AMF_MFD, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, - { .type = AMD_FW_MPCCX, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_MPCCX, .subprog=0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_MPCCX, .subprog=1, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_LSDMA, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_C20_MP, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_MINIMSMU, .inst = 0, .level = PSP_BOTH | PSP_LVL2_AB }, - { .type = AMD_FW_MINIMSMU, .inst = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_MINIMSMU, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_MINIMSMU, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_GFXIMU_0, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_GFXIMU_0, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_GFXIMU_1, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_GFXIMU_1, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_GFXIMU_2, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_SRAM_FW_EXT, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_UMSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_S3IMG, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_USBDP, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_USBSS, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_USB4, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_INVALID }, }; @@ -302,7 +319,8 @@ { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, { .type = AMD_BIOS_BIN, .reset = 1, .copy = 1, .zlib = 1, .inst = 0, .level = BDT_BOTH }, - { .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 }, + { .type = AMD_BIOS_APOB_NV, .level = BDT_BOTH }, + { .type = AMD_BIOS_NV_ST, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 0, .level = BDT_BOTH }, @@ -351,14 +369,14 @@ { .type = AMD_BIOS_PMUD, .inst = 12, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 13, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 13, .subpr = 1, .level = BDT_BOTH }, - { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 }, + { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 }, { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 }, { .type = AMD_BIOS_UCODE, .inst = 3, .level = BDT_LVL2 }, { .type = AMD_BIOS_UCODE, .inst = 4, .level = BDT_LVL2 }, { .type = AMD_BIOS_UCODE, .inst = 5, .level = BDT_LVL2 }, { .type = AMD_BIOS_UCODE, .inst = 6, .level = BDT_LVL2 }, - { .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 }, + { .type = AMD_BIOS_MP2_CFG, .level = BDT_BOTH }, { .type = AMD_BIOS_PSP_SHARED_MEM, .inst = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_INVALID }, }; diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index f87fbf5..de4a075 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -46,6 +46,7 @@ AMD_FW_PSP_TRUSTLETKEY = 0x0d, AMD_FW_PSP_SMU_FIRMWARE2 = 0x12, AMD_DEBUG_UNLOCK = 0x13, + AMD_FW_PSP_TEEIPKEY = 0x15, AMD_BOOT_DRIVER = 0x1b, AMD_SOC_DRIVER = 0x1c, AMD_DEBUG_DRIVER = 0x1d, @@ -97,6 +98,7 @@ AMD_RIB = 0x76, AMD_FW_AMF_SRAM = 0x85, AMD_FW_AMF_DRAM = 0x86, + AMD_FW_MFD_MPM = 0x87, AMD_FW_AMF_WLAN = 0x88, AMD_FW_AMF_MFD = 0x89, AMD_FW_MPDMA_TF = 0x8c, @@ -108,8 +110,15 @@ AMD_FW_C20_MP = 0x95, AMD_FW_FCFG_TABLE = 0x98, AMD_FW_MINIMSMU = 0x9a, + AMD_FW_GFXIMU_0 = 0x9b, + AMD_FW_GFXIMU_1 = 0x9c, + AMD_FW_GFXIMU_2 = 0x9d, AMD_FW_SRAM_FW_EXT = 0x9d, AMD_FW_UMSMU = 0xa2, + AMD_FW_S3IMG = 0xa0, + AMD_FW_USBDP = 0xa4, + AMD_FW_USBSS = 0xa5, + AMD_FW_USB4 = 0xa6, AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ AMD_FW_GEC, AMD_FW_XHCI, @@ -131,6 +140,7 @@ AMD_BIOS_EARLY_VGA = 0x69, AMD_BIOS_MP2_CFG = 0x6a, AMD_BIOS_PSP_SHARED_MEM = 0x6b, + AMD_BIOS_NV_ST = 0x6d, AMD_BIOS_L2_PTR = 0x70, AMD_BIOS_INVALID, AMD_BIOS_SKIP diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 64ec4d7..0fda1af 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -206,6 +206,9 @@ } else if (strcmp(fw_name, "PSP_HW_IPCFG_FILE_SUB1") == 0) { fw_type = AMD_HW_IPCFG; subprog = 1; + } else if (strcmp(fw_name, "PSP_HW_IPCFG_FILE_SUB2") == 0) { + fw_type = AMD_HW_IPCFG; + subprog = 2; } else if (strcmp(fw_name, "PSP_SMUFW1_SUB1_FILE") == 0) { fw_type = AMD_FW_PSP_SMU_FIRMWARE; subprog = 1; @@ -218,6 +221,9 @@ } else if (strcmp(fw_name, "PSP_SMUFW2_SUB1_FILE") == 0) { fw_type = AMD_FW_PSP_SMU_FIRMWARE2; subprog = 1; + } else if (strcmp(fw_name, "PSP_TEEIPKEY_FILE") == 0) { + fw_type = AMD_FW_PSP_TEEIPKEY; + subprog = 0; } else if (strcmp(fw_name, "PSP_SMUFW2_SUB2_FILE") == 0) { fw_type = AMD_FW_PSP_SMU_FIRMWARE2; subprog = 2; @@ -295,6 +301,9 @@ } else if (strcmp(fw_name, "PSP_IKEK_FILE") == 0) { fw_type = AMD_WRAPPED_IKEK; subprog = 0; + } else if (strcmp(fw_name, "PSP_IKEK_FILE_UNSECURE") == 0) { + fw_type = AMD_WRAPPED_IKEK; + subprog = 0; } else if (strcmp(fw_name, "PSP_SECG0_FILE") == 0) { fw_type = AMD_SEC_GASKET; subprog = 0; @@ -339,6 +348,14 @@ fw_type = AMD_FW_AMF_DRAM; subprog = 0; instance = 1; + } else if (strcmp(fw_name, "MFD_MPM_TEE_INS0") == 0) { + fw_type = AMD_FW_MFD_MPM; + subprog = 0; + instance = 0; + } else if (strcmp(fw_name, "MFD_MPM_TEE_INS1") == 0) { + fw_type = AMD_FW_MFD_MPM; + subprog = 0; + instance = 1; } else if (strcmp(fw_name, "AMF_WLAN_FILE_INS0") == 0) { fw_type = AMD_FW_AMF_WLAN; subprog = 0; @@ -347,12 +364,23 @@ fw_type = AMD_FW_AMF_WLAN; subprog = 0; instance = 1; + } else if (strcmp(fw_name, "AMF_WLAN_FILE_INS2") == 0) { + fw_type = AMD_FW_AMF_WLAN; + subprog = 0; + instance = 2; + } else if (strcmp(fw_name, "AMF_WLAN_FILE_INS3") == 0) { + fw_type = AMD_FW_AMF_WLAN; + subprog = 0; + instance = 3; } else if (strcmp(fw_name, "AMF_MFD_FILE") == 0) { fw_type = AMD_FW_AMF_MFD; subprog = 0; } else if (strcmp(fw_name, "MPCCX_FILE") == 0) { fw_type = AMD_FW_MPCCX; subprog = 0; + } else if (strcmp(fw_name, "MPCCX_FILE_SUB1_FILE") == 0) { + fw_type = AMD_FW_MPCCX; + subprog = 1; } else if (strcmp(fw_name, "LSDMA_FILE") == 0) { fw_type = AMD_FW_LSDMA; subprog = 0; @@ -360,6 +388,30 @@ fw_type = AMD_FW_MINIMSMU; instance = 0; subprog = 0; + } else if (strcmp(fw_name, "MINIMSMU_FILE_SUB1_FILE") == 0) { + fw_type = AMD_FW_MINIMSMU; + instance = 0; + subprog = 1; + } else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_0") == 0) { + fw_type = AMD_FW_GFXIMU_0; + instance = 0; + subprog = 0; + } else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_01") == 0) { + fw_type = AMD_FW_GFXIMU_0; + instance = 0; + subprog = 1; + } else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_1") == 0) { + fw_type = AMD_FW_GFXIMU_1; + instance = 0; + subprog = 0; + } else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_11") == 0) { + fw_type = AMD_FW_GFXIMU_1; + instance = 0; + subprog = 1; + } else if (strcmp(fw_name, "PSP_GFX_IMMU_FILE_2") == 0) { + fw_type = AMD_FW_GFXIMU_2; + instance = 0; + subprog = 0; } else if (strcmp(fw_name, "MINIMSMU_FILE_INS1") == 0) { fw_type = AMD_FW_MINIMSMU; instance = 1; @@ -414,6 +466,9 @@ } else if (strcmp(fw_name, "MSMU_FILE") == 0) { fw_type = AMD_FW_MSMU; subprog = 0; + } else if (strcmp(fw_name, "MSMU_FILE_SUB1_FILE") == 0) { + fw_type = AMD_FW_MSMU; + subprog = 1; } else if (strcmp(fw_name, "DMCUB_FILE") == 0) { fw_type = AMD_FW_DMCUB; subprog = 0; @@ -445,6 +500,18 @@ } else if (strcmp(fw_name, "UMSMU_FILE") == 0) { fw_type = AMD_FW_UMSMU; subprog = 0; + } else if (strcmp(fw_name, "PSP_S3_IMG") == 0) { + fw_type = AMD_FW_S3IMG; + subprog = 0; + } else if (strcmp(fw_name, "PSP_USB_DP") == 0) { + fw_type = AMD_FW_USBDP; + subprog = 0; + } else if (strcmp(fw_name, "PSP_USB_SS") == 0) { + fw_type = AMD_FW_USBSS; + subprog = 0; + } else if (strcmp(fw_name, "PSP_USB_4") == 0) { + fw_type = AMD_FW_USB4; + subprog = 0; } else if (strcmp(fw_name, "PSP_OEM_ABL_KEY_FILE") == 0) { fw_type = AMD_FW_ABL_PUBKEY; subprog = 0; @@ -469,6 +536,9 @@ } else if (strcmp(fw_name, "PSP_RIB_FILE_SUB1") == 0) { fw_type = AMD_RIB; subprog = 1; + } else if (strcmp(fw_name, "PSP_RIB_FILE_SUB2") == 0) { + fw_type = AMD_RIB; + subprog = 2; } else if (strcmp(fw_name, "FEATURE_TABLE_FILE") == 0) { fw_type = AMD_FW_FCFG_TABLE; subprog = 0; @@ -553,10 +623,32 @@ } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { if (cb_config->load_mp2_fw) { fw_type = AMD_BIOS_MP2_CFG; + } else if (strcmp(fw_name, "PSP_BDT_UCODE_INS0") == 0) { + fw_type = AMD_BIOS_UCODE; subprog = 0; + instance = 0; + } else if (strcmp(fw_name, "PSP_BDT_UCODE_INS1") == 0) { + fw_type = AMD_BIOS_UCODE; + subprog = 0; + instance = 1; } else { fw_type = AMD_BIOS_SKIP; } + } else if (strcmp(fw_name, "PSP_BDT_APCB_BK_INS0") == 0) { + fw_type = AMD_BIOS_APCB_BK; + subprog = 0; + instance = 0; + } else if (strcmp(fw_name, "PSP_BDT_APCB_BK_INS8") == 0) { + fw_type = AMD_BIOS_APCB_BK; + subprog = 0; + instance = 8; + } else if (strcmp(fw_name, "PSP_MP2CFG_FILE") == 0) { + fw_type = AMD_BIOS_MP2_CFG; + subprog = 0; + } else if (strcmp(fw_name, "PSP_BDT_BIOS_NV_ST") == 0) { + fw_type = AMD_BIOS_NV_ST; + subprog = 0; + instance = 0; } else { fw_type = AMD_BIOS_INVALID; } -- To view, visit https://review.coreboot.org/c/coreboot/+/84373?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78d7a9dba71de557e0a9a885d8561eea1f4191ef Gerrit-Change-Number: 84373 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: mb/google/brya/var/trulo: Update ISH GPIO config for tablet mode switch
by Varun Upadhyay (Code Review) 15 Sep '24

15 Sep '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel. Varun Upadhyay has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/84351?usp=email ) Change subject: mb/google/brya/var/trulo: Update ISH GPIO config for tablet mode switch ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84351/comment/067ef74a_84c52919?us… : PS2, Line 13: TEST=Builds successfully for google/trulo. > > Do you have access to the board, and could you verify that it works? […] yes, Its been tested with ISH changes CL-5849310 -- To view, visit https://review.coreboot.org/c/coreboot/+/84351?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id22e397e46b522428ffdabe34a445ed7e4fb6fc5 Gerrit-Change-Number: 84351 Gerrit-PatchSet: 2 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jayvik Desai <jayvik(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 15 Sep 2024 13:17:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds
by Matt DeVillier (Code Review) 15 Sep '24

15 Sep '24

Attention is currently required from: Jakub Czapiga, Jędrzej Ciupis, Subrata Banik. Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84359?usp=email ) Change subject: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/dedede/Kconfig: https://review.coreboot.org/c/coreboot/+/84359/comment/029b91af_7e249504?us… : PS1, Line 39: select SOC_INTEL_CRASHLOG > > ummm, can you move the below code into JSL SoC Kconfig in that way, it might help you ? […] I also don't know why we'd want to move it to the SoC vs the mainboard -- To view, visit https://review.coreboot.org/c/coreboot/+/84359?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53be4befe9a04bdaece21f40f93af6599baa7e0b Gerrit-Change-Number: 84359 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jędrzej Ciupis <jciupis(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jędrzej Ciupis <jciupis(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Comment-Date: Sun, 15 Sep 2024 12:11:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Enable CRASHLOG for Chrome OS
by Matt DeVillier (Code Review) 15 Sep '24

15 Sep '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Rishika Raj, Subrata Banik. Matt DeVillier has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84365?usp=email ) Change subject: soc/intel/alderlake: Enable CRASHLOG for Chrome OS ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/84365/comment/9be79649_9fa316d5?us… : PS1, Line 87: MAINBOARD_HAS_CHROMEOS while this is consistent with the previous behavior, I'm not sure why you want to move it to the SoC code, rather than select it in the mainboard(s) only for ChromeOS -- To view, visit https://review.coreboot.org/c/coreboot/+/84365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia23ef1cbebdba9a3b724204eb25ee788afa3e8fd Gerrit-Change-Number: 84365 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sun, 15 Sep 2024 12:10:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds
by Matt DeVillier (Code Review) 15 Sep '24

15 Sep '24

Attention is currently required from: Jakub Czapiga, Jędrzej Ciupis, Subrata Banik. Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84359?usp=email ) Change subject: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/dedede/Kconfig: https://review.coreboot.org/c/coreboot/+/84359/comment/dc66c7eb_fa6b2ceb?us… : PS1, Line 39: select SOC_INTEL_CRASHLOG > ummm, can you move the below code into JSL SoC Kconfig in that way, it might help you ? no, because `MAINBOARD_HAS_CHROMEOS` is always true for dedede/brya/brox etc. IT has to be conditional on `CHROMEOS` -- To view, visit https://review.coreboot.org/c/coreboot/+/84359?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53be4befe9a04bdaece21f40f93af6599baa7e0b Gerrit-Change-Number: 84359 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jędrzej Ciupis <jciupis(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jędrzej Ciupis <jciupis(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Comment-Date: Sun, 15 Sep 2024 12:08:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"
by Subrata Banik (Code Review) 15 Sep '24

15 Sep '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84368?usp=email ) Change subject: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence" ...................................................................... Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence" This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309. This workaround is not valid with the latest Intel PRQ silicon, so I'm dropping it now. Additionally, able to boot to ChromeOS without any hang, and I also ran an S0ix cycle without any failures. BUG=b:244082753 TEST=Able to boot google/rex0 to CrOS. Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/acpi/tcss.asl 1 file changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/84368/1 diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index dbe76f2..24d28f3 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -602,13 +602,7 @@ } /* Request IOM for D3 cold entry sequence. */ - /* - * FIXME: Remove this workaround after resolving b/244082753 - * - * Document #742990: TCCold exit flow may not complete when processor at package - * C0. The implication is that the system may hang. - */ - // TD3C = 1 + TD3C = 1 } PowerResource (D3C, 5, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/84368?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e Gerrit-Change-Number: 84368 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[master]: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"
by Subrata Banik (Code Review) 15 Sep '24

15 Sep '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, John Zhao, Kapil Porwal, Subrata Banik, Tarun, Tarun Tuli, Tim Wawrzynczak, Utkarsh H Patel. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, John Zhao, Kapil Porwal, Tarun, Tarun Tuli, Tim Wawrzynczak, Utkarsh H Patel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84367?usp=email to look at the new patch set (#2). Change subject: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence" ...................................................................... Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence" This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309. This workaround is not valid with the latest Intel PRQ silicon, so I'm dropping it now. I was able to boot to ChromeOS without any hang, and I also ran an S0ix cycle without any failures. BUG=b:244082753 TEST=Able to boot google/rex0 to CrOS. Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/acpi/tcss.asl 1 file changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/84367/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84367?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e Gerrit-Change-Number: 84367 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence
by Subrata Banik (Code Review) 15 Sep '24

15 Sep '24

Subrata Banik has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/67560?usp=email ) Change subject: soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/67560?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: revert Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17bcde75360c4b2b40885d355702e3e5f45d770a Gerrit-Change-Number: 67560 Gerrit-PatchSet: 6 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[master]: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"
by Subrata Banik (Code Review) 15 Sep '24

15 Sep '24

Attention is currently required from: John Zhao, Kapil Porwal, Tarun Tuli, Tim Wawrzynczak, Utkarsh H Patel. Hello build bot (Jenkins), Utkarsh H Patel, Tarun Tuli, John Zhao, Tim Wawrzynczak, Kapil Porwal, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/84367?usp=email to review the following change. Change subject: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence" ...................................................................... Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence" This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309. This workaround is not valid with the latest Intel PRQ silicon, so I'm dropping it now. I was able to boot to ChromeOS without any hang, and I also ran an S0ix cycle without any failures. BUG=b:244082753 TEST=Able to boot google/rex0 to CrOS. Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e --- M src/soc/intel/meteorlake/acpi/tcss.asl 1 file changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/84367/1 diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index c2212f0..87d6521 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -719,13 +719,7 @@ } /* Request IOM for D3 cold entry sequence. */ - /* - * FIXME: Remove this workaround after resolving b/244082753 - * - * Document #742990: TCCold exit flow may not complete when processor at package - * C0. The implication is that the system may hang. - */ - // TD3C = 1 + TD3C = 1 } PowerResource (D3C, 5, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/84367?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e Gerrit-Change-Number: 84367 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/brya: Drop redundant entries of crashlog config
by Elyes Haouas (Code Review) 15 Sep '24

15 Sep '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Rishika Raj, Subrata Banik. Elyes Haouas has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84364?usp=email ) Change subject: mb/google/brya: Drop redundant entries of crashlog config ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84364?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaff7954d4dafb4c6ca72a1521dfb434fb36b495a Gerrit-Change-Number: 84364 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 15 Sep 2024 10:19:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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