coreboot-gerrit September 2024

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Cliff Huang (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... Patch Set 125: (4 comments) Patchset: PS123: > As GPE1 changes might take longer time, i'm suggesting to push CLs w/o GPE1 for now and we can add t […] Acknowledged File src/soc/intel/pantherlake/acpi/southbridge.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/709e75dd_111d50b5?us… : PS81, Line 11: #if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB) > > Subrata, I don't quite follow. The CL 84138 you mentioned contains changes removing soc/itss.h. […] Done File src/soc/intel/pantherlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/24d64fb9_c3b963f9?us… : PS123, Line 218: If (CondRefOf (\_SB.PCI0.TXHC)) { : /* Invoke PCIe root ports wake event handler */ : \_SB.PCI0.TRP0.HPEV() : } : /* Check Root Port 0 for a Hot Plug Event if the port is enabled */ : If (((\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) && \_SB.PCI0.TRP0.HPSX)) { : If (\_SB.PCI0.TRP0.PDCX) { : /* Clear all status bits */ : \_SB.PCI0.TRP0.PDCX = 1 : \_SB.PCI0.TRP0.HPSX = 1 : /* : * Intercept Presence Detect Changed interrupt and make sure : * the L0s is disabled on empty slots. : */ : If (!\_SB.PCI0.TRP0.PDSX) { : /* : * The PCIe slot is empty, so disable L0s on hot unplug. : */ : \_SB.PCI0.TRP0.L0SE = 0 : } : /* Performs proper notification to the OS. */ : Notify (\_SB.PCI0.TRP0, 0) : } Else { : /* False event. Clear Hot-Plug status, then exit. */ : \_SB.PCI0.TRP0.HPSX = 1 : } : } > please create helper function and call into w/o adding implementation for each RP here. defer GPE1 related changes from upstream. File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/482dcb84_e5505f8d?us… : PS123, Line 236: } > please leave one space before Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 125 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 14 Sep 2024 00:37:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Cliff Huang (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Cliff Huang has uploaded a new patch set (#125) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... soc/intel/ptl: Add SoC ACPI directory for Panther Lake List of changes: 1. Select common ACPI Kconfig to include common ACPI code block from IA-common code 2. Select ACPI Kconfig support for wake-up from sleep states. 3. Add SoC ASL code for SoC IPs like IPU, HDA etc. 4. PTL replaces DMI3 with SAF to ensure common/block/acpi/acpi/northbridge.asl binding with PTL change, #if DMI_BASE_SIZE guard check is added in northbridge.asl 5. include GPIO ASL that supports new pinctrl schema. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl A src/soc/intel/pantherlake/acpi/gpio.asl A src/soc/intel/pantherlake/acpi/hda.asl A src/soc/intel/pantherlake/acpi/pcie.asl A src/soc/intel/pantherlake/acpi/serialio.asl A src/soc/intel/pantherlake/acpi/southbridge.asl A src/soc/intel/pantherlake/acpi/tcss.asl A src/soc/intel/pantherlake/acpi/tcss_dma.asl A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl A src/soc/intel/pantherlake/acpi/tcss_xhci.asl A src/soc/intel/pantherlake/acpi/xhci.asl 12 files changed, 2,939 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/125 -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 125 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines
by Cliff Huang (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84297?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Add GPE1 defines ...................................................................... soc/intel/ptl: Add GPE1 defines defines for GPE number for additional STD GPE0 in PTL defines for GPE number for GPE1 defines for GPE1 bits NOTE: All GEP1 bits are STD GPE bits. BUG=362310295 TEST=This cannot be tested directly. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 --- M src/soc/intel/pantherlake/include/soc/gpe.h M src/soc/intel/pantherlake/include/soc/pm.h 2 files changed, 369 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84297/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 Gerrit-Change-Number: 84297 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: soc/mt6366: Work around GCC LTO build
by Julius Werner (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Arthur Heymans, Cliff Huang, Elyes Haouas, Hung-Te Lin, Jérémy Compostella, Lance Zhao, Tim Wawrzynczak, Yidi Lin, Yu-Ping Wu. Julius Werner has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84208?usp=email ) Change subject: soc/mt6366: Work around GCC LTO build ...................................................................... Patch Set 8: (1 comment) File src/soc/mediatek/mt8186/mt6366.c: https://review.coreboot.org/c/coreboot/+/84208/comment/1994176a_7bcac456?us… : PS8, Line 10: #define NO_BUILDTIME_ASSERT > Code like […] Sure, but is doing this by file more robust? Maybe I'm missing something here but to me it sounds like whether GCC bugs out on a particular assert() statement or not seems almost entirely random (within some constraints, e.g. the value needs to depend on passed-in function parameters). There's no reason why we should be saying that the mt6366.c file is more likely to see this issue than any other files. As far as I understand, all Arthur has been doing here is to try it out, see which files had errors and then add the `#define` to those files... and the next time anyone changes the code and the errors move around to other assert statements, we'll have to just try it out and add the `#define` to those files as well. So it seems to me that until GCC fixes this bug, our only choice (other than disabling build-time assertions completely for the GCC+LTO combo, which is also worth considering) is to keep playing whack-a-mole with this bug whenever it crops up somewhere. The only question is whether we want to do that at the level of whole files or at the level of single statements. Since as far as I understand there should be no reason to assume that just because one assert statement in a file had this issue the other statements in that file are somehow more likely to also have it (compared to the rest of the code base), I don't think it makes sense to aggregate this workaround on a per-file basis. (The syntax can of course be bikeshed, e.g. if you want it to look less jarring it could be `assert()` and `assertX()` or something like that. I don't really care about the naming.) -- To view, visit https://review.coreboot.org/c/coreboot/+/84208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e Gerrit-Change-Number: 84208 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 13 Sep 2024 23:14:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Define 64-bit FSP_STATUS_GLOBAL_RESET
by Jérémy Compostella (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Pranava Y N, Ronak Kanabar, Subrata Banik, Tarun. Hello Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Pranava Y N, Ronak Kanabar, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84356?usp=email to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Define 64-bit FSP_STATUS_GLOBAL_RESET ...................................................................... drivers/intel/fsp2_0: Define 64-bit FSP_STATUS_GLOBAL_RESET FSP reset status type is efi_return_status_t (not uint32_t) which size varies with the FSP binary architecture (32-bit vs 64-bit). This commit defines FSP_STATUS_GLOBAL_RESET accordingly to PLATFORM_USES_FSP2_X86_32 and take care of the side effect of such 64-bit value. BUG=b:348678529 TEST=Verified with fatcat mainboard on pantherlake reference board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5f Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/include/efi/efi_datatype.h M src/soc/intel/common/fsp_reset.c M src/soc/intel/common/reset.h M src/soc/intel/meteorlake/chip.c M src/soc/intel/pantherlake/chip.c 6 files changed, 24 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/84356/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5f Gerrit-Change-Number: 84356 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Karthik Ramasubramanian (Code Review) 14 Sep '24

14 Sep '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... mb/google/brox: Fix booting to kernel without battery When battery is disconnected and only adaptor is connected higher PL2 power draw causes cpu brown out and system does not boot to kernel. To avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome power spikes from SoC during boot. Remove Psys implementation as it impacts active state platform performance. BUG=b:335046538,b:329722827 BRANCH=None TEST=Able to successfully boot on 3 different Brox proto2 SKU1 and SKU2 boards with 65W, 45W and 30W adaptors for 3 iterations of cold boot. Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83752 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/romstage.c M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c M src/mainboard/google/brox/variants/brox/ramstage.c M src/soc/intel/alderlake/chip.h 5 files changed, 59 insertions(+), 23 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index a1d284b..8fd43f4 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -117,6 +117,19 @@ hex default 0x4 if BOARD_GOOGLE_BASEBOARD_BROX +config PL4_LIMIT_FOR_CRITICAL_BAT_BOOT + int + default 9 + help + Select this if the variant has to boot even with low battery, critical battery + threshold, or when the battery is physically disconnected. PL4, which stands for + Processor Instantaneous Power or Absolute Peak Power, controls the highest power draw + from the processor at any given moment within the Pl1Tau duration. Therefore, PL4 + acts as a failsafe mechanism to set an upper threshold limit for the processor's + instantaneous power draw. For a 30W adapter, the maximum peak power is set at 9 + watts, which is 30W multiplied by 32% efficiency. This default pl4 value is set for + 30W or any higher adapter rating, such as 45W or 65W. + config DRIVER_TPM_I2C_ADDR hex default 0x50 diff --git a/src/mainboard/google/brox/romstage.c b/src/mainboard/google/brox/romstage.c index 4e88eca..ced9184 100644 --- a/src/mainboard/google/brox/romstage.c +++ b/src/mainboard/google/brox/romstage.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> #include <fsp/api.h> #include <gpio.h> #include <soc/romstage.h> @@ -19,6 +20,14 @@ const struct pad_config *pads; size_t pads_num; + /* If battery is not present - Boot with maximum non-turbo frequency */ + if (CONFIG(EC_GOOGLE_CHROMEEC) && + !google_chromeec_is_battery_present_and_above_critical_threshold()) { + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + mem_cfg->BootFrequency = MAX_NONTURBO_PERFORMANCE; + printk(BIOS_DEBUG, "Boot Frequency is set to %u\n", mem_cfg->BootFrequency); + } + memcfg_init(memupd, mem_config, &spd_info, half_populated); pads = variant_romstage_gpio_table(&pads_num); diff --git a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c index 038255f..85c3c48 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c @@ -42,13 +42,27 @@ } if (i == num_entries) { - printk(BIOS_ERR, "Cannot find correct brox sku index (mchid = %u).\n", mchid); + printk(BIOS_ERR, "Cannot find brox sku index (mchid = %u)\n", mchid); return false; } return true; } +static void variant_pl4_override(struct soc_power_limits_config *config, + const struct cpu_power_limits *limits, size_t brox_idx) +{ + if (!config->tdp_pl4) + return; + + /* limiting PL4 value for battery disconnected or below critical threshold */ + if (CONFIG_PL4_LIMIT_FOR_CRITICAL_BAT_BOOT && + (!google_chromeec_is_battery_present_and_above_critical_threshold())) + config->tdp_pl4 = CONFIG_PL4_LIMIT_FOR_CRITICAL_BAT_BOOT; + else + config->tdp_pl4 = DIV_ROUND_UP(limits[brox_idx].pl4_power, MILLIWATTS_TO_WATTS); +} + void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) { const struct device *policy_dev; @@ -61,30 +75,33 @@ if (!num_entries) return; - policy_dev = DEV_PTR(dptf_policy); - if (!policy_dev) - return; - if (!get_sku_index(limits, num_entries, &intel_idx, &brox_idx)) return; - config = policy_dev->chip_info; - settings = &config->controls.power_limits; conf = config_of_soc(); soc_config = &conf->power_limits_config[intel_idx]; + variant_pl4_override(soc_config, limits, brox_idx); + + policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) { + printk(BIOS_INFO, "DPTF policy not set\n"); + return; + } + config = policy_dev->chip_info; + settings = &config->controls.power_limits; settings->pl1.min_power = limits[brox_idx].pl1_min_power; settings->pl1.max_power = limits[brox_idx].pl1_max_power; settings->pl2.min_power = limits[brox_idx].pl2_min_power; settings->pl2.max_power = limits[brox_idx].pl2_max_power; if (soc_config->tdp_pl2_override != 0) { - settings->pl2.max_power = soc_config->tdp_pl2_override * 1000; + settings->pl2.max_power = soc_config->tdp_pl2_override * MILLIWATTS_TO_WATTS; settings->pl2.min_power = settings->pl2.max_power; } - if (soc_config->tdp_pl4 == 0) - soc_config->tdp_pl4 = DIV_ROUND_UP(limits[brox_idx].pl4_power, - MILLIWATTS_TO_WATTS); + printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", + settings->pl1.min_power, settings->pl1.max_power, settings->pl2.min_power, + settings->pl2.max_power, soc_config->tdp_pl4); } /* @@ -138,7 +155,8 @@ watts = ((u32)current_ma * volts_mv) / 1000000; } /* If battery is present and has enough charge, add discharge rate */ - if (CONFIG(EC_GOOGLE_CHROMEEC) && google_chromeec_is_battery_present_and_above_critical_threshold()) { + if (CONFIG(EC_GOOGLE_CHROMEEC) && + google_chromeec_is_battery_present_and_above_critical_threshold()) { watts += 65; } diff --git a/src/mainboard/google/brox/variants/brox/ramstage.c b/src/mainboard/google/brox/variants/brox/ramstage.c index 78e03ca..aef7a00 100644 --- a/src/mainboard/google/brox/variants/brox/ramstage.c +++ b/src/mainboard/google/brox/variants/brox/ramstage.c @@ -33,16 +33,6 @@ }, }; -const struct system_power_limits sys_limits[] = { - /* SKU_ID, TDP (Watts), psys_pl2 (Watts) */ - { PCI_DID_INTEL_RPL_P_ID_3, 15, 60 }, - { PCI_DID_INTEL_RPL_P_ID_4, 15, 60 }, -}; - -const struct psys_config psys_config = { - .efficiency = 86, -}; - void __weak variant_devtree_update(void) { uint32_t board_version = board_id(); @@ -52,7 +42,6 @@ size_t limits_size = ARRAY_SIZE(performance_efficient_limits); variant_update_power_limits(limits, limits_size); - variant_update_psys_power_limits(limits, sys_limits, limits_size, &psys_config); /* Disable I2C bus device for Touchscreen */ if (board_version >= 1) { diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index c3034ca..040b3d1 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -42,6 +42,13 @@ /* add ECC error injection if needed by a mainboard */ }; +/* FSPM UPD for setting the boot frequency */ +enum fspm_boot_freq { + MAX_BATTERY_PERFORMANCE, + MAX_NONTURBO_PERFORMANCE, + TURBO_PERFORMANCE +}; + /* Types of different SKUs */ enum soc_intel_alderlake_power_limits { ADL_P_142_242_282_15W_CORE, -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 34 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com>

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[XL] Change in coreboot[main]: mb/google/fatcat: Add Panther Lake SOC support
by Jérémy Compostella (Code Review) 14 Sep '24

14 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Cliff Huang, Felix Held, Jérémy Compostella, Paul Menzel, Pranava Y N, Saurabh Mishra, Subrata Banik. Jérémy Compostella has uploaded a new patch set (#176) to the change originally created by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email ) The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/fatcat: Add Panther Lake SOC support ...................................................................... mb/google/fatcat: Add Panther Lake SOC support Details: - This patch updates the original google/fatcat support added with Meteor Lake support as a workaround. - Adds initial support to build google/fatcat for Panther Lake SOC based board till bootblock stage. - Adds soc acpi file entry in mainboard dsdt.asl BUG=b:348678529 TEST=Able to build the google/fatcat and boot to bootblock stage using Intel® Simics® Pre Silicon Simulation platform for PTL. Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/Makefile.mk M src/mainboard/google/fatcat/chromeos-debug-fsp.fmd M src/mainboard/google/fatcat/chromeos.fmd M src/mainboard/google/fatcat/dsdt.asl M src/mainboard/google/fatcat/mainboard.c M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h M src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/fatcat/variants/fatcat/Makefile.mk A src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c A src/mainboard/google/fatcat/variants/fatcat/hda_verb.c M src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h A src/mainboard/google/fatcat/variants/fatcat/memory.c A src/mainboard/google/fatcat/variants/fatcat/overridetree.cb A src/mainboard/google/fatcat/variants/fatcat/variant.c 17 files changed, 1,894 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83419/176 -- To view, visit https://review.coreboot.org/c/coreboot/+/83419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Gerrit-Change-Number: 83419 Gerrit-PatchSet: 176 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XL] Change in coreboot[main]: mb/google/fatcat: Add Panther Lake SOC support
by Jérémy Compostella (Code Review) 13 Sep '24

13 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Cliff Huang, Felix Held, Jérémy Compostella, Paul Menzel, Pranava Y N, Saurabh Mishra, Subrata Banik. Jérémy Compostella has uploaded a new patch set (#175) to the change originally created by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Add Panther Lake SOC support ...................................................................... mb/google/fatcat: Add Panther Lake SOC support Details: - This patch updates the original google/fatcat support added with Meteor Lake support as a workaround. - Adds initial support to build google/fatcat for Panther Lake SOC based board till bootblock stage. - Adds soc acpi file entry in mainboard dsdt.asl BUG=b:348678529 TEST=Able to build the google/fatcat and boot to bootblock stage using Intel® Simics® Pre Silicon Simulation platform for PTL. Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/Makefile.mk M src/mainboard/google/fatcat/chromeos-debug-fsp.fmd M src/mainboard/google/fatcat/chromeos.fmd M src/mainboard/google/fatcat/dsdt.asl M src/mainboard/google/fatcat/mainboard.c M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h M src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/fatcat/variants/fatcat/Makefile.mk A src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c A src/mainboard/google/fatcat/variants/fatcat/hda_verb.c M src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h A src/mainboard/google/fatcat/variants/fatcat/memory.c A src/mainboard/google/fatcat/variants/fatcat/overridetree.cb A src/mainboard/google/fatcat/variants/fatcat/variant.c 17 files changed, 1,894 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83419/175 -- To view, visit https://review.coreboot.org/c/coreboot/+/83419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Gerrit-Change-Number: 83419 Gerrit-PatchSet: 175 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Define 64-bit FSP_STATUS_GLOBAL_RESET
by Jérémy Compostella (Code Review) 13 Sep '24

13 Sep '24

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84356?usp=email ) Change subject: drivers/intel/fsp2_0: Define 64-bit FSP_STATUS_GLOBAL_RESET ...................................................................... drivers/intel/fsp2_0: Define 64-bit FSP_STATUS_GLOBAL_RESET FSP reset status type is efi_return_status_t (not uint32_t) which size varies with the FSP binary architecture (32-bit vs 64-bit). This commit defines FSP_STATUS_GLOBAL_RESET accordingly to PLATFORM_USES_FSP2_X86_32 and take care of the side effect of such 64-bit value. BUG=b:348678529 TEST=Verified with fatcat mainboard on pantherlake reference board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5f Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/common/fsp_reset.c M src/soc/intel/common/reset.h M src/soc/intel/meteorlake/chip.c M src/soc/intel/pantherlake/chip.c 5 files changed, 23 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/84356/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8e9dcdc..40a4423 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -374,12 +374,18 @@ config FSP_STATUS_GLOBAL_RESET hex depends on SOC_INTEL_COMMON_FSP_RESET - default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3 - default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4 - default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5 - default 0x40000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6 - default 0x40000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7 - default 0x40000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8 + default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3 && PLATFORM_USES_FSP2_X86_32 + default 0x4000000000000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3 + default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4 && PLATFORM_USES_FSP2_X86_32 + default 0x4000000000000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4 && PLATFORM_USES_FSP2_X86_32 + default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5 && PLATFORM_USES_FSP2_X86_32 + default 0x4000000000000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5 + default 0x40000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6 && PLATFORM_USES_FSP2_X86_32 + default 0x4000000000000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6 + default 0x40000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7 && PLATFORM_USES_FSP2_X86_32 + default 0x4000000000000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7 + default 0x40000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8 && PLATFORM_USES_FSP2_X86_32 + default 0x4000000000000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8 default 0xffffffff help If global reset is supported by SoC then select the correct status value for global diff --git a/src/soc/intel/common/fsp_reset.c b/src/soc/intel/common/fsp_reset.c index 2626c39..983d4fc 100644 --- a/src/soc/intel/common/fsp_reset.c +++ b/src/soc/intel/common/fsp_reset.c @@ -41,7 +41,7 @@ die("unknown reset type"); } -static uint32_t fsp_reset_type_to_status(EFI_RESET_TYPE reset_type) +static efi_return_status_t fsp_reset_type_to_status(EFI_RESET_TYPE reset_type) { efi_return_status_t status; @@ -68,7 +68,7 @@ * If reset type is `EfiResetPlatformSpecific` then relying on pch_reset_data structure * to know if the reset type is a global reset. */ -uint32_t fsp_get_pch_reset_status(void) +efi_return_status_t fsp_get_pch_reset_status(void) { size_t size; const struct fsp_reset_hob *hob = fsp_find_extension_hob_by_guid(fsp_reset_guid, &size); diff --git a/src/soc/intel/common/reset.h b/src/soc/intel/common/reset.h index d9c6ac6..658223c 100644 --- a/src/soc/intel/common/reset.h +++ b/src/soc/intel/common/reset.h @@ -3,6 +3,8 @@ #ifndef _INTEL_COMMON_RESET_H_ #define _INTEL_COMMON_RESET_H_ +#include <efi/efi_datatype.h> + /* * Implement SoC specific global reset (i.e. a reset of both host and * ME partitions). Usually the ME is asked to perform the reset first. @@ -21,6 +23,6 @@ * If reset type if `EfiResetPlatformSpecific` then relying on pch_reset_data structure * to know if the reset type is a global reset. */ -uint32_t fsp_get_pch_reset_status(void); +efi_return_status_t fsp_get_pch_reset_status(void); #endif /* _INTEL_COMMON_RESET_H_ */ diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 84b9235b2..326104d 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -264,7 +264,7 @@ static void soc_init_final_device(void *chip_info) { - uint32_t reset_status = fsp_get_pch_reset_status(); + efi_return_status_t reset_status = fsp_get_pch_reset_status(); if (reset_status == FSP_SUCCESS) return; @@ -273,8 +273,8 @@ fsp_handle_reset(reset_status); /* Control shouldn't return here */ - die_with_post_code(POSTCODE_HW_INIT_FAILURE, - "Failed to handle the FSP reset request with error 0x%08x\n", reset_status); + fsp_die_with_post_code(reset_status, POSTCODE_HW_INIT_FAILURE, + "Failed to handle the FSP reset request"); } struct chip_operations soc_intel_meteorlake_ops = { diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c index 6b596b0..0d5406e 100644 --- a/src/soc/intel/pantherlake/chip.c +++ b/src/soc/intel/pantherlake/chip.c @@ -262,7 +262,7 @@ static void soc_init_final_device(void *chip_info) { - uint32_t reset_status = fsp_get_pch_reset_status(); + efi_return_status_t reset_status = fsp_get_pch_reset_status(); if (reset_status == FSP_SUCCESS) return; @@ -271,8 +271,8 @@ fsp_handle_reset(reset_status); /* Control shouldn't return here */ - die_with_post_code(POSTCODE_HW_INIT_FAILURE, - "Failed to handle the FSP reset request with error 0x%08x\n", reset_status); + fsp_die_with_post_code(reset_status, POSTCODE_HW_INIT_FAILURE, + "Failed to handle the FSP reset request"); } struct chip_operations soc_intel_pantherlake_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/84356?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5f Gerrit-Change-Number: 84356 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[L] Change in coreboot[main]: mb/hardkernel/odroid-h4: Add support for ODROID-H4 series
by Angel Pons (Code Review) 13 Sep '24

13 Sep '24

Attention is currently required from: Alicja Michalska, Benjamin Doron, David Milosevic, Felix Held, Felix Singer, Lean Sheng Tan, Marvin Drees, Matt DeVillier. Angel Pons has posted comments on this change by David Milosevic. ( https://review.coreboot.org/c/coreboot/+/83979?usp=email ) Change subject: mb/hardkernel/odroid-h4: Add support for ODROID-H4 series ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83979/comment/3ec1f328_7f954c56?us… : PS11, Line 43: - PECI: undocumented protocol and undocumented Super I/O > CB:80318 tells me the IT8613E has banks. […] Will figure out later. Fan speeds up to full speed once the measured temperature gets high enough, but the on-board sensor isn't great. -- To view, visit https://review.coreboot.org/c/coreboot/+/83979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Gerrit-Change-Number: 83979 Gerrit-PatchSet: 13 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Fri, 13 Sep 2024 20:46:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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