coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: lib/jpeg: return string (not int) error messages
by Nico Huber (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Nigel Tao. Nico Huber has posted comments on this change by Nigel Tao. ( https://review.coreboot.org/c/coreboot/+/84341?usp=email ) Change subject: lib/jpeg: return string (not int) error messages ...................................................................... Patch Set 5: Code-Review+2 (2 comments) Patchset: PS5: It feels uncommon to directly return a string in C (compared to `errno` and similar). But I actually don't mind this in a cohesive environment, i.e. not an API that is used all over the place. File src/lib/jpeg.h: https://review.coreboot.org/c/coreboot/+/84341/comment/428691e5_1dced40d?us… : PS5, Line 7: Should have a comment that `!= NULL` is an error. -- To view, visit https://review.coreboot.org/c/coreboot/+/84341?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I465a6eebc2a41ca9a618b1e86dee015cea40800b Gerrit-Change-Number: 84341 Gerrit-PatchSet: 5 Gerrit-Owner: Nigel Tao <nigeltao(a)golang.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nigel Tao <nigeltao(a)golang.org> Gerrit-Comment-Date: Thu, 12 Sep 2024 20:48:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: lib/jpeg: enable dst-pixel-format allowlist
by Nico Huber (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Nigel Tao. Nico Huber has posted comments on this change by Nigel Tao. ( https://review.coreboot.org/c/coreboot/+/84340?usp=email ) Change subject: lib/jpeg: enable dst-pixel-format allowlist ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > What do you think? Technically, it's undefined. Some people run VGA option roms in coreboot, and then you get the framebuffer format that the option rom supports. Which also shows an issue here: It looks like when the wuffs decoder was added, the format was hardcoded. I guess to mimic the old decoder. Saving space is much appreciate, still. What we could do here could be to decide the format based on Kconfig options. For every gfx init option except for the option rom we should know the format, including the color depth, at compile time. If this is something you would like to explore, I could have a look at translating the options to the pixel format. -- To view, visit https://review.coreboot.org/c/coreboot/+/84340?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie29592f74f245cb890d18b68060640e9bab192b2 Gerrit-Change-Number: 84340 Gerrit-PatchSet: 3 Gerrit-Owner: Nigel Tao <nigeltao(a)golang.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nigel Tao <nigeltao(a)golang.org> Gerrit-Comment-Date: Thu, 12 Sep 2024 20:37:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nigel Tao <nigeltao(a)golang.org>

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[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines
by Cliff Huang (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email ) Change subject: soc/intel/ptl: Add GPE1 defines ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/pantherlake/include/soc/pm.h: https://review.coreboot.org/c/coreboot/+/84297/comment/0eb6ab6c_fe97d62c?us… : PS4, Line 285: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) : uint32_t gpe1_sts[3]; : uint32_t gpe1_en[3]; : #endif > please maintain the order. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 Gerrit-Change-Number: 84297 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 12 Sep 2024 19:22:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines
by Cliff Huang (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Saurabh Mishra, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84297?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Add GPE1 defines ...................................................................... soc/intel/ptl: Add GPE1 defines defines for GPE number for additional STD GPE0 in PTL defines for GPE number for GPE1 defines for GPE1 bits NOTE: All GEP1 bits are STD GPE bits. BUG=362310295 TEST=This cannot be tested directly. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 --- M src/soc/intel/pantherlake/include/soc/gpe.h M src/soc/intel/pantherlake/include/soc/pm.h 2 files changed, 297 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84297/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 Gerrit-Change-Number: 84297 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: lib: Compile memcpy, memset and __clzsi2 without LTO
by Paul Menzel (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Arthur Heymans. Paul Menzel has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84335?usp=email ) Change subject: lib: Compile memcpy, memset and __clzsi2 without LTO ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84335/comment/51109152_ea79d40a?us… : PS4, Line 11: Paste the error, and for posterity mention the GCC version? -- To view, visit https://review.coreboot.org/c/coreboot/+/84335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieecd198932545d1ac2bbe0354183519c544ff971 Gerrit-Change-Number: 84335 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 12 Sep 2024 19:17:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Add RTS522A vdd ctrl by gpio
by Paul Menzel (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Jian Tong, Kun Liu. Paul Menzel has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/84254?usp=email ) Change subject: mb/google/brox/var/lotso: Add RTS522A vdd ctrl by gpio ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84254/comment/7b2398ea_eb78b05b?us… : PS2, Line 8: Please mention your source. -- To view, visit https://review.coreboot.org/c/coreboot/+/84254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id256b3a94d3c8ed6f6832d63ecc74c2438c7d15a Gerrit-Change-Number: 84254 Gerrit-PatchSet: 2 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 12 Sep 2024 19:16:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
by Paul Menzel (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email ) Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz ...................................................................... Patch Set 12: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84298/comment/65e5547f_bb36e3e3?us… : PS9, Line 13: measure eMMC clock ok : > https://partnerissuetracker.corp.google.com/issues/356578805#comment26 […] I am denied access to that URL. Commit messages need to be self-contained. It’d be great if you added it. Commit Message: https://review.coreboot.org/c/coreboot/+/84298/comment/d37e3ed7_41344af7?us… : PS12, Line 11: When we need to set a clock output frequency, we actually set a frequency division value. Originally, we set the source clock frequency to 50MHz, the target frequency to 400KHz, and the frequency division value to 125. However, the actual source clock frequency is 400MHz, so the final actual output is 400MHz/125=3.2MHz. When we set the source clock frequency correctly, we can get the correct frequency division value, and then get the correct clock output. Please add a blank line between paragraphs, and re-flow it for 72 characters per line. File src/soc/mediatek/common/msdc.c: https://review.coreboot.org/c/coreboot/+/84298/comment/2a133c7c_222bd9f8?us… : PS9, Line 432: host->src_hz = 400 * 1000 * 1000; Mengqi, thank you for the explanation. Please also update the summary then. Maybe: > Correct src clk frq to 400 MHz for eMMMC clk of 400 kHz -- To view, visit https://review.coreboot.org/c/coreboot/+/84298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381 Gerrit-Change-Number: 84298 Gerrit-PatchSet: 12 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 12 Sep 2024 19:16:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Mengqi Zhang <mengqi.zhang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: mb/asus: Add PRIME H610M-K D4
by Felix Singer (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Máté Kukri. Felix Singer has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/84243?usp=email ) Change subject: mb/asus: Add PRIME H610M-K D4 ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84243/comment/4a74e4b6_ee9540c1?us… : PS10, Line 11: TODO (please don't submit before this is removed): Maybe mark it as WIP again, so that people don't start reviewing. -- To view, visit https://review.coreboot.org/c/coreboot/+/84243?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ab821f6799009d231de4d21219f0ac2ae89c5c9 Gerrit-Change-Number: 84243 Gerrit-PatchSet: 10 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Comment-Date: Thu, 12 Sep 2024 19:06:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines
by Cliff Huang (Code Review) 12 Sep '24

12 Sep '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Saurabh Mishra, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email ) Change subject: soc/intel/ptl: Add GPE1 defines ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/pantherlake/include/soc/gpe.h: https://review.coreboot.org/c/coreboot/+/84297/comment/56fca2dd_35810639?us… : PS4, Line 30: 146 > unable to follow why the index is 145 or 0x91 ? […] GPE1[0] starts from 0x80 (i.e. 128 dec) CNVI_BT_PME_B0 is bit 18, 128 + 18 = 146 (0x92), corresponding to _L92 events. -- To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 Gerrit-Change-Number: 84297 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 12 Sep 2024 19:02:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: mb/asus: Add PRIME H610M-K D4
by Máté Kukri (Code Review) 12 Sep '24

12 Sep '24

Máté Kukri has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/84243?usp=email ) Change subject: mb/asus: Add PRIME H610M-K D4 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84243?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ab821f6799009d231de4d21219f0ac2ae89c5c9 Gerrit-Change-Number: 84243 Gerrit-PatchSet: 10 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 12 Sep 2024 18:42:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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coreboot-gerrit September 2024