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Change subject: ec/google/chromeec: Ensure pre-CR50 devices use "short" battery strings
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> > check for the more general TPM_GOOGLE config […]
verified patch set 2 on google/lulu
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Hello Caveh Jalali, Forest Mittelberg, Peter Marheine, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84300?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: ec/google/chromeec: Ensure pre-CR50 devices use "short" battery strings
......................................................................
ec/google/chromeec: Ensure pre-CR50 devices use "short" battery strings
Commit b97ec4f0166b ("chromeec: support reading long battery strings")
added support for reading long battery strings, but the method used to
determine if this feature is supported causes Windows to hang when
booting on older pre-CR50 ChromeOS devices. Add a short circuit to the
BRSX method to ensure that pre-CR50 devices use older/shorter strings.
In testing, affected platforms were Broadwell/Braswell and earlier.
Skylake is pre-CR50 as well, but unaffected. No adverse impact to
grouping it with the others as those boards do not support or use
longer battery strings.
TEST=build/boot Windows on google link, wolf, samus, chell and others.
Verify boot successful and battery info populated correctly.
Change-Id: If3686dc9b82b44202947081ec7e253317deb8fff
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/ec/google/chromeec/acpi/battery.asl
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/84300/2
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Change subject: [RFC] ec/google/chromeec: Guard reading long battery strings
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> check for the more general TPM_GOOGLE config
that seems like the cleanest solution, not sure how I missed that existing
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Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
......................................................................
Patch Set 12:
(1 comment)
File src/soc/mediatek/common/msdc.c:
https://review.coreboot.org/c/coreboot/+/84298/comment/32e2c289_418b107f?us… :
PS9, Line 432: host->src_hz = 400 * 1000 * 1000;
> Do you mean `50 * 1000 * 1000` is a wrong reference value because the actual source clock is running […]
Is the source clock always 400MHz on all platforms? Or is it a platform-specific value that we should probably set a config, and use the config here?
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Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400 kHz
......................................................................
Patch Set 12: Code-Review+2
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/cb769998_d22a5aec?us… :
PS12, Line 14: measure eMMC clock ok
please also measure the boot time.
File src/soc/mediatek/common/msdc.c:
https://review.coreboot.org/c/coreboot/+/84298/comment/b4ef30b6_156bddb0?us… :
PS9, Line 432: host->src_hz = 400 * 1000 * 1000;
> When we need to set a clock output frequency, we actually set a frequency division value. […]
Do you mean `50 * 1000 * 1000` is a wrong reference value because the actual source clock is running at `400MHz`?
So we should set `host->src_hz` to `400 * 1000 * 1000` in order to compute correct devision number ?
File src/soc/mediatek/common/msdc.c:
https://review.coreboot.org/c/coreboot/+/84298/comment/328be697_963955ae?us… :
PS12, Line 353: msdc_debug("sclk: %d\n", sclk);
can you attach this log to the commit message ? (before and after the patch)
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Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Subrata Banik.
Hello Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Rishika Raj, Ronak Kanabar, Shelley Chen, Subrata Banik, build bot (Jenkins),
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
mb/google/brox: Fix booting to kernel without battery
When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/mainboard/google/brox/Kconfig
M src/mainboard/google/brox/romstage.c
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/brox/ramstage.c
M src/soc/intel/alderlake/chip.h
5 files changed, 59 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83752/32
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