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Change subject: soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/84392/comment/a51385c4_84ee9904?us… :
PS2, Line 111: HAVE
> do you wish to land this CL as is or plan to change SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to SOC_INT […]
Subra, Yes. I will need to add CL for SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1 and change this accordingly.
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Change subject: soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS3:
> Please submit this CL without rebasing into the PTL recipe.
Subrata, can you consider this to be part of PTL recipe? We need this flag set to '0' since we don't have DMI in PTL.
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Change subject: soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84349/comment/6da6afe8_5f72f7fa?us… :
PS3, Line 12: Verified on Intel® Simics® Pre Silicon Simulation platform
: for PTL using google/fatcat mainboard.
:
> How? Was booting not possible before, and now it is?
Done
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Change subject: soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI
......................................................................
Patch Set 5:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84349/comment/69d5727d_90577957?us… :
PS3, Line 7: soc/intel/common/block/acpi/exclude DMI fixed memory range if no DMI
> I think the colon is missing to separate the prefix from the summary.
Done
https://review.coreboot.org/c/coreboot/+/84349/comment/f902d6cd_69930cac?us… :
PS3, Line 9: exclude DMI in northbridge.asl if DMI_BASE_SIZE is '0'
> Why?
Done
https://review.coreboot.org/c/coreboot/+/84349/comment/4307a3a3_5372abd7?us… :
PS3, Line 9: exclude
> Exclude
Done
File src/soc/intel/common/block/acpi/acpi/northbridge.asl:
https://review.coreboot.org/c/coreboot/+/84349/comment/7b148e54_1403d535?us… :
PS3, Line 294: #if DMI_BASE_SIZE != 0
> nit […]
Done
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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84349?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI
......................................................................
soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI
In newer SOC, such as PTL, there is no DMI. Exclude DMI memory range in
northbridge.asl if DMI_BASE_SIZE is '0'
BUG=b:348678529
TEST=Build CB with DMI_BASE_SIZE set to '0' in the SOC directory. Boot
to OS and check ACPI PDRC device from the ACPI DSDT table. There should
not have an entry for DMI in its _CRS method.
Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d
---
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/84349/6
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Change subject: payloads/depthcharge: Add default 64-bit libpayload config
......................................................................
Patch Set 9:
(1 comment)
File payloads/libpayload/configs/defconfig_64:
https://review.coreboot.org/c/coreboot/+/84107/comment/07c5c9ac_4ae93af3?us… :
PS8, Line 1: # NOTE: remove to test _LP64 issue: CONFIG_LP_ARCH_X86_64=y
> If this is commented out it's same as defconfig. […]
Yes. I think it is related, but not sure how to build 3rdparty/cmocka/ which will build libpayload/tests/mock. In our build, we don't build tests directory under libpayload.
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Mario Scheithauer has posted comments on this change by Mario Scheithauer. ( https://review.coreboot.org/c/coreboot/+/84399?usp=email )
Change subject: soc/intel/ehl/fsp_params: Fix double setting of 'PchPwrOptEnable'
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/84399/comment/7310ebcf_09ab3580?us… :
PS2, Line 327: params->PchPwrOptEnable = 0;
> I would keep this line just to be independent from the default FSP setting.
Yes, you're right. It also looks better.
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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ehl/fsp_params: Fix double setting of 'PchPwrOptEnable'
......................................................................
soc/intel/ehl/fsp_params: Fix double setting of 'PchPwrOptEnable'
If real-time tuning was enabled, 'PchPwrOptEnable' was set two times.
This patch fixes the issue.
BUG=none
TEST=Enabled UPD debug output and checked 'PchPwrOptEnable' offset
Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/soc/intel/elkhartlake/fsp_params.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/84399/3
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