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Change subject: Updating MESSAGE and RESOPONSE address for SMU Mail box for STX
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84384/comment/3ee27116_401d8e21?us… :
PS1, Line 7: Updating MESSAGE and RESOPONSE address for SMU Mail box for STX
soc/amd/glinda/include/smu.h: update mailbox register addresses
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Change subject: soc/intel/ehl/fsp_params: Fix double setting of 'PchPwrOptEnable'
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Patch Set 2:
(1 comment)
File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/84399/comment/a0ff9112_c3b61468?us… :
PS2, Line 327: params->PchPwrOptEnable = 0;
I would keep this line just to be independent from the default FSP setting.
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Change subject: mb/google/nissa/var/riven: enable WIFI SAR
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Patch Set 5:
(2 comments)
File src/mainboard/google/brya/variants/riven/variant.c:
https://review.coreboot.org/c/coreboot/+/84339/comment/269dad53_842c36da?us… :
PS5, Line 11: uint64_t
why uint64_t and not uint32_t?
https://review.coreboot.org/c/coreboot/+/84339/comment/a98e20f6_f65f57c1?us… :
PS5, Line 12: uint64_t
same
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