Attention is currently required from: Ashish Kumar Mishra.
Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/84397?usp=email )
Change subject: mb/google/brox: Remove Platform(PSys) related implementation
......................................................................
Patch Set 3:
(2 comments)
File src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/84397/comment/b711da87_92301305?us… :
PS3, Line 58: struct psys_config {
> Please update this struct reference in other brox variants, as well. Such as variants/jubilant. […]
psys_config and psys_pl2 power are not used in any Brox variant
https://review.coreboot.org/c/coreboot/+/84397/comment/f62acf10_e2b513df?us… :
PS3, Line 82: void variant_update_psys_power_limits(const struct cpu_power_limits *limits,
> Please update this function call reference in other brox variants, as well. […]
https://review.coreboot.org/c/coreboot/+/84219 - this function is not called in Jubilant .The patch is already merged
--
To view, visit https://review.coreboot.org/c/coreboot/+/84397?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I6c0e9561367b5846b00be27012f002dd7c299414
Gerrit-Change-Number: 84397
Gerrit-PatchSet: 3
Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-Comment-Date: Tue, 17 Sep 2024 12:23:19 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Attention is currently required from: Sowmya Aralguppe.
Ashish Kumar Mishra has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/84397?usp=email )
Change subject: mb/google/brox: Remove Platform(PSys) related implementation
......................................................................
Patch Set 3:
(3 comments)
Patchset:
PS3:
This commit will break other brox variant builds.
File src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/84397/comment/830a6056_e6d43d93?us… :
PS3, Line 58: struct psys_config {
Please update this struct reference in other brox variants, as well. Such as variants/jubilant. They are using same header.
https://review.coreboot.org/c/coreboot/+/84397/comment/65f1a1af_5fa72557?us… :
PS3, Line 82: void variant_update_psys_power_limits(const struct cpu_power_limits *limits,
Please update this function call reference in other brox variants, as well. Such as variants/jubilant. They are using same header from baseboard.
--
To view, visit https://review.coreboot.org/c/coreboot/+/84397?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I6c0e9561367b5846b00be27012f002dd7c299414
Gerrit-Change-Number: 84397
Gerrit-PatchSet: 3
Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
Gerrit-Comment-Date: Tue, 17 Sep 2024 11:48:06 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Attention is currently required from: Mario Scheithauer, Paul Menzel, Uwe Poeche.
Werner Zeh has posted comments on this change by Mario Scheithauer. ( https://review.coreboot.org/c/coreboot/+/84391?usp=email )
Change subject: mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl5}: Enable real-time tuning in FSP
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84391/comment/932794fe_ffc52fdc?us… :
PS1, Line 11: improves performance in the real-time environment for these mainboards.
> Hi Paul, […]
I set this comment to resolved so that this easy patch can go in.
--
To view, visit https://review.coreboot.org/c/coreboot/+/84391?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I04859b2f32bc11344b0620925f2414e7a6df625e
Gerrit-Change-Number: 84391
Gerrit-PatchSet: 2
Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com>
Gerrit-Comment-Date: Tue, 17 Sep 2024 11:07:56 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: Yes
Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>
Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84398?usp=email )
Change subject: soc/intel: Move CSE update ELOG to cse_lite.c
......................................................................
soc/intel: Move CSE update ELOG to cse_lite.c
The ELOG for CSE updates was being added in fsp_params.c, but the
actual update happens in cse_lite.c. This commit moves the ELOG to
cse_lite.c to more accurately reflect where the event is happening.
This also removes the need for a sol_type variable in
meteorlake/romstage/fsp_params.c.
It also helps to avoid redundant ELOG event entry while performing
CSE update (due to CSE RO to RW switch dependency).
BUG=b:361253028 (Multiple CSE sync elog prints for Nissa/Trulo)
TEST=Able to see only one instance of ELOG while performimg CSE sync.
w/o this patch:
elogtool list
0 | Log area cleared | 4088
1 | Kernel Event | Clean Shutdown
2 | Early Sign of Life | MRC Early SOL Screen Shown
3 | Early Sign of Life | CSE Sync Early SOL Screen Shown
4 | System boot | 29
5 | Memory Cache Update | Normal | Success
6 | Early Sign of Life | CSE Sync Early SOL Screen Shown
w/ this patch:
elogtool list
0 | Log area cleared | 4088
1 | Early Sign of Life | MRC Early SOL Screen Shown
2 | Memory Cache Update | Normal | Success
3 | System boot | 30
4 | Memory Cache Update | Normal | Success
5 | Early Sign of Life | CSE Sync Early SOL Screen Shown
Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/meteorlake/romstage/fsp_params.c
3 files changed, 3 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84398/1
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index d4608ee..969e15f 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -445,8 +445,6 @@
name = "CSE update";
esol_required = true;
}
-
- elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
}
if (esol_required)
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 8f59724..a7389f8 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -835,6 +835,7 @@
return CB_ERR;
printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n");
+ elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
return CB_SUCCESS;
}
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 84e665d..917503e 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -447,19 +447,16 @@
void *vbt;
size_t vbt_size;
uint32_t vga_init_control = 0;
- uint8_t sol_type;
/* Memory training. */
if (!arch_upd->NvsBufferPtr) {
vga_init_control = VGA_INIT_CONTROL_ENABLE |
VGA_INIT_CONTROL_TEAR_DOWN;
- sol_type = ELOG_FW_EARLY_SOL_MRC;
+ elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);
}
- if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) {
+ if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required())
vga_init_control = VGA_INIT_CONTROL_ENABLE;
- sol_type = ELOG_FW_EARLY_SOL_CSE_SYNC;
- }
if (!vga_init_control)
return;
@@ -478,7 +475,6 @@
}
printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n");
- elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, sol_type);
m_cfg->VgaInitControl = vga_init_control;
m_cfg->VbtPtr = (efi_uintn_t)vbt;
--
To view, visit https://review.coreboot.org/c/coreboot/+/84398?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62
Gerrit-Change-Number: 84398
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Attention is currently required from: Nicholas Sudsgaard.
Michał Żygowski has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/84396?usp=email )
Change subject: mb/msi/ms7e06: Correct number of jacks in hda_verb.c
......................................................................
Patch Set 1: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/84396?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I5cf34d8c4e27835d126eb66f2015d2e9d93b700f
Gerrit-Change-Number: 84396
Gerrit-PatchSet: 1
Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
Gerrit-Comment-Date: Tue, 17 Sep 2024 09:51:21 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes