Attention is currently required from: Paul Menzel, Uwe Poeche, Werner Zeh.
Mario Scheithauer has posted comments on this change by Mario Scheithauer. ( https://review.coreboot.org/c/coreboot/+/84391?usp=email )
Change subject: mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl5}: Enable real-time tuning in FSP
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84391/comment/f32337c0_e7eb1a05?us… :
PS1, Line 7: mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl5}: Enable real-time tuning
> … in FSP
Done
https://review.coreboot.org/c/coreboot/+/84391/comment/bd1ee3de_e8012551?us… :
PS1, Line 11: improves performance in the real-time environment for these mainboards.
> We use our self-made Linux system and our real-time automation software for the test. […]
Hi Paul,
Is this answer sufficient for you?
--
To view, visit https://review.coreboot.org/c/coreboot/+/84391?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I04859b2f32bc11344b0620925f2414e7a6df625e
Gerrit-Change-Number: 84391
Gerrit-PatchSet: 2
Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com>
Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-Comment-Date: Tue, 17 Sep 2024 04:39:52 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>
Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84368?usp=email )
Change subject: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"
......................................................................
Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"
This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309.
This workaround is not valid with the latest Intel PRQ silicon,
so I'm dropping it now. Additionally, able to boot to ChromeOS without
any hang, and I also ran an S0ix cycle without any failures.
BUG=b:244082753
TEST=Able to boot google/rex0 to CrOS.
Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84368
Reviewed-by: Jakub Czapiga <czapiga(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/meteorlake/acpi/tcss.asl
1 file changed, 1 insertion(+), 7 deletions(-)
Approvals:
build bot (Jenkins): Verified
Jakub Czapiga: Looks good to me, approved
diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl
index dbe76f2..24d28f3 100644
--- a/src/soc/intel/meteorlake/acpi/tcss.asl
+++ b/src/soc/intel/meteorlake/acpi/tcss.asl
@@ -602,13 +602,7 @@
}
/* Request IOM for D3 cold entry sequence. */
- /*
- * FIXME: Remove this workaround after resolving b/244082753
- *
- * Document #742990: TCCold exit flow may not complete when processor at package
- * C0. The implication is that the system may hang.
- */
- // TD3C = 1
+ TD3C = 1
}
PowerResource (D3C, 5, 0)
--
To view, visit https://review.coreboot.org/c/coreboot/+/84368?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e
Gerrit-Change-Number: 84368
Gerrit-PatchSet: 2
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com>
Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Tarun <tstuli(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Attention is currently required from: Dinesh Gehlot.
Subrata Banik has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/84120?usp=email )
Change subject: vc/google/chromeos: Skip boot info logging if cse sync at payload
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Apologies for missing this, I lost track of some emails in the last few weeks. But honestly, I'm still not convinced this is the right move. We have always had additional resets in depthcharge as well (e.g. due to EC sync or TCPC sync). We picked the end of ramstage for this because it was the most convenient point to implement it (it already has an elog driver that is always used on all platforms anyway), not because it's a huge issue to occasionally log this twice. Depthcharge does not normally write to elog on every boot, so by adding this you are adding the overhead of linking the elog code and initializing the driver (reading the area from flash) a second time to your critical boot path.
>
> But my main concern here is that you are making something more complicated that doesn't deserve to be that complicated. Introducing such a difference between platforms is always an ongoing maintenance burden, even if you were to move the code to commonlib. People will always have to think about where and how exactly the logging works for each particular platform, and may get confused because it works different on some than on others. There is value in keeping things simple.
The EC and PD resets are rare occurrences that we often don't encounter, so we can assume that 98% of the time during boot, we don't see redundant FW boot information logs. As a result, the test case was never adjusted to account for such edge cases. With CSE sync moving to depthcharge (planned for PTL), we'll encounter this issue frequently, as we'll see redundant FW boot information due to CSE changing the slot from RO to RW. Therefore, the probability of the test failing is higher than before, unless the test script is modified to account for the additional reboots.
The complexity arises from the fact that we're migrating things from coreboot to depthcharge, which results in duplicate code across (to optimize SPI flash usage). Ideally, I'd like to see us avoid redundant code in DC and instead pass everything as commonlib via libpayload to reduce duplicate work.
--
To view, visit https://review.coreboot.org/c/coreboot/+/84120?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ia29ec350facc6850c04bb988027ecb146e648a50
Gerrit-Change-Number: 84120
Gerrit-PatchSet: 3
Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Julius Werner <jwerner(a)chromium.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Comment-Date: Tue, 17 Sep 2024 04:36:57 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com>
Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>
Attention is currently required from: Dinesh Gehlot, Eric Lai, Ivan Chen, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Shou-Chieh Hsu, YH Lin.
Subrata Banik has posted comments on this change by YH Lin. ( https://review.coreboot.org/c/coreboot/+/84393?usp=email )
Change subject: nissa/riven: add the binding to the SAR tables
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/84393/comment/4c8f6501_07312991?us… :
PS2, Line 485: select CHROMEOS_WIFI_SAR if CHROMEOS
if you could follow the alphabetic order ?
--
To view, visit https://review.coreboot.org/c/coreboot/+/84393?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I3061364ab335d6a10738eb858404cb834a770d2d
Gerrit-Change-Number: 84393
Gerrit-PatchSet: 2
Gerrit-Owner: YH Lin <yueherngl(a)google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com>
Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com>
Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Jayvik Desai <jayvik(a)google.com>
Gerrit-Attention: Eric Lai <ericllai(a)google.com>
Gerrit-Attention: YH Lin <yueherngl(a)google.com>
Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com>
Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Attention: Ivan Chen <yulunchen(a)google.com>
Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com>
Gerrit-Comment-Date: Tue, 17 Sep 2024 04:14:45 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Matt DeVillier, Nick Vaccaro, Rishika Raj.
Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84365?usp=email )
Change subject: soc/intel/alderlake: Enable CRASHLOG for Chrome OS
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/84365/comment/7ade4fb6_436fa57d?us… :
PS1, Line 87: MAINBOARD_HAS_CHROMEOS
> > Fair enough. But currently there is no mechanism to disable the feature via Kconfig, and it doesn't appear to have been tested for the non-CHROMEOS use case.
>
>
> I have guarded `MAINBOARD_HAS_CHROMEOS` to ensure atleast on ChromeOS devices, we have enabled and tested this feature started with ADL. Intel recently fixed some issues over Crashlog enablement in ADL as well.
>
> This code will ensure crashlog config is only enabled for devices with CrOS.
@Matt, please let me know your thoughts here. I can resolve this comment based on feedback
--
To view, visit https://review.coreboot.org/c/coreboot/+/84365?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ia23ef1cbebdba9a3b724204eb25ee788afa3e8fd
Gerrit-Change-Number: 84365
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Jayvik Desai <jayvik(a)google.com>
Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com>
Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Comment-Date: Tue, 17 Sep 2024 03:30:33 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>
Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84396?usp=email )
Change subject: mb/msi/ms7e06: Correct number of jacks in hda_verb.c
......................................................................
mb/msi/ms7e06: Correct number of jacks in hda_verb.c
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I5cf34d8c4e27835d126eb66f2015d2e9d93b700f
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M src/mainboard/msi/ms7e06/hda_verb.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/84396/1
diff --git a/src/mainboard/msi/ms7e06/hda_verb.c b/src/mainboard/msi/ms7e06/hda_verb.c
index 51f9a50..96578fa 100644
--- a/src/mainboard/msi/ms7e06/hda_verb.c
+++ b/src/mainboard/msi/ms7e06/hda_verb.c
@@ -26,7 +26,7 @@
/* Alderlake HDMI */
0x80862818, /* Vendor ID */
0x80860101, /* Subsystem ID */
- 2, /* Number of entries */
+ 10, /* Number of entries */
AZALIA_SUBVENDOR(2, 0x80860101),
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
AZALIA_PIN_CFG(2, 0x06, 0x18560010),
--
To view, visit https://review.coreboot.org/c/coreboot/+/84396?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I5cf34d8c4e27835d126eb66f2015d2e9d93b700f
Gerrit-Change-Number: 84396
Gerrit-PatchSet: 1
Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
Nicholas Sudsgaard has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84395?usp=email )
Change subject: mb/samsung/lumpy: Correct number of jacks in hda_verb.c
......................................................................
mb/samsung/lumpy: Correct number of jacks in hda_verb.c
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I3a40e6229419ee7d1a238916ee6d49cf9314f6ab
Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>
---
M src/mainboard/samsung/lumpy/hda_verb.c
1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/84395/1
diff --git a/src/mainboard/samsung/lumpy/hda_verb.c b/src/mainboard/samsung/lumpy/hda_verb.c
index d18d8d2..a2b60bf 100644
--- a/src/mainboard/samsung/lumpy/hda_verb.c
+++ b/src/mainboard/samsung/lumpy/hda_verb.c
@@ -6,12 +6,15 @@
/* coreboot specific header */
0x10134210, // Codec Vendor / Device ID: Cirrus Logic CS4210
0x152D0924, // Subsystem ID
- 0x00000007, // Number of jacks
+ 0x00000008, // Number of jacks
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x152D0924 */
AZALIA_SUBVENDOR(0, 0x152D0924),
0x00170500,
+ 0x00170500,
+ 0x00170500,
+ 0x00170500,
/* Pin Widget Verb Table */
--
To view, visit https://review.coreboot.org/c/coreboot/+/84395?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email
Gerrit-MessageType: newchange
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I3a40e6229419ee7d1a238916ee6d49cf9314f6ab
Gerrit-Change-Number: 84395
Gerrit-PatchSet: 1
Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com>