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Change subject: soc/amd/glinda/chipset.cb: Update for glinda
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
the devicetrees for birman and birman plus with glinda soc also need to be updated to match these changes; haven't checked all the details, but the xhci_0 controller is now on a different bus in the chipset devicetree and the mainboard devicetree
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Change subject: soc/intel/xeon_sp: Handle GPIO SMIs
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 125:
(13 comments)
File src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/bd8c7d55_cdbca84f?us… :
PS125, Line 4: #define B_ICLK_PCR_FREQUENCY 0x1
> Please add a TODO for pending ICLK register details in EDS and/or equivalent
This is covered by task 17 IMGCLKOUT[n]: https://partnerissuetracker.corp.google.com/issues/357011633#comment23
File src/soc/intel/pantherlake/acpi/tcss.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/5f84732a_3b9509a4?us… :
PS125, Line 405: , 2,
> why we need this ?
removed.
https://review.coreboot.org/c/coreboot/+/83772/comment/fd73e459_bdc822b4?us… :
PS125, Line 608: /*
: * FIXME: Remove this workaround after resolving b/244082753
: *
: * Document #742990: TCCold exit flow may not complete when processor at package
: * C0. The implication is that the system may hang.
: */
> remove stale comments
Done
File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/e5945254_a4ea7008?us… :
PS125, Line 39: LNRE, 1,
> please add a description for this bit-field
Done
https://review.coreboot.org/c/coreboot/+/83772/comment/227bc1e0_6a736a75?us… :
PS125, Line 43: LSOE, 1,
: LNSE, 1,
> same
This is covered by task 17 for the register info https://partnerissuetracker.corp.google.com/issues/357011633#comment25https://review.coreboot.org/c/coreboot/+/83772/comment/125cc9cd_22082276?us… :
PS125, Line 49: 0x5BC
> 0x5bc
Done
https://review.coreboot.org/c/coreboot/+/83772/comment/d6bf07a9_be99ecb1?us… :
PS125, Line 53: 0xBA8
> in smaller case
Done
https://review.coreboot.org/c/coreboot/+/83772/comment/a8df05da_b292d2d1?us… :
PS125, Line 57: 0xBB2
> same
Done
https://review.coreboot.org/c/coreboot/+/83772/comment/8675cc1e_11bd5d75?us… :
PS125, Line 65: 0xDC
> same
this is not correct value. also change the for the macros to use lower cases.
https://review.coreboot.org/c/coreboot/+/83772/comment/5773b37e_c94d4018?us… :
PS125, Line 212: }
> please allow one empty line between 212 and 213
Done
File src/soc/intel/pantherlake/acpi/tcss_xhci.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/8a182540_cbfd79a0?us… :
PS125, Line 37: /* D3COLD_SUPPORT */
> nit: […]
Done
https://review.coreboot.org/c/coreboot/+/83772/comment/f797575c_0c44d7ca?us… :
PS125, Line 56: // D3COLD_SUPPORT
> same
Done
File src/soc/intel/pantherlake/acpi/xhci.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/d0e4cda9_364b9a91?us… :
PS125, Line 29: Pantherlake
> please remove this entire line, we are inside PTL soc
Done
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Cliff Huang has uploaded a new patch set (#126) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake-up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
4. PTL replaces DMI3 with SAF to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE guard check is added in northbridge.asl
5. include GPIO ASL that supports new pinctrl schema.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
A src/soc/intel/pantherlake/acpi/gpio.asl
A src/soc/intel/pantherlake/acpi/hda.asl
A src/soc/intel/pantherlake/acpi/pcie.asl
A src/soc/intel/pantherlake/acpi/serialio.asl
A src/soc/intel/pantherlake/acpi/southbridge.asl
A src/soc/intel/pantherlake/acpi/tcss.asl
A src/soc/intel/pantherlake/acpi/tcss_dma.asl
A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
A src/soc/intel/pantherlake/acpi/tcss_xhci.asl
A src/soc/intel/pantherlake/acpi/xhci.asl
12 files changed, 2,932 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/126
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Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84297?usp=email
to look at the new patch set (#10).
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Change subject: soc/intel/ptl: Define GPE1 macros and register fields
......................................................................
soc/intel/ptl: Define GPE1 macros and register fields
New GPE1 bits are introduced in PTL for internal devices, incuding
PME_B0, hot plug, and PCIe events.
defines for GPE number for additional STD GPE0 in PTL
defines for GPE number for GPE1
defines for GPE1 bits
NOTE: All GEP1 bits are STD (Intel's Standard) GPE bits.
BUG=362310295
TEST=This cannot be tested directly.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836
---
M src/soc/intel/pantherlake/include/soc/gpe.h
M src/soc/intel/pantherlake/include/soc/pm.h
2 files changed, 369 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84297/10
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Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )
Change subject: soc/intel/ptl: Add GPE1 defines
......................................................................
Patch Set 9:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84297/comment/e9e1c6e0_84be7ad0?us… :
PS9, Line 7: Add GPE1 defines
> Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/84297/comment/70914e11_ada21f20?us… :
PS9, Line 9: defines for GPE number for additional STD GPE0 in PTL
: defines for GPE number for GPE1
: defines for GPE1 bits
> Please elaborate more before this is submitted.
Done
https://review.coreboot.org/c/coreboot/+/84297/comment/6707ec2c_00cc2f5b?us… :
PS9, Line 12: STD
> STD GPE have been used for Intel's GPE bits in this case. I can add more here.
Done
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Change subject: soc/intel/ptl: Add GPE1 defines
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/pantherlake/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/84297/comment/ce2401db_3c952930?us… :
PS9, Line 133: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)
> Subrata, we will hit the GPE1_* marco redefined build error if CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is not set in PTL. I recall I brought up this issue.
yes, I remember. In such case we should introduce `SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1` and `SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1`
PTL SoC to select SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 and mainboard can select SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1 if they wish to use it.
this way, you don't run into any issue (macro definition of is still inside !SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1, therefore, for PTL it will only include one/proper register definition)
```
fadt->gpe1_blk = 0;
if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) {
fadt->gpe1_blk = pmbase + GPE1_STS(0);
fadt->gpe1_blk_len = 2 * GPE1_REG_MAX * sizeof(uint32_t);
/*
* NOTE: gpe1 is after gpe0, which has _STS and _EN register sets.
* gpe1_base is the starting bit offset for GPE1.
*/
fadt->gpe1_base = fadt->gpe0_blk_len / 2 * 8;
}
```
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Change subject: soc/intel/ptl: Add GPE1 defines
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/pantherlake/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/84297/comment/4b26953b_92415e34?us… :
PS9, Line 133: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)
> Sure. Let me a new CL for this and remove this CPP.
Subrata, we will hit the GPE1_* marco redefined build error if CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is not set in PTL. I recall I brought up this issue.
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Change subject: soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84392/comment/419ad8db_10817664?us… :
PS1, Line 12: 362310295
b:362310295
https://review.coreboot.org/c/coreboot/+/84392/comment/cd24942f_75cb65ce?us… :
PS1, Line 13: , boot to
boot google/fatcat or intel/ptlrvp to CrOS
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