coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Handle GPIO SMIs
by Alicja Michalska (Code Review) 16 Sep '24

16 Sep '24

Attention is currently required from: Alicja Michalska, Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84301?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Christian Walter Change subject: soc/intel/xeon_sp: Handle GPIO SMIs ...................................................................... soc/intel/xeon_sp: Handle GPIO SMIs This patch implements GPIO_SMI_STS handler on Lewisburg. Change-Id: I906978d2bb2c5e055143aab656e40e06c24ace8d Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> --- M src/soc/intel/xeon_sp/lbg/Makefile.mk M src/soc/intel/xeon_sp/smihandler.c 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/84301/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84301?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I906978d2bb2c5e055143aab656e40e06c24ace8d Gerrit-Change-Number: 84301 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Handle GPIO SMIs
by Christian Walter (Code Review) 16 Sep '24

16 Sep '24

Attention is currently required from: Alicja Michalska, Arthur Heymans, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Christian Walter has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/84301?usp=email ) Change subject: soc/intel/xeon_sp: Handle GPIO SMIs ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: After fixing unstable builds.. :) -- To view, visit https://review.coreboot.org/c/coreboot/+/84301?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I906978d2bb2c5e055143aab656e40e06c24ace8d Gerrit-Change-Number: 84301 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 16 Sep 2024 20:15:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd/glinda/chipset.cb: Update for glinda
by Felix Held (Code Review) 16 Sep '24

16 Sep '24

Attention is currently required from: Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84376?usp=email ) Change subject: soc/amd/glinda/chipset.cb: Update for glinda ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > the devicetrees for birman and birman plus with glinda soc also need to be updated to match these ch […] ah, that's also why the build fails -- To view, visit https://review.coreboot.org/c/coreboot/+/84376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1138f27bfd47f6fa70a0c2afcc65a5553a609d57 Gerrit-Change-Number: 84376 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 16 Sep 2024 20:14:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd/glinda/chipset.cb: Update for glinda
by Felix Held (Code Review) 16 Sep '24

16 Sep '24

Attention is currently required from: Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84376?usp=email ) Change subject: soc/amd/glinda/chipset.cb: Update for glinda ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: the devicetrees for birman and birman plus with glinda soc also need to be updated to match these changes; haven't checked all the details, but the xhci_0 controller is now on a different bus in the chipset devicetree and the mainboard devicetree -- To view, visit https://review.coreboot.org/c/coreboot/+/84376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1138f27bfd47f6fa70a0c2afcc65a5553a609d57 Gerrit-Change-Number: 84376 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 16 Sep 2024 20:13:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Handle GPIO SMIs
by Christian Walter (Code Review) 16 Sep '24

16 Sep '24

Attention is currently required from: Alicja Michalska, Arthur Heymans, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Christian Walter has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/84301?usp=email ) Change subject: soc/intel/xeon_sp: Handle GPIO SMIs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84301?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I906978d2bb2c5e055143aab656e40e06c24ace8d Gerrit-Change-Number: 84301 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 16 Sep 2024 20:08:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Cliff Huang (Code Review) 16 Sep '24

16 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... Patch Set 125: (13 comments) File src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/bd8c7d55_cdbca84f?us… : PS125, Line 4: #define B_ICLK_PCR_FREQUENCY 0x1 > Please add a TODO for pending ICLK register details in EDS and/or equivalent This is covered by task 17 IMGCLKOUT[n]: https://partnerissuetracker.corp.google.com/issues/357011633#comment23 File src/soc/intel/pantherlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/5f84732a_3b9509a4?us… : PS125, Line 405: , 2, > why we need this ? removed. https://review.coreboot.org/c/coreboot/+/83772/comment/fd73e459_bdc822b4?us… : PS125, Line 608: /* : * FIXME: Remove this workaround after resolving b/244082753 : * : * Document #742990: TCCold exit flow may not complete when processor at package : * C0. The implication is that the system may hang. : */ > remove stale comments Done File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/e5945254_a4ea7008?us… : PS125, Line 39: LNRE, 1, > please add a description for this bit-field Done https://review.coreboot.org/c/coreboot/+/83772/comment/227bc1e0_6a736a75?us… : PS125, Line 43: LSOE, 1, : LNSE, 1, > same This is covered by task 17 for the register info https://partnerissuetracker.corp.google.com/issues/357011633#comment25 https://review.coreboot.org/c/coreboot/+/83772/comment/125cc9cd_22082276?us… : PS125, Line 49: 0x5BC > 0x5bc Done https://review.coreboot.org/c/coreboot/+/83772/comment/d6bf07a9_be99ecb1?us… : PS125, Line 53: 0xBA8 > in smaller case Done https://review.coreboot.org/c/coreboot/+/83772/comment/a8df05da_b292d2d1?us… : PS125, Line 57: 0xBB2 > same Done https://review.coreboot.org/c/coreboot/+/83772/comment/8675cc1e_11bd5d75?us… : PS125, Line 65: 0xDC > same this is not correct value. also change the for the macros to use lower cases. https://review.coreboot.org/c/coreboot/+/83772/comment/5773b37e_c94d4018?us… : PS125, Line 212: } > please allow one empty line between 212 and 213 Done File src/soc/intel/pantherlake/acpi/tcss_xhci.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/8a182540_cbfd79a0?us… : PS125, Line 37: /* D3COLD_SUPPORT */ > nit: […] Done https://review.coreboot.org/c/coreboot/+/83772/comment/f797575c_0c44d7ca?us… : PS125, Line 56: // D3COLD_SUPPORT > same Done File src/soc/intel/pantherlake/acpi/xhci.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/d0e4cda9_364b9a91?us… : PS125, Line 29: Pantherlake > please remove this entire line, we are inside PTL soc Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 125 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 16 Sep 2024 19:35:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Cliff Huang (Code Review) 16 Sep '24

16 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Cliff Huang has uploaded a new patch set (#126) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... soc/intel/ptl: Add SoC ACPI directory for Panther Lake List of changes: 1. Select common ACPI Kconfig to include common ACPI code block from IA-common code 2. Select ACPI Kconfig support for wake-up from sleep states. 3. Add SoC ASL code for SoC IPs like IPU, HDA etc. 4. PTL replaces DMI3 with SAF to ensure common/block/acpi/acpi/northbridge.asl binding with PTL change, #if DMI_BASE_SIZE guard check is added in northbridge.asl 5. include GPIO ASL that supports new pinctrl schema. BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl A src/soc/intel/pantherlake/acpi/gpio.asl A src/soc/intel/pantherlake/acpi/hda.asl A src/soc/intel/pantherlake/acpi/pcie.asl A src/soc/intel/pantherlake/acpi/serialio.asl A src/soc/intel/pantherlake/acpi/southbridge.asl A src/soc/intel/pantherlake/acpi/tcss.asl A src/soc/intel/pantherlake/acpi/tcss_dma.asl A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl A src/soc/intel/pantherlake/acpi/tcss_xhci.asl A src/soc/intel/pantherlake/acpi/xhci.asl 12 files changed, 2,932 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/126 -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 126 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: soc/intel/ptl: Define GPE1 macros and register fields
by Cliff Huang (Code Review) 16 Sep '24

16 Sep '24

Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84297?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Define GPE1 macros and register fields ...................................................................... soc/intel/ptl: Define GPE1 macros and register fields New GPE1 bits are introduced in PTL for internal devices, incuding PME_B0, hot plug, and PCIe events. defines for GPE number for additional STD GPE0 in PTL defines for GPE number for GPE1 defines for GPE1 bits NOTE: All GEP1 bits are STD (Intel's Standard) GPE bits. BUG=362310295 TEST=This cannot be tested directly. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 --- M src/soc/intel/pantherlake/include/soc/gpe.h M src/soc/intel/pantherlake/include/soc/pm.h 2 files changed, 369 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84297/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 Gerrit-Change-Number: 84297 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines
by Cliff Huang (Code Review) 16 Sep '24

16 Sep '24

Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email ) Change subject: soc/intel/ptl: Add GPE1 defines ...................................................................... Patch Set 9: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84297/comment/e9e1c6e0_84be7ad0?us… : PS9, Line 7: Add GPE1 defines > Maybe: […] Done https://review.coreboot.org/c/coreboot/+/84297/comment/70914e11_ada21f20?us… : PS9, Line 9: defines for GPE number for additional STD GPE0 in PTL : defines for GPE number for GPE1 : defines for GPE1 bits > Please elaborate more before this is submitted. Done https://review.coreboot.org/c/coreboot/+/84297/comment/6707ec2c_00cc2f5b?us… : PS9, Line 12: STD > STD GPE have been used for Intel's GPE bits in this case. I can add more here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 Gerrit-Change-Number: 84297 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 16 Sep 2024 19:02:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines
by Subrata Banik (Code Review) 16 Sep '24

16 Sep '24

Attention is currently required from: Cliff Huang, Kapil Porwal, Paul Menzel, Pranava Y N. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email ) Change subject: soc/intel/ptl: Add GPE1 defines ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/pantherlake/include/soc/pm.h: https://review.coreboot.org/c/coreboot/+/84297/comment/ce2401db_3c952930?us… : PS9, Line 133: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) > Subrata, we will hit the GPE1_* marco redefined build error if CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is not set in PTL. I recall I brought up this issue. yes, I remember. In such case we should introduce `SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1` and `SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1` PTL SoC to select SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 and mainboard can select SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1 if they wish to use it. this way, you don't run into any issue (macro definition of is still inside !SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1, therefore, for PTL it will only include one/proper register definition) ``` fadt->gpe1_blk = 0; if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) { fadt->gpe1_blk = pmbase + GPE1_STS(0); fadt->gpe1_blk_len = 2 * GPE1_REG_MAX * sizeof(uint32_t); /* * NOTE: gpe1 is after gpe0, which has _STS and _EN register sets. * gpe1_base is the starting bit offset for GPE1. */ fadt->gpe1_base = fadt->gpe0_blk_len / 2 * 8; } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 Gerrit-Change-Number: 84297 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 16 Sep 2024 18:53:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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coreboot-gerrit September 2024