coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mainboard/google/fatcat: Update SoC to Panther Lake
by Subrata Banik (Code Review) 25 Sep '24

25 Sep '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84537?usp=email ) Change subject: mainboard/google/fatcat: Update SoC to Panther Lake ...................................................................... mainboard/google/fatcat: Update SoC to Panther Lake This commit updates the fatcat mainboard to use the Panther Lake SoC instead of Meteor Lake. The changes include: - Selecting the `SOC_INTEL_PANTHERLAKE_U_H` config option. - Updating the `mainboard_update_soc_chip_config()` function to use the `soc_intel_pantherlake_config` struct. - Updating the devicetree to use the `soc/intel/pantherlake` chip. - Updating variant header files to reflect the SoC change. This update enables support for the Panther Lake SoC and its features on the fatcat mainboard. BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie0c6257dfb9dd1f627472ad220614f9b24c911ef Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84537 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/mainboard.c M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb M src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h 4 files changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 42a839c..960ab14 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -20,6 +20,7 @@ select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 select SOC_INTEL_CSE_SEND_EOP_ASYNC + select SOC_INTEL_PANTHERLAKE_U_H config BOARD_GOOGLE_BASEBOARD_FATCAT def_bool n @@ -28,7 +29,6 @@ select MAINBOARD_HAS_CHROMEOS select MEMORY_SOLDERDOWN select SOC_INTEL_IOE_DIE_SUPPORT - select SOC_INTEL_METEORLAKE_U_H select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 diff --git a/src/mainboard/google/fatcat/mainboard.c b/src/mainboard/google/fatcat/mainboard.c index 107ee8d..55b9e4c 100644 --- a/src/mainboard/google/fatcat/mainboard.c +++ b/src/mainboard/google/fatcat/mainboard.c @@ -16,12 +16,12 @@ /* default implementation does nothing */ } -void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *config) { variant_update_soc_chip_config(config); } -__weak void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +__weak void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) { /* default implementation does nothing */ } diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index 9f4f3455..73b99db 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -1,3 +1,3 @@ -chip soc/intel/meteorlake +chip soc/intel/pantherlake device domain 0 on end end diff --git a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h index 8a97d00..27fd8b7 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h @@ -22,7 +22,7 @@ void variant_get_spd_info(struct mem_spd *spd_info); int variant_memory_sku(void); bool variant_is_half_populated(void); -void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config); +void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config); /* Get soc power limit config struct for current CPU sku */ struct soc_power_limits_config *variant_get_soc_power_limit_config(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/84537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie0c6257dfb9dd1f627472ad220614f9b24c911ef Gerrit-Change-Number: 84537 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mainboard/google/fatcat: Remove unused virtual GPIOs
by Subrata Banik (Code Review) 25 Sep '24

25 Sep '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84536?usp=email ) Change subject: mainboard/google/fatcat: Remove unused virtual GPIOs ...................................................................... mainboard/google/fatcat: Remove unused virtual GPIOs This commit removes the virtual GPIOs for recovery and write protection from the fatcat variant. These GPIOs are not utilized on the fatcat platform, and their removal simplifies the GPIO configuration and improves code readability. The `CROS_GPIO_DEVICE_NAME` macro is no longer applicable for Panther Lake SoCs. Future changes will introduce a suitable GPIO device name that meets the requirements of Panther Lake. BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I492fec28637edb2f84e9290b28dabce3f23aa867 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84536 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/variants/fatcat/gpio.c 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index ebb0120..c966ab7 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -46,8 +46,6 @@ } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; DECLARE_CROS_GPIOS(cros_gpios); -- To view, visit https://review.coreboot.org/c/coreboot/+/84536?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I492fec28637edb2f84e9290b28dabce3f23aa867 Gerrit-Change-Number: 84536 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brya: Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for vell
by Subrata Banik (Code Review) 25 Sep '24

25 Sep '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84525?usp=email ) Change subject: mb/google/brya: Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for vell ...................................................................... mb/google/brya: Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for vell Enable the SOC_INTEL_COMMON_BASECODE_RAMTOP Kconfig option for the google/vell mainboard. This option ensures improving the boot time on google/vell by 40ms in an average. BUG=b:352330495 TEST=Able to reduced google/vell boot time by 40ms. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Iedfd346c62b1ac79796042dd3569d846007b8f10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84525 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index efe9b50..5088ade 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -583,6 +583,7 @@ select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_I2C_CS35L53 select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_BASECODE_RAMTOP select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_RAPTORLAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/84525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iedfd346c62b1ac79796042dd3569d846007b8f10 Gerrit-Change-Number: 84525 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/common/systemagent: Fixup systemagent address
by Name of user not set (Code Review) 25 Sep '24

25 Sep '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Paul Menzel. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent: Fixup systemagent address ...................................................................... Patch Set 19: (1 comment) Patchset: PS19: > It would still be a mess because you would have to specify how to handle the register value somehow, […] Ok, I will follow your suggestion. Actually there are actually other server platforms that is using the same system agent as Snow Ridge. May I add a server-specific system agent in the common code, or just leave them as SoC-specific code? -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 19 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 25 Sep 2024 02:11:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: util/cbfstool: Add Intel platform boot policy support
by Shuo Liu (Code Review) 25 Sep '24

25 Sep '24

Attention is currently required from: Alicja Michalska, Angel Pons, Arthur Heymans, Chen, Gang C, Jincheng Li, Paul Menzel. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84305?usp=email ) Change subject: util/cbfstool: Add Intel platform boot policy support ...................................................................... Patch Set 2: (1 comment) File util/cbfstool/fit.c: https://review.coreboot.org/c/coreboot/+/84305/comment/3349db0c_87a0839b?us… : PS2, Line 372: > Remove the spaces? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84305?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f9fc61341430b1a35a44d50b108dcfaf31cd11c Gerrit-Change-Number: 84305 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Wed, 25 Sep 2024 01:40:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: util/cbfstool: Add Intel platform boot policy support
by Shuo Liu (Code Review) 25 Sep '24

25 Sep '24

Attention is currently required from: Alicja Michalska, Angel Pons, Arthur Heymans, Chen, Gang C, Jincheng Li, Shuo Liu. Hello Alicja Michalska, Angel Pons, Arthur Heymans, Chen, Gang C, Jincheng Li, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84305?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/cbfstool: Add Intel platform boot policy support ...................................................................... util/cbfstool: Add Intel platform boot policy support Intel platform boot policy setting blob is linked into FIT table as an FIT4 entry. It is required for server executing CBnT and/or PFR without a PCH. Please refer to chapter 4.6 of the document in below link: https://www.intel.com/content/dam/www/public/us/en/documents/ guides/fit-bios-specification.pdf Tool usage: ./util/cbfstool/ifittool -f <binary> -a -n <cbfs name> -t 4 \ -r COREBOOT -s <max table size> Change-Id: I0f9fc61341430b1a35a44d50b108dcfaf31cd11c Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Li, Jincheng <jincheng.li(a)intel.com> --- M src/cpu/intel/fit/Kconfig M src/cpu/intel/fit/Makefile.mk M util/cbfstool/fit.c M util/cbfstool/fit.h 4 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/84305/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84305?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f9fc61341430b1a35a44d50b108dcfaf31cd11c Gerrit-Change-Number: 84305 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Report PCIe integrated end points under DRHD
by Shuo Liu (Code Review) 25 Sep '24

25 Sep '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84315?usp=email ) Change subject: soc/intel/xeon_sp: Report PCIe integrated end points under DRHD ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84315/comment/59c51ba8_931df69a?us… : PS1, Line 7: RCiEPs > What are RCiEPs? RCiEP is root complex integrated end points. I used PCIe integrated end points to be more straightforward. -- To view, visit https://review.coreboot.org/c/coreboot/+/84315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib015b002f2c077f50d48c046513504bdbd5b35aa Gerrit-Change-Number: 84315 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 25 Sep 2024 01:29:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Report PCIe integrated end points under DRHD
by Shuo Liu (Code Review) 25 Sep '24

25 Sep '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84315?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Report PCIe integrated end points under DRHD ...................................................................... soc/intel/xeon_sp: Report PCIe integrated end points under DRHD In case of a PCH-less platform, no DRHD_INCLUDE_PCI_ALL flags are used, all PCIe integrated end points should be explicitly listed under its specific DRHD. Change-Id: Ib015b002f2c077f50d48c046513504bdbd5b35aa Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/uncore_acpi.c 1 file changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/84315/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84315?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib015b002f2c077f50d48c046513504bdbd5b35aa Gerrit-Change-Number: 84315 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Remove INCLUDE_PCI_ALL bit for IBL platforms
by Shuo Liu (Code Review) 25 Sep '24

25 Sep '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84316?usp=email to look at the new patch set (#3). Change subject: soc/intel/xeon_sp: Remove INCLUDE_PCI_ALL bit for IBL platforms ...................................................................... soc/intel/xeon_sp: Remove INCLUDE_PCI_ALL bit for IBL platforms Change-Id: I0755143b21633d5fa8fe4a6eb93e4e6ff0301ab5 Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/uncore_acpi.c 1 file changed, 8 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/84316/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0755143b21633d5fa8fe4a6eb93e4e6ff0301ab5 Gerrit-Change-Number: 84316 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Remove INCLUDE_PCI_ALL bit for IBL platforms
by Shuo Liu (Code Review) 25 Sep '24

25 Sep '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84316?usp=email ) Change subject: soc/intel/xeon_sp: Remove INCLUDE_PCI_ALL bit for IBL platforms ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/xeon_sp/uncore_acpi.c: https://review.coreboot.org/c/coreboot/+/84316/comment/457051e7_8465595b?us… : PS1, Line 271: if (!CONFIG(SOC_INTEL_COMMON_IBL_BASE) && is_dev_on_domain0(iommu)) { : printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " : "Register Base Address: 0x%x\n", : DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); : current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, : pcie_seg, reg_base, vtd_probe_bar_size(iommu)); : } else { : printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " : "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); : current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base, : vtd_probe_bar_size(iommu)); : } > can we get rid of the if else statement and change the function input into a variable called flags? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0755143b21633d5fa8fe4a6eb93e4e6ff0301ab5 Gerrit-Change-Number: 84316 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 25 Sep 2024 01:17:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit September 2024