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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
soc/intel/common/block/pmc: Add GPE1 functions
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 flag.
- The existing static gpe functions has been renamed with gpe0.
- Add gpe1 functions.
BUG:362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 flag,
boot google/fatcat or intel/ptlrvp DUT, and check if GPE1 sts bits have
been printed during boot. Search for:
[DEBUG] GPE1 STD STS: <event string>
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 108 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/25
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I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
soc/intel/common/block/pmc: Add GPE1 functions
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 flag.
- The existing static gpe functions has been renamed with gpe0.
- Add gpe1 functions.
BUG:362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 flag,
boot google/fatcat or intel/ptlrvp DUT, and check if GPE1 sts bits have
been printed during boot. Search for:
[DEBUG] GPE1 STD STS: <event string>
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 110 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/24
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Change subject: mb/google/brya/var/trulo: Update ISH GPIO config for tablet mode switch
......................................................................
mb/google/brya/var/trulo: Update ISH GPIO config for tablet mode switch
This patch configures the GPIO pins for ISH to notify EC about the
tablet mode change in accordance with schematic_20240607.
BUG=b:347811875
TEST=Build and boot google/trulo. Placed the device in tabletmode & on EC console,"tabletmode" command shows "tablet mode".
Cq-Depend: chromium:5850328
Change-Id: Id22e397e46b522428ffdabe34a445ed7e4fb6fc5
Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com>
---
M src/mainboard/google/brya/variants/trulo/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/84351/4
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Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84392?usp=email )
Change subject: soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84392/comment/3cd1d859_647182e9?us… :
PS1, Line 12: 362310295
> b:362310295
Done
https://review.coreboot.org/c/coreboot/+/84392/comment/5e10f312_1314e623?us… :
PS1, Line 13: , boot to
> boot google/fatcat or intel/ptlrvp to CrOS
Done
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Sowmya Aralguppe has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/84397?usp=email )
Change subject: mb/google/brox: Remove Platform(PSys) related implementation
......................................................................
mb/google/brox: Remove Platform(PSys) related implementation
PSys provides enhanced thermal power management mechanisms and requires
Psys signal implementation in HW. This will increase the cost and also
impacts performance during the active state of the platform.Hence PSys
based power management is not an optimal solution for no/low battery
boot and implementation related to this is removed in this patch.
BUG=None
BRANCH=None
TEST=Build and boot on brox board
Change-Id: I6c0e9561367b5846b00be27012f002dd7c299414
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
2 files changed, 0 insertions(+), 107 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84397/3
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Change subject: soc/intel/xeon_sp: Handle GPIO SMIs
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84301/comment/7053d723_d922661d?us… :
PS2, Line 9: GPIO_SMI_STS
Why do you need to handle GPIO_SMIs? Why are they enabled when there are no mainboard_smi_gpi_handler() in any of the boards supporting Lewisburg.
Maybe your GPIO config is just wrong or copy&pasted from some other firmware?
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Change subject: mb/google/fatcat: Add Panther Lake SOC support
......................................................................
Patch Set 179: Code-Review-2
(2 comments)
Patchset:
PS179:
very difficult to review the code like this
I would suggest splitting this CL as below
1. Submit the minimum changes for fatcat to use PTL SoC and pass the build
2. Add Memory changes
3. Add GPIO changes
4. Add override tree changes
5. Add FW config changes
6. Add Verb table changes
File src/mainboard/google/fatcat/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/83419/comment/fc6e9442_28a694b2?us… :
PS179, Line 13: 0x20110725
this should be updated now ?
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Change subject: soc/intel/common/block/acpi/exclude DMI fixed memory range if no DMI
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Ping! can u please address this ?
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