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Change subject: nissa/riven: add the binding to the SAR tables
......................................................................
Abandoned
Use CB:84339 instead.
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Change subject: mb/google/nissa/var/riven: enable WIFI SAR
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
Patchset:
PS5:
> RF team teld us, maybe need six sar table. […]
In that case yeah this is the way to go. Thanks!
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Change subject: soc/intel/alderlake: Enable CRASHLOG for Chrome OS
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/84365/comment/c6db19a7_b3902624?us… :
PS1, Line 87: MAINBOARD_HAS_CHROMEOS
> I don't see any issues here with crashlog on ADL, only on JSL. I'm fine with moving the enablement from the board to the SoC though I'm not sure it needs guarding with MAINBOARD_HAS_CHROMEOS
I've locked down crashlog enablement with MAINBOARD_HAS_CHROMEOS config to limit the scope of validation. Not sure if all ADL consumers (non CrOS) have tested crashlog yet.
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Change subject: mb/siemens/{mc_ehl2,mc_ehl3,mc_ehl5}: Enable real-time tuning in FSP
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Patch Set 2: Code-Review+1
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Change subject: inteltool: improve support for Elkhart Lake
......................................................................
Patch Set 7:
(1 comment)
File util/inteltool/inteltool.h:
https://review.coreboot.org/c/coreboot/+/75214/comment/34f9ad9c_4235eb1f?us… :
PS7, Line 513:
i wonder why this empty line and the one a few lines below are added here; probably best to remove those two
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Change subject: soc/intel/alderlake: Enable CRASHLOG for Chrome OS
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/84365/comment/e98b55f3_28c95aab?us… :
PS1, Line 87: MAINBOARD_HAS_CHROMEOS
> > > Fair enough. […]
I don't see any issues here with crashlog on ADL, only on JSL. I'm fine with moving the enablement from the board to the SoC though I'm not sure it needs guarding with MAINBOARD_HAS_CHROMEOS
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Hello Lean Sheng Tan, Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84399?usp=email
to look at the new patch set (#2).
Change subject: soc/intel/ehl/fsp_params: Fix double setting of 'PchPwrOptEnable'
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soc/intel/ehl/fsp_params: Fix double setting of 'PchPwrOptEnable'
If real-time tuning was enabled, 'PchPwrOptEnable' was set two times.
This patch fixes the issue.
BUG=none
TEST=Enabled UPD debug output and checked 'PchPwrOptEnable' offset
Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/soc/intel/elkhartlake/fsp_params.c
1 file changed, 1 insertion(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/84399/2
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Change subject: mb/google/brox: Remove Platform(PSys) related implementation
......................................................................
Patch Set 3:
(2 comments)
File src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/84397/comment/b711da87_92301305?us… :
PS3, Line 58: struct psys_config {
> Please update this struct reference in other brox variants, as well. Such as variants/jubilant. […]
psys_config and psys_pl2 power are not used in any Brox variant
https://review.coreboot.org/c/coreboot/+/84397/comment/f62acf10_e2b513df?us… :
PS3, Line 82: void variant_update_psys_power_limits(const struct cpu_power_limits *limits,
> Please update this function call reference in other brox variants, as well. […]
https://review.coreboot.org/c/coreboot/+/84219 - this function is not called in Jubilant .The patch is already merged
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