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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 25:
(7 comments)
Patchset:
PS25:
> can you please add SoC override as well?
will add separate CL for override functions for PTL soc.
Commit Message:
https://review.coreboot.org/c/coreboot/+/84104/comment/7a652037_4ef95ba6?us… :
PS11, Line 15: and check if GPE1 sts bits have been printed during boot.
> Paste the new debug messages?
Done
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/0b1b7226_370f596f?us… :
PS24, Line 254: return
> ```/* nop */```
Done
https://review.coreboot.org/c/coreboot/+/84104/comment/5254a62d_bfa04902?us… :
PS24, Line 259: return
> ```/* nop */```
Done
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/84104/comment/e972bab0_57a1d1b7?us… :
PS11, Line 68: /* SoC overrides for GPE1 when SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is enabled */
: __weak const char *const *soc_std_gpe1_sts_array(int idx, size_t *a)
: {
: return NULL;
: }
:
: /* disable the corresponding GPE1 bits based on standard GPE0 bits */
: __weak void soc_pmc_disable_std_gpe1(uint32_t gpe0_mask)
: {
: }
:
: /* enable the corresponding GPE1 bits based on standard GPE0 bits */
: __weak void soc_pmc_enable_std_gpe1(uint32_t gpe0_mask)
: {
: }
> oh, that SOC_INTEL_COMMON_BLOCK_ should have been SOC_INTEL_COMMON_BLOCK_PMC; not sure where those f […]
Felix, build issue fixed?
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/84104/comment/33aad979_164e9356?us… :
PS24, Line 421: print_std_gpe1_sts(gpe1_sts);
> shouldn't we print first and then reset ?
Similar to GPE0 in line 415, the STS values are read and saved prior to the reset. print function merely print the previous stored STS values.
https://review.coreboot.org/c/coreboot/+/84104/comment/1342bb6c_17dcb04b?us… :
PS24, Line 522:
> one tab less?
Done
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Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins),
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
soc/intel/common/block/pmc: Add GPE1 functions
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 flag.
- The existing static gpe functions has been renamed with gpe0.
- Add gpe1 functions.
BUG:362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 flag,
boot google/fatcat or intel/ptlrvp DUT, and check if GPE1 sts bits have
been printed during boot. Search for:
[DEBUG] GPE1 STD STS: <event string>
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 108 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/26
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Change subject: mb/google/nissa/var/riven: enable WIFI SAR
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/brya/variants/riven/variant.c:
https://review.coreboot.org/c/coreboot/+/84339/comment/9989ec30_1cc0d28d?us… :
PS5, Line 15: if (sar_id == UNDEFINED_FW_CONFIG) {
> you probably need to check both?
Done. Thanks.
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Change subject: soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
......................................................................
soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to add GPE1 block
rather than checking if GPE1_STS(0) is '0'.
BUG:362310295
TEST=with the flag, boot google/fatcat or intel/ptlrvp to OS and check
that FADT table includes GPE1. FADT should have:
GPE1 Block Address : 00001810
GPE1 Block Length : 18
GPE1 Base Offset : 80
Without the flag, boot to OS and check that FADT table does not include
GPE1. FADT should have:
GPE1 Block Address : 0
GPE1 Block Length : 0
GPE1 Base Offset : 0
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7
---
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/acpi.c
2 files changed, 28 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/84392/4
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I'd like you to reexamine a change. Please visit
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Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
......................................................................
soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to add GPE1 block
rather than checking if GPE1_STS(0) is '0'.
BUG:362310295
TEST=with the flag, boot google/fatcat or intel/ptlrvp to OS and check
that FADT table includes GPE1. FADT should have:
GPE1 Block Address : 00001810
GPE1 Block Length : 18
GPE1 Base Offset : 80
Without the flag, boot to OS and check that FADT table does not include
GPE1. FADT should have:
GPE1 Block Address : 0
GPE1 Block Length : 0
GPE1 Base Offset : 0
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7
---
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/acpi.c
2 files changed, 27 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/84392/3
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Change subject: soc/qclib_common.h: Fix Wunterminated-string-initialization error on qclib_cb_if_table
......................................................................
Patch Set 5: Code-Review-2
(1 comment)
Patchset:
PS5:
...okay, I'm not gonna -2 each of these individually. Data structures have meaning, you can't just go into a ton of code you're not familiar with and start changing sizes willy-nilly. These are used to interoperate with other code that expects an exact format, and they will break if you randomly shift things around.
Maybe forget about this particular warning, or use pragmas to disable it around code where it is more harmful than helpful.
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Change subject: commonlib/coreboot_tables.h: Increase GPIO_MAX_NAME_LENGTH to 17 for backlight enable
......................................................................
Patch Set 4: Code-Review-2
(1 comment)
Patchset:
PS4:
coreboot table entries are supposed to be stable once they start being used, and they need to be aligned.
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Change subject: commonlib/loglevel.h: Fix Wunterminated-string-initialization error
......................................................................
Patch Set 4: Code-Review-2
(1 comment)
File src/commonlib/include/commonlib/loglevel.h:
https://review.coreboot.org/c/coreboot/+/84171/comment/deefd224_9a94b214?us… :
PS4, Line 169: /* Note: These strings are *not* null-terminated to save space. */
This comment is here explaining why things are the way they are specifically to make sure nobody uploads a patch like this. Please read before you delete.
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Change subject: amdfwtool: Check fletcher of each header
......................................................................
Patch Set 1:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/84338/comment/71ccbde2_0c5c8c69?us… :
PS1, Line 571: default: /* ISH */
hmm, the ISH table has its checksum where all other tables have the cookie field, so if we're unlucky and the ISH checksum has a value of one of the cookie values, we'll end up in the wrong case. so i wonder if the function should have a bool is_ish parameter to tell it if it's an ISH table to know for sure that it's an ISH table
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Hello Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Pranava Y N, Rishika Raj, Ronak Kanabar, Sean Rhodes, Subrata Banik, Tarun, Werner Zeh, build bot (Jenkins),
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Change subject: drivers/intel/fsp2_0: Simplify FSP global reset definition
......................................................................
drivers/intel/fsp2_0: Simplify FSP global reset definition
This commit simplifies the definition of the FSP global reset return
status:
1. According to the FSP 2.x specification, FSP reset status are a
suite of integers starting from FSP_STATUS_RESET_REQUIRED_COLD,
hence we can define the FSP Global reset as a simple index.
2. Since all the platforms defining
SOC_INTEL_COMMON_FSP_RESET (tigerlake, alderlake, jasperlake,
meteorlake, pantherlake, elkhartlake, skylake, cannonlake and
apollolake) pick a global reset value, we can default the most
common (3).
FSP 2.x status code uses the UEFI EFI_STATUS type (aka.
efi_return_status_t) type whose size varies with the
architecture (32-bit vs 64-bit). As a result of the code
simplification introduced by this commit, FSP_STATUS_GLOBAL_RESET is
appropriately defined for 64-bit FSP. Therefore, functions handling
this reset status such fsp_get_pch_reset_status() must use
efi_return_status_t type. It waterfalls into a few extra changes due
to dependencies.
BUG=b:348678529
TEST=FSP-s Global reset request is handled properly on pantherlake
fatcat
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5f
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/fsp2_0/Kconfig
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/common/fsp_reset.c
M src/soc/intel/common/reset.h
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/meteorlake/chip.c
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/chip.c
M src/soc/intel/skylake/Kconfig
M src/soc/intel/tigerlake/Kconfig
14 files changed, 25 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/84356/6
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