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Change subject: soc/amd/glinda: Update I2C for glinda
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/glinda/include/soc/smi.h:
https://review.coreboot.org/c/coreboot/+/84382/comment/98cadd69_e490c840?us… :
PS1, Line 88: #define SMITYPE_USB_PD_I2C4 40
> would be good to mark those as reserved to be consistent with the rest of the file
Done
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Hello Felix Held, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84382?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/amd/glinda: Update I2C for glinda
......................................................................
soc/amd/glinda: Update I2C for glinda
I24 and I2C5 don't exist.
Reference: Document 57254
Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M src/soc/amd/glinda/fch.c
M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
M src/soc/amd/glinda/include/soc/aoac_defs.h
M src/soc/amd/glinda/include/soc/i2c.h
M src/soc/amd/glinda/include/soc/smi.h
5 files changed, 1 insertion(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/84382/2
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Change subject: soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
......................................................................
Patch Set 4:
(6 comments)
File src/soc/intel/common/block/acpi/Kconfig:
https://review.coreboot.org/c/coreboot/+/84392/comment/cd675dad_74bf8248?us… :
PS4, Line 80: bool "SOC supports GPE1 Event bits"
same feedback
https://review.coreboot.org/c/coreboot/+/84392/comment/2713b2f1_c6dbe157?us… :
PS4, Line 88: SOC
please change `SOC` to `SoC`
https://review.coreboot.org/c/coreboot/+/84392/comment/92bb36db_074f8ae5?us… :
PS4, Line 94:
remove empty lines
https://review.coreboot.org/c/coreboot/+/84392/comment/e941eb5f_f9727dd0?us… :
PS4, Line 96: bool "SOC to use GPE1 Event approach"
please don't use the prompt, just `bool` is enough
we need to mention that mainboard should decide if they would like to use the GPE1 where else `SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1` exposes a SoC capability using ACPI
https://review.coreboot.org/c/coreboot/+/84392/comment/7536e719_7aa5205a?us… :
PS4, Line 99: SOC
SoC?
File src/soc/intel/common/block/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/84392/comment/db123944_7a5b8a71?us… :
PS2, Line 111: HAVE
> Subra, Yes. […]
Acknowledged
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Change subject: soc/amd/glinda: Update SCI mapping
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/glinda/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/84381/comment/c063d26b_f252a49b?us… :
PS1, Line 68: #define XHCI0_DEV 0x0
: #define XHCI0_FUNC 0
: #define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC)
> this one should be moved below the correct internal bus C
Done
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Hello Felix Held, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84381?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/amd/glinda: Update SCI mapping
......................................................................
soc/amd/glinda: Update SCI mapping
source: PPR #57254 Rev 1.71
Change-Id: I5eaed888109b89c25bcf0ba91abefa7c36c1851b
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M src/soc/amd/glinda/include/soc/pci_devs.h
M src/soc/amd/glinda/xhci.c
2 files changed, 27 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/84381/2
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Change subject: efi: Set EFIAPI to 32-bit ABI for FSP1_1
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84402/comment/e22e12f1_66aaf93d?us… :
PS2, Line 7: FSP1_1
which platform you have encountered this problem that has support for FSP1.1 and active ?
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Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84356?usp=email )
Change subject: drivers/intel/fsp2_0: Simplify FSP global reset definition
......................................................................
Patch Set 6:
(2 comments)
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/84356/comment/68e0d6d3_3d2b16cc?us… :
PS6, Line 347: 3
what is this magic number ?
earlier implementation was much clear, please keep the same implementation.
File src/soc/intel/apollolake/Kconfig:
https://review.coreboot.org/c/coreboot/+/84356/comment/dda330c4_82175bfe?us… :
PS6, Line 400: default 5
no one can follow these magic numbers w/o an explanation. The earlier implementation was very clean. Here you are only planning to add 64-bit support. that can be added like what you did as along as Intel FSP spec explicitly says what is the reset status difference between 32-bit vs 64-bit
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Change subject: soc/amd/glinda: Update gpp bridge naming scheme
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/amd/birman/devicetree_glinda.cb:
https://review.coreboot.org/c/coreboot/+/84378/comment/7ebb3b74_d49176f7?us… :
PS1, Line 161: device ref gpp_bridge_2_1 on end # NVME SSD0
: device ref gpp_bridge_2_2 on end # SD
: device ref gpp_bridge_2_3 on end # WLAN
: device ref gpp_bridge_2_4 on end # GBE
> this isn't just the rename of the bridges. […]
Done
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Hello Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/amd/glinda/chipset.cb: Update for glinda
......................................................................
soc/amd/glinda/chipset.cb: Update for glinda
This also updates the mainboards depending on it.
Change-Id: I1138f27bfd47f6fa70a0c2afcc65a5553a609d57
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M src/mainboard/amd/birman/devicetree_glinda.cb
M src/mainboard/amd/birman_plus/devicetree_glinda.cb
M src/soc/amd/glinda/chipset.cb
3 files changed, 103 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/84376/3
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Hello Felix Held, Fred Reitberger, Jason Glenesk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84378?usp=email
to look at the new patch set (#2).
Change subject: soc/amd/glinda: Update gpp bridge naming scheme
......................................................................
soc/amd/glinda: Update gpp bridge naming scheme
This patch updates the naming scheme used for the GPP bridges.
The naming scheme now matches what we also have on phoenix.
Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M src/mainboard/amd/birman/devicetree_glinda.cb
M src/mainboard/amd/birman_plus/devicetree_glinda.cb
M src/soc/amd/glinda/chipset.cb
3 files changed, 15 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/84378/2
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