coreboot-gerrit September 2024

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Subrata Banik (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Felix Held, Hannah Williams, Jamie Ryu, Paul Menzel. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 27: (1 comment) File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/84104/comment/df52d593_14ca6a31?us… : PS27, Line 237: HAVE should be `USE` -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 27 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 18 Sep 2024 03:01:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/fatcat: Add HDA verb tables
by Subrata Banik (Code Review) 18 Sep '24

18 Sep '24

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[L] Change in coreboot[main]: mb/google/fatcat: Add FW_CONFIG
by Subrata Banik (Code Review) 18 Sep '24

18 Sep '24

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[M] Change in coreboot[main]: soc/intel/ptl: Add GPE1 support in pmutil.c
by Cliff Huang (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84410?usp=email to look at the new patch set (#2). Change subject: soc/intel/ptl: Add GPE1 support in pmutil.c ...................................................................... soc/intel/ptl: Add GPE1 support in pmutil.c This change is to add the required GPE1 override functions for PTL. The override functions are called in Intel common pmclib.c. NOTE that GPE1 bits are SOC-specific and they are related to GPE0 events. 1. When CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 is set, the SOC GPE1 override functions soc_pmc_disable_std_gpe1() and soc_pmc_enable_std_gpe1() are required in order to configure GPE1 bits properly according to the corresponding GPE0 bits. 2. The mapping for GPE1 bits to their readable string is also provided BUG=b:362310295 TEST=This cannot be tested directly. Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 in google/fatcat or inte/ptlrvp. Boot to OS, Check both GPE0 and GPE1 EN bits. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia79c49d399eff4b2f6978323b2f5e2bb167d8638 --- M src/soc/intel/pantherlake/pmutil.c 1 file changed, 112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/84410/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84410?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia79c49d399eff4b2f6978323b2f5e2bb167d8638 Gerrit-Change-Number: 84410 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: mb/google/fatcat: Add override tree
by Subrata Banik (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Jérémy Compostella, Pranava Y N. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84407?usp=email ) Change subject: mb/google/fatcat: Add override tree ...................................................................... Patch Set 1: (13 comments) Patchset: PS1: Could you please add minimal override tree support without dumping all possible IOs at once? We should take devices one at a time and add their required changes when we're ready to enable them. File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/84407/comment/3dcc93f7_7ef64e33?us… : PS1, Line 3: # GPE configuration : # Note that GPE events called out in ASL code rely on this : # route. i.e. If this route changes then the affected GPE : # offset bits also need to be changed. : register "pmc_gpe0_dw0" = "GPP_B" : register "pmc_gpe0_dw1" = "GPP_D" : register "pmc_gpe0_dw2" = "GPP_E" this should do to baseboard devicetree https://review.coreboot.org/c/coreboot/+/84407/comment/93033073_bb95d40d?us… : PS1, Line 45: : # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f : register "gen1_dec" = "0x00fc0801" : register "gen2_dec" = "0x000c0201" : # EC memory map range is 0x900-0x9ff : register "gen3_dec" = "0x00fc0901" same as previous comment https://review.coreboot.org/c/coreboot/+/84407/comment/f841f763_a17c4706?us… : PS1, Line 52: # This disabled autonomous GPIO power management for early PO : register "gpio_override_pm" = "1" : register "gpio_pm[COMM_0]" = "0" : register "gpio_pm[COMM_1]" = "0" : register "gpio_pm[COMM_3]" = "0" : register "gpio_pm[COMM_4]" = "0" : register "gpio_pm[COMM_5]" = "0" we don't need to override to zero value, unless defined the value should be zero https://review.coreboot.org/c/coreboot/+/84407/comment/e12e5a8c_714c5691?us… : PS1, Line 69: # Enable s0ix : register "s0ix_enable" = "1" this should do to baseboard devicetree https://review.coreboot.org/c/coreboot/+/84407/comment/cd86d616_f9471c94?us… : PS1, Line 114: # Intel Common SoC Config we generally maintain a table to understand the I2Cx mapping, can you please apply that here as well ? https://review.coreboot.org/c/coreboot/+/84407/comment/01e0100e_ac498c74?us… : PS1, Line 223: please use consistent tab https://review.coreboot.org/c/coreboot/+/84407/comment/48329c87_4c984a6f?us… : PS1, Line 223: use usb2_port1 as usb2_port : use tcss_usb3_port0 as usb3_port : device generic 0 alias conn0 on end : end : chip drivers/intel/pmc_mux/conn : use usb2_port2 as usb2_port : use tcss_usb3_port1 as usb3_port : device generic 1 alias conn1 on end : end : chip drivers/intel/pmc_mux/conn : use usb2_port3 as usb2_port : use tcss_usb3_port2 as usb3_port : device generic 2 alias conn2 on end : end : chip drivers/intel/pmc_mux/conn : use usb2_port4 as usb2_port : use tcss_usb3_port3 as usb3_port : device generic 3 alias conn3 on end : end : end I also don't believe we need PMC MUX when we are planning to use PDC<->PMC communication in PTL https://review.coreboot.org/c/coreboot/+/84407/comment/34d089df_01fcb984?us… : PS1, Line 246: device ref pcie_rp1 off : # register "pcie_rp[PCIE_RP(1)]" = "{ : # .clk_src = 3, : # .clk_req = 3, : # .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, : # }" : end # Gbe please don't add GBE support which is non-POR for Chrome, if you wish to keep RP0 enabled then keep it on in devicetree.cb https://review.coreboot.org/c/coreboot/+/84407/comment/18475431_ab66d175?us… : PS1, Line 253: device ref pcie_rp2 on : register "pcie_rp[PCIE_RP(2)]" = "{ : .clk_src = 5, : .clk_req = 5, : .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, : }" : end # WWAN : device ref pcie_rp3 on : # Enable PCH PCIE x1 slot using CLK 3 : register "pcie_rp[PCIE_RP(3)]" = "{ : .clk_src = 2, : .clk_req = 2, : .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, : }" : chip soc/intel/common/block/pcie/rtd3 : register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)" : register "enable_delay_ms" = "100" : register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)" : register "reset_delay_ms" = "20" : register "srcclk_pin" = "2" : device generic 0 on end : end : end # PCIE x1 slot : device ref pcie_rp4 on : register "pcie_rp[PCH_RP(4)]" = "{ : .clk_src = 4, : .clk_req = 4, : .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, : }" : chip soc/intel/common/block/pcie/rtd3 : register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" : register "srcclk_pin" = "4" : device pci 00.0 on end : end : end # discrete WLAN all IOs should be part of FW_CONFIG. https://review.coreboot.org/c/coreboot/+/84407/comment/94c47c5e_bf2539fd?us… : PS1, Line 305: device ref pcie_rp9 on : register "pcie_rp[PCIE_RP(9)]" = "{ : .clk_src = 1, : .clk_req = 1, : .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, : }" : chip soc/intel/common/block/pcie/rtd3 : register "is_storage" = "true" : register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" : register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)" : register "srcclk_pin" = "1" : device generic 0 on end : end : end # Gen5 M.2 SSD / x4 PCIe slot please don't need Gen5 support. we will add depending on FW config later https://review.coreboot.org/c/coreboot/+/84407/comment/4c717505_b25f79ca?us… : PS1, Line 330: lnlrvp_ish please don't enable everything as part of base CL. Kindly keep ISH off for now https://review.coreboot.org/c/coreboot/+/84407/comment/cc2ca6c1_f67fc015?us… : PS1, Line 654: device ref hda on : chip drivers/intel/soundwire : device generic 0 on : chip drivers/soundwire/alc711 : # SoundWire Link 1 ID 1 : register "desc" = ""Headset Codec"" : device generic 1.1 on end : end : end : end : chip drivers/generic/max98357a : register "hid" = ""MX98357A"" : register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" : register "sdmode_delay" = "5" : device generic 0 on end : end : chip drivers/generic/max98357a : register "hid" = ""MX98360A"" : register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" : register "sdmode_delay" = "5" : device generic 0 on end : end : end : : end please use consistent spacing -- To view, visit https://review.coreboot.org/c/coreboot/+/84407?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d53 Gerrit-Change-Number: 84407 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 18 Sep 2024 02:54:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/nissa/var/riven: enable WIFI SAR
by Eric Lai (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: David Wu, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rishika Raj, Subrata Banik, YH Lin. Eric Lai has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/84339?usp=email ) Change subject: mb/google/nissa/var/riven: enable WIFI SAR ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84339?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I647d64a008991a7a20791b2c87ea6308af6bb82e Gerrit-Change-Number: 84339 Gerrit-PatchSet: 7 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 18 Sep 2024 02:54:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI
by Cliff Huang (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Paul Menzel, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84349?usp=email ) Change subject: soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/acpi/acpi/northbridge.asl: https://review.coreboot.org/c/coreboot/+/84349/comment/af227359_94017052?us… : PS6, Line 325: #if DMI_BASE_SIZE != 0 > #if DMI_BASE_SIZE Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d Gerrit-Change-Number: 84349 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 18 Sep 2024 02:54:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI
by Cliff Huang (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Cliff Huang, Paul Menzel. Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84349?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI ...................................................................... soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI In newer SOC, such as PTL, there is no DMI. Exclude DMI memory range in northbridge.asl if DMI_BASE_SIZE is '0' BUG=b:348678529 TEST=Build CB with DMI_BASE_SIZE set to '0' in the SOC directory. Boot to OS and check ACPI PDRC device from the ACPI DSDT table. There should not have an entry for DMI in its _CRS method. Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/84349/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/84349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d Gerrit-Change-Number: 84349 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/riven: enable WIFI SAR
by David Wu (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rishika Raj, Subrata Banik, YH Lin. David Wu has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/84339?usp=email ) Change subject: mb/google/nissa/var/riven: enable WIFI SAR ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/brya/variants/riven/variant.c: https://review.coreboot.org/c/coreboot/+/84339/comment/31d4d08f_61f08c40?us… : PS6, Line 14: : if ((type << 3 | sar_id) == UNDEFINED_FW_CONFIG) { > shouldn't we check if `type` || `sar_id` is UNDEFINED_FW_CONFIG and bail out early ? Thanks for reminding. -- To view, visit https://review.coreboot.org/c/coreboot/+/84339?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I647d64a008991a7a20791b2c87ea6308af6bb82e Gerrit-Change-Number: 84339 Gerrit-PatchSet: 7 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 18 Sep 2024 02:47:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: mb/google/fatcat: Add memory settings
by Subrata Banik (Code Review) 18 Sep '24

18 Sep '24

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coreboot-gerrit September 2024