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Change subject: soc/amd/glinda/include/smu.h: Update mailbox register addresses
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84384/comment/ed9278e5_80f772c1?us… :
PS1, Line 7: Updating MESSAGE and RESOPONSE address for SMU Mail box for STX
> soc/amd/glinda/include/smu. […]
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84384?usp=email
to look at the new patch set (#2).
Change subject: soc/amd/glinda/include/smu.h: Update mailbox register addresses
......................................................................
soc/amd/glinda/include/smu.h: Update mailbox register addresses
Signed-off-by: Avinash Munduru <AvinashMunduru(a)amd.com>
Change-Id: I427186aa9f0fb0650b2ab8d6171a51a33edf2778
Tested-by: Avinash Munduru <Avinash.Munduru(a)amd.com>
Reviewed-by: Anand Vaikar <Anand.Vaikar(a)amd.com>
---
M src/soc/amd/glinda/include/soc/smu.h
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/84384/2
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Change subject: soc/amd/glinda: Update pci int defs
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/glinda/fch.c:
https://review.coreboot.org/c/coreboot/+/84375/comment/663c01df_2f4596d5?us… :
PS1, Line 65: { PIRQ_UART2, "UART2" },
> PIRQ_GSCI and PIRQ_GSMI missing from amd_pci_int_defs. […]
Done
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84375?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/amd/glinda: Update pci int defs
......................................................................
soc/amd/glinda: Update pci int defs
source:
PPR #57254 Rev 1.59 Table 137
Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M src/soc/amd/glinda/acpi/pci_int_defs.asl
M src/soc/amd/glinda/fch.c
M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
3 files changed, 15 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/84375/2
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 27:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/d4d8a25a_f9b97fa9?us… :
PS27, Line 237: HAVE
> should be `USE`
shoudn't we need to clear and disable GPE1 events regardless we use GPE1 or not. after all, they still exists. _USE_ flag exposes GPE1 blocks in FADT and ACPI (GEP1 handers) _Lnn events are added instead of GPE0 _Lnn methods.
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Change subject: soc/intel/ptl: Add GPE1 support in pmutil.c
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/pantherlake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/84410/comment/ca204ded_2f288139?us… :
PS2, Line 181: if (std_gpe0_mask & PME_B0_EN)
: pmc_disable_gpe1(GPE1_EN(0), GPE1_PME_B0_EVENT_EN_BITS);
:
: if (std_gpe0_mask & TC_PME_B0_EN)
: pmc_disable_gpe1(GPE1_EN(0), GPE1_TC_PME_B0_EVENT_EN_BITS);
:
> isn't `PME_B0_EN` is a super set of `TC_PME_B0_EN`?
No. TC_PME_B0_EN is added to GPE0 in PTL. TCSS uses separate one now.
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Hello Bora Guvendik, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
......................................................................
soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to add GPE1 block
rather than checking if GPE1_STS(0) is '0'.
BUG:362310295
TEST=with the flag, boot google/fatcat or intel/ptlrvp to OS and check
that FADT table includes GPE1. FADT should have:
GPE1 Block Address : 00001810
GPE1 Block Length : 18
GPE1 Base Offset : 80
Without the flag, boot to OS and check that FADT table does not include
GPE1. FADT should have:
GPE1 Block Address : 0
GPE1 Block Length : 0
GPE1 Base Offset : 0
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7
---
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/acpi.c
2 files changed, 28 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/84392/5
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Change subject: soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI
......................................................................
Patch Set 7: Code-Review+2
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