Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84297?usp=email
to look at the new patch set (#12).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Define GPE1 macros and register fields
......................................................................
soc/intel/ptl: Define GPE1 macros and register fields
New GPE1 bits are introduced in PTL for internal devices, incuding
PME_B0, hot plug, and PCIe events.
defines for GPE number for additional STD GPE0 in PTL
defines for GPE number for GPE1
defines for GPE1 bits
NOTE: All GEP1 bits are STD (Intel's Standard) GPE bits.
BUG=362310295
TEST=This cannot be tested directly.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836
---
M src/soc/intel/pantherlake/include/soc/gpe.h
M src/soc/intel/pantherlake/include/soc/pm.h
2 files changed, 436 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84297/12
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Attention is currently required from: Anil Kumar K, Bora Guvendik, Felix Held, Hannah Williams, Jamie Ryu, Paul Menzel, Subrata Banik.
Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84104?usp=email
to look at the new patch set (#27).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
soc/intel/common/block/pmc: Add GPE1 functions
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 flag.
- The existing static gpe functions has been renamed with gpe0.
- Add gpe1 functions.
BUG=b:362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 flag,
boot google/fatcat or intel/ptlrvp DUT, and check if GPE1 sts bits have
been printed during boot. Search for:
[DEBUG] GPE1 STD STS: <event string>
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 123 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/27
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Maximilian Brune has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84379?usp=email )
Change subject: Update UPD for system configuration, Fast and Slow PPT to set 45W TDP
......................................................................
Abandoned
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Jérémy Compostella has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email )
Change subject: mb/google/fatcat: Add Panther Lake SOC support
......................................................................
Patch Set 180:
(2 comments)
Patchset:
PS179:
> very difficult to review the code like this […]
Done
File src/mainboard/google/fatcat/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/83419/comment/ff487f55_751e5efc?us… :
PS179, Line 13: 0x20110725
> this should be updated now ?
Done
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Attention is currently required from: Ashish Kumar Mishra, Cliff Huang, Felix Held, Jérémy Compostella, Paul Menzel, Pranava Y N, Saurabh Mishra.
Jérémy Compostella has uploaded a new patch set (#180) to the change originally created by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83419?usp=email )
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: mb/google/fatcat: Add Panther Lake SOC support
......................................................................
mb/google/fatcat: Add Panther Lake SOC support
- This patch updates the original google/fatcat support added
with Meteor Lake support as a workaround.
- Adds initial support to build google/fatcat for Panther Lake SOC
- Adds soc acpi file entry in mainboard dsdt.asl
BUG=b:348678529
TEST=Build google fatcat board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/mainboard/google/fatcat/Kconfig
M src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
M src/mainboard/google/fatcat/chromeos.fmd
M src/mainboard/google/fatcat/dsdt.asl
M src/mainboard/google/fatcat/mainboard.c
M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
M src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/fatcat/variants/fatcat/gpio.c
M src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h
9 files changed, 77 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83419/180
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