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Change subject: mb/google: amd projects: Add signed verstage files
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Patch Set 3:
(1 comment)
Patchset:
PS3:
> Could we get release notes and license files added please? […]
I'll file a bug to add.
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
Patch Set 71:
(2 comments)
File src/soc/intel/pantherlake/elog.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/ccf7f1b7_5911b64d?us… :
PS71, Line 140:
> should we be adding GPE1 as well here? […]
Yes. The code is ready once GPE1 changes CLs are merged, I will work with
Saurabh to include the changes, including GPE1 changes in include/soc/pm.h and include/soc/gpe.h, as well as tcss ASL files in https://review.coreboot.org/c/coreboot/+/83772.
File src/soc/intel/pantherlake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/b1f8b37c_9f9bf541?us… :
PS71, Line 110:
> should we add GPE1 as well here […]
Yes. The code is ready once GPE1 changes CLs are merged, I will work with
Saurabh to include the changes, including GPE1 changes in include/soc/pm.h and include/soc/gpe.h, as well as tcss ASL files in https://review.coreboot.org/c/coreboot/+/83772.
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Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84104?usp=email
to look at the new patch set (#8).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
soc/intel/common/block/pmc: Add GPE1 functions
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag.
- The existing static gpe functions has been renamed with gpe0.
- Add gpe1 functions.
- Remove functions that enables GPE events. This is not used and should
not be used during boot.
BUG=362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag, boot DUT,
and check if GPE1 sts bits have been printed during boot.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 72 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/8
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 7:
(9 comments)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/84104/comment/05ddc183_befa9a8d?us… :
PS3, Line 406: pmc_clear_gpi_gpe0_status
> > gpi_gpe0 means the general GPI event in GPE0. GPE1 only contains Intel's std events. […]
Subrata,
pmc_disable_all_gpe() is called in smm_southbridge_enable function in src/soc/intel/common/block/smm/smm.c.
from SOC cpu.c, we have MP OPS:
.pre_mp_smm_init = smm_initialize, <- NOTE: GPE STS bits are cleared here
.post_mp_init = post_mp_init, <- NOTE: GPE EN bits are cleared here
This should still be earlier enough.
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/84104/comment/7fa9afc6_43c665c0?us… :
PS7, Line 306: 0
> this should be NULL ? as you are returning `char *`
Done
https://review.coreboot.org/c/coreboot/+/84104/comment/096aedda_cd23f62a?us… :
PS7, Line 341: pmc_clear_gpi_gpe0_status
> sure. working on this.
I do a search and only the existing gpe event disabling functions need to cover GPE1 EN bits if _HAVE_GPE1. By doing this, no _gpe_function needs to be renamed outside of pmclib.c.
In addition, I delete the GPE event enable functions since not used. CB should not enable these events during boot, anyways.
https://review.coreboot.org/c/coreboot/+/84104/comment/93761458_c330ea5c?us… :
PS7, Line 379: gpe_sts
> check the NULL pointer at line 381
Done
https://review.coreboot.org/c/coreboot/+/84104/comment/73efea28_9331eb8f?us… :
PS7, Line 381: int i;
> drop
Done
https://review.coreboot.org/c/coreboot/+/84104/comment/4c6fabb1_8d2596be?us… :
PS7, Line 383: i
> ```int i```
Done
https://review.coreboot.org/c/coreboot/+/84104/comment/78107c0a_bf24424a?us… :
PS7, Line 393: int i;
> same
Done
https://review.coreboot.org/c/coreboot/+/84104/comment/caaee312_6089af7c?us… :
PS7, Line 396: sts_arr =
> missing NULL check ?
Done
https://review.coreboot.org/c/coreboot/+/84104/comment/18023c22_27025b52?us… :
PS7, Line 406: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) {
> WDYT […]
Done
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