coreboot-gerrit September 2024

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[M] Change in coreboot[main]: mb/google/brask/var/bujia: Add PsysPmax setting
by Derek Huang (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Shon Wang, Subrata Banik. Derek Huang has posted comments on this change by Shon Wang. ( https://review.coreboot.org/c/coreboot/+/83593?usp=email ) Change subject: mb/google/brask/var/bujia: Add PsysPmax setting ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83593/comment/fda7d0dd_fb2763b8?us… : PS8, Line 9: displayer display -- To view, visit https://review.coreboot.org/c/coreboot/+/83593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Gerrit-Change-Number: 83593 Gerrit-PatchSet: 8 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 01:08:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/brask/var/bujia: Add PsysPmax setting
by Derek Huang (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Shon Wang, Subrata Banik. Derek Huang has posted comments on this change by Shon Wang. ( https://review.coreboot.org/c/coreboot/+/83593?usp=email ) Change subject: mb/google/brask/var/bujia: Add PsysPmax setting ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/brya/variants/bujia/ramstage.c: https://review.coreboot.org/c/coreboot/+/83593/comment/4e6dabe3_3bad18e7?us… : PS8, Line 41: kuldax bujia -- To view, visit https://review.coreboot.org/c/coreboot/+/83593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Gerrit-Change-Number: 83593 Gerrit-PatchSet: 8 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 01:07:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/brask/var/bujia: Add PsysPmax setting
by Derek Huang (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Shon Wang, Subrata Banik. Derek Huang has posted comments on this change by Shon Wang. ( https://review.coreboot.org/c/coreboot/+/83593?usp=email ) Change subject: mb/google/brask/var/bujia: Add PsysPmax setting ...................................................................... Patch Set 8: (4 comments) File src/mainboard/google/brya/variants/bujia/include/variant/get_input_power_voltage.h: https://review.coreboot.org/c/coreboot/+/83593/comment/2d435978_96abcfa8?us… : PS8, Line 1: /* SPDX-License-Identifier: GPL-2.0-or-later */ : : #ifndef VARIANT_GET_INPUT_POWER_VOLTAGE_H : #define VARIANT_GET_INPUT_POWER_VOLTAGE_H : : int32_t get_input_power_voltage(void); : : #endif : This file is redundant. File src/mainboard/google/brya/variants/bujia/ramstage.c: https://review.coreboot.org/c/coreboot/+/83593/comment/85d46d46_379b4858?us… : PS8, Line 10: #include <fw_config.h> redundant https://review.coreboot.org/c/coreboot/+/83593/comment/56f981e8_787218cc?us… : PS8, Line 12: #include <variant/get_input_power_voltage.h> redundant https://review.coreboot.org/c/coreboot/+/83593/comment/3022645d_163a2680?us… : PS8, Line 64: int32_t static int32_t -- To view, visit https://review.coreboot.org/c/coreboot/+/83593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd Gerrit-Change-Number: 83593 Gerrit-PatchSet: 8 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 01:04:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[NoOp] Change in blobs[main]: mb/google: amd projects: Add signed verstage files
by Jon Murphy (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Matt DeVillier. Jon Murphy has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/blobs/+/76477?usp=email ) Change subject: mb/google: amd projects: Add signed verstage files ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Could we get release notes and license files added please? […] I'll file a bug to add. -- To view, visit https://review.coreboot.org/c/blobs/+/76477?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I3ce54d2bbd84a9b0b0ed070fde86d91cd0c8c6a9 Gerrit-Change-Number: 76477 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 22:06:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com>

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[L] Change in coreboot[main]: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support
by Angel Pons (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Alicja Michalska, David Milosevic. Angel Pons has posted comments on this change by David Milosevic. ( https://review.coreboot.org/c/coreboot/+/83979?usp=email ) Change subject: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support ...................................................................... Patch Set 2: (5 comments) File src/mainboard/hardkernel/odroid-h4/devicetree.cb: https://review.coreboot.org/c/coreboot/+/83979/comment/6cf2e774_8e5fc087?us… : PS2, Line 84: # .clk_src = 2, > On most ADL-N systems, M.2 NVME is connected to Clock Source 0. […] Nice, schematics are also available from the Odroid wiki: https://wiki.odroid.com/_media/odroid-h4/hardware/adln-h4_sch_2024-0306.pdf https://review.coreboot.org/c/coreboot/+/83979/comment/d8cb4db5_09ea5ffb?us… : PS2, Line 82: #device ref pcie_rp3 on : # register "pch_pcie_rp[PCH_RP(3)]" = "{ : # .clk_src = 2, : # .clk_req = 2, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : # smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" : # "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth2X" : #end : #device ref pcie_rp7 on # LAN1 : # register "pch_pcie_rp[PCH_RP(7)]" = "{ : # .clk_src = 3, : # .clk_req = 3, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : #end : #device ref pcie_rp9 on # LAN2 : # register "pch_pcie_rp[PCH_RP(9)]" = "{ : # .clk_src = 0, : # .clk_req = 0, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : #end : #device ref pcie_rp10 on : # register "pch_pcie_rp[PCH_RP(10)]" = "{ : # .clk_src = 1, : # .clk_req = 1, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : # smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" : # "M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X" : #end I've left it commented out so that the differences are easier to see, but you should obviously uncomment it: ```suggestion #device ref pcie_rp3 on # LAN1 # register "pch_pcie_rp[PCH_RP(3)]" = "{ # .clk_src = 1, # .clk_req = 1, # .flags = PCIE_RP_CLK_REQ_DETECT, # }" #end #device ref pcie_rp4 on # LAN2 # register "pch_pcie_rp[PCH_RP(4)]" = "{ # .clk_src = 2, # .clk_req = 2, # .flags = PCIE_RP_CLK_REQ_DETECT, # }" #end #device ref pcie_rp7 on # ASM1064B SATA # register "pch_pcie_rp[PCH_RP(7)]" = "{ # .clk_src = 3, # .flags = PCIE_RP_CLK_REQ_UNUSED, # }" #end #device ref pcie_rp9 on # M.2 SSD # register "pch_pcie_rp[PCH_RP(9)]" = "{ # .clk_src = 0, # .clk_req = 0, # .flags = PCIE_RP_CLK_REQ_DETECT, # }" # smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" # "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth4X" #end ``` https://review.coreboot.org/c/coreboot/+/83979/comment/e2441410_b81f25ce?us… : PS2, Line 148: device pnp 2e.a on end # CIR CIR seems unused as well https://review.coreboot.org/c/coreboot/+/83979/comment/3187d3e2_c66af2b9?us… : PS2, Line 151: device ref uart0 on : register "serial_io_uart_mode" = "{ : [PchSerialIoIndexUART0] = PchSerialIoSkipInit, : }" : end I can't see this being used in the schematics, the UART on the 2x12 header comes from the IT8613E Super I/O https://review.coreboot.org/c/coreboot/+/83979/comment/273d6ed7_a7c39893?us… : PS2, Line 156: device ref gspi0 on : register "serial_io_gspi_mode" = "{ : [PchSerialIoIndexGSPI0] = PchSerialIoPci, : }" : end GSPI0 pins are disconnected in the schematic, this can be disabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/83979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Gerrit-Change-Number: 83979 Gerrit-PatchSet: 2 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 20:54:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Cliff Huang (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Saurabh Mishra, Subrata Banik. Cliff Huang has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 71: (2 comments) File src/soc/intel/pantherlake/elog.c: https://review.coreboot.org/c/coreboot/+/83798/comment/ccf7f1b7_5911b64d?us… : PS71, Line 140: > should we be adding GPE1 as well here? […] Yes. The code is ready once GPE1 changes CLs are merged, I will work with Saurabh to include the changes, including GPE1 changes in include/soc/pm.h and include/soc/gpe.h, as well as tcss ASL files in https://review.coreboot.org/c/coreboot/+/83772. File src/soc/intel/pantherlake/pmutil.c: https://review.coreboot.org/c/coreboot/+/83798/comment/b1f8b37c_9f9bf541?us… : PS71, Line 110: > should we add GPE1 as well here […] Yes. The code is ready once GPE1 changes CLs are merged, I will work with Saurabh to include the changes, including GPE1 changes in include/soc/pm.h and include/soc/gpe.h, as well as tcss ASL files in https://review.coreboot.org/c/coreboot/+/83772. -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 71 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 20:15:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: [WIP] superio/ite: Add support for IT8625E
by Alicja Michalska (Code Review) 01 Sep '24

01 Sep '24

Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84176?usp=email ) Change subject: [WIP] superio/ite: Add support for IT8625E ...................................................................... [WIP] superio/ite: Add support for IT8625E We don't have datasheet for this chip, but iTech doesn't change their design much. Found on tiny firewall appliance from Chinese company named "Topton" with Intel N100 SoC. Because this system is fanless, all we really need is the ability to use cisco-style serial console on front of the device, which is working. Change-Id: I9c27f52785d294a6f7c315b8df47d4dd5b389414 Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A src/superio/ite/it8625e/Kconfig A src/superio/ite/it8625e/Makefile.mk A src/superio/ite/it8625e/chip.h A src/superio/ite/it8625e/it8625e.h A src/superio/ite/it8625e/superio.c 5 files changed, 109 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/84176/1 diff --git a/src/superio/ite/it8625e/Kconfig b/src/superio/ite/it8625e/Kconfig new file mode 100644 index 0000000..2f1d557 --- /dev/null +++ b/src/superio/ite/it8625e/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_ITE_IT8625E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8625e/Makefile.mk b/src/superio/ite/it8625e/Makefile.mk new file mode 100644 index 0000000..a906e9b --- /dev/null +++ b/src/superio/ite/it8625e/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_ITE_IT8625E) += superio.c diff --git a/src/superio/ite/it8625e/chip.h b/src/superio/ite/it8625e/chip.h new file mode 100644 index 0000000..6deb23a --- /dev/null +++ b/src/superio/ite/it8625e/chip.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8625E_CHIP_H +#define SUPERIO_ITE_IT8625E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8625e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8625E_CHIP_H */ diff --git a/src/superio/ite/it8625e/it8625e.h b/src/superio/ite/it8625e/it8625e.h new file mode 100644 index 0000000..0e4b094 --- /dev/null +++ b/src/superio/ite/it8625e/it8625e.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8625E_H +#define SUPERIO_ITE_IT8625E_H + +#define IT8625E_FDC 0x00 /* Floppy Controller */ +#define IT8625E_SP1 0x01 /* Com1 */ +#define IT8625E_SP2 0x02 /* Com2 */ +#define IT8625E_PP 0x03 /* Parallel port */ +#define IT8625E_EC 0x04 /* Environment controller */ +#define IT8625E_KBCK 0x05 /* PS/2 keyboard */ +#define IT8625E_KBCM 0x06 /* PS/2 mouse */ +#define IT8625E_GPIO 0x07 /* GPIO */ + +#endif /* SUPERIO_ITE_IT8625E_H */ diff --git a/src/superio/ite/it8625e/superio.c b/src/superio/ite/it8625e/superio.c new file mode 100644 index 0000000..1a291d4a9f4 --- /dev/null +++ b/src/superio/ite/it8625e/superio.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <superio/conf_mode.h> +#include <superio/ite/common/env_ctrl.h> + +#include "chip.h" +#include "it8625e.h" + +/* No datasheet available for this chip. So far it's only been found in + * firewall appliance from Topton. All we care about in this scenario + * is the ability to use cisco-style RS232 console, which is working. */ + +static void it8625e_init(struct device *dev) +{ + const struct superio_ite_it8625e_config *conf = dev->chip_info; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8625E_EC: + res = probe_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8625E_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case IT8625E_KBCM: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8625e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8625E_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, }, + { NULL, IT8625E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8625E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8625E_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0, + 0x0ff8, 0x0ff8, }, + { NULL, IT8625E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff0, 0x0ff0, }, + { NULL, IT8625E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, }, + { NULL, IT8625E_KBCM, PNP_IRQ0, }, + { NULL, IT8625E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, + 0x0fff, 0x0fe0, 0x0fff, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8625e_ops = { + .name = "ITE IT8625E Super I/O", + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/84176?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c27f52785d294a6f7c315b8df47d4dd5b389414 Gerrit-Change-Number: 84176 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com>

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[L] Change in coreboot[main]: [WIP] mb/topton/adl: Add initial support for X2F N100 FW appliance
by Alicja Michalska (Code Review) 01 Sep '24

01 Sep '24

Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84175?usp=email ) Change subject: [WIP] mb/topton/adl: Add initial support for X2F N100 FW appliance ...................................................................... [WIP] mb/topton/adl: Add initial support for X2F N100 FW appliance X2F-N100 is an embedded device/firewall with Intel N100 SoC and 4x 2.5Gb Intel I226-V NICs. Currently tested and working: - Platform bringup - Payload (EDK2) - All USB ports - M.2 NVME - 4x NICs Broken/not working/TODO: - SATA - Suspend (probably won't care, since it's an appliance for 24/7 use) - Internal USB ports on M.2/mPCI-E slots - mPCI-E slot (don't have any cards on hand) - PCI-E passtrough (VT-d) - All SuperIO functions aside from RS232 (cisco-style console) Time spend on this port so far: 2 hours. Change-Id: Ic5cd2060c1635b79cb28ffe294220b63ad2bab65 Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A src/mainboard/topton/Kconfig A src/mainboard/topton/Kconfig.name A src/mainboard/topton/adl/Kconfig A src/mainboard/topton/adl/Kconfig.name A src/mainboard/topton/adl/Makefile.mk A src/mainboard/topton/adl/board_info.txt A src/mainboard/topton/adl/bootblock.c A src/mainboard/topton/adl/data.vbt A src/mainboard/topton/adl/devicetree.cb A src/mainboard/topton/adl/dsdt.asl A src/mainboard/topton/adl/gpio.h A src/mainboard/topton/adl/mainboard.c A src/mainboard/topton/adl/romstage_fsp_params.c 13 files changed, 588 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/84175/1 diff --git a/src/mainboard/topton/Kconfig b/src/mainboard/topton/Kconfig new file mode 100644 index 0000000..6010fcf --- /dev/null +++ b/src/mainboard/topton/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if VENDOR_TOPTON + +choice + prompt "Mainboard model" + +source "src/mainboard/topton/*/Kconfig.name" + +endchoice + +source "src/mainboard/topton/*/Kconfig" + +config MAINBOARD_VENDOR + default "TOPTON" + +endif # VENDOR_TOPTON diff --git a/src/mainboard/topton/Kconfig.name b/src/mainboard/topton/Kconfig.name new file mode 100644 index 0000000..3ed4b2d --- /dev/null +++ b/src/mainboard/topton/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config VENDOR_TOPTON + bool "Topton" diff --git a/src/mainboard/topton/adl/Kconfig b/src/mainboard/topton/adl/Kconfig new file mode 100644 index 0000000..63c137c --- /dev/null +++ b/src/mainboard/topton/adl/Kconfig @@ -0,0 +1,41 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_TOPTON_X2F_N100 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select FSP_TYPE_IOT + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select SUPERIO_ITE_IT8625E + select DRIVERS_UART_8250IO + select DRIVERS_USB_ACPI + select USE_LEGACY_8254_TIMER + select SOC_INTEL_ALDERLAKE_PCH_N + +config MAINBOARD_DIR + default "topton/adl" + +config MAINBOARD_PART_NUMBER + default "X2F_N100" + +config NO_POST + default y + +# Speeds up FSP memory training +config DIMM_MAX + default 2 + +# For debugging purposes, will be removed in the future +config PCIEXP_ASPM + default n + +config PCIEXP_L1_SUB_STATE + default n + +config PCIEXP_CLK_PM + default n + +endif diff --git a/src/mainboard/topton/adl/Kconfig.name b/src/mainboard/topton/adl/Kconfig.name new file mode 100644 index 0000000..5b8b5ff --- /dev/null +++ b/src/mainboard/topton/adl/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_TOPTON_X2F_N100 + bool "X2F_N100" diff --git a/src/mainboard/topton/adl/Makefile.mk b/src/mainboard/topton/adl/Makefile.mk new file mode 100644 index 0000000..62d07cd --- /dev/null +++ b/src/mainboard/topton/adl/Makefile.mk @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +bootblock-y += bootblock.c +romstage-y += romstage_fsp_params.c +ramstage-y += mainboard.c diff --git a/src/mainboard/topton/adl/board_info.txt b/src/mainboard/topton/adl/board_info.txt new file mode 100644 index 0000000..75dbcc3 --- /dev/null +++ b/src/mainboard/topton/adl/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Topton +Board name: X2F_N100 +Release year: 2023 +Category: Embedded +ROM IC: W25Q128FV +ROM package: SOIC-8 +ROM socketed: no +Flashrom support: yes diff --git a/src/mainboard/topton/adl/bootblock.c b/src/mainboard/topton/adl/bootblock.c new file mode 100644 index 0000000..285c328 --- /dev/null +++ b/src/mainboard/topton/adl/bootblock.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8625e/it8625e.h> + +#define UART_DEV PNP_DEV(0x2e, IT8625E_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/topton/adl/data.vbt b/src/mainboard/topton/adl/data.vbt new file mode 100644 index 0000000..e9522d7 --- /dev/null +++ b/src/mainboard/topton/adl/data.vbt Binary files differ diff --git a/src/mainboard/topton/adl/devicetree.cb b/src/mainboard/topton/adl/devicetree.cb new file mode 100644 index 0000000..cca5024 --- /dev/null +++ b/src/mainboard/topton/adl/devicetree.cb @@ -0,0 +1,105 @@ +chip soc/intel/alderlake + + register "s0ix_enable" = "1" + register "dptf_enable" = "1" + register "sagv" = "SaGv_Enabled" + + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + device domain 0 on + device ref igpu on end + + # TODO: Even though USB ports are functional, they're not mapped correctly. + # Need to check and enable only necessary ones. + + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), + [1] = USB2_PORT_MID(OC_SKIP), + [2] = USB2_PORT_MID(OC_SKIP), + [3] = USB2_PORT_MID(OC_SKIP), + [4] = USB2_PORT_MID(OC_SKIP), + [5] = USB2_PORT_MID(OC_SKIP), + [6] = USB2_PORT_MID(OC_SKIP), + [7] = USB2_PORT_MID(OC_SKIP), + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), + [1] = USB3_PORT_DEFAULT(OC_SKIP), + [2] = USB3_PORT_DEFAULT(OC_SKIP), + [3] = USB3_PORT_DEFAULT(OC_SKIP), + [4] = USB3_PORT_DEFAULT(OC_SKIP), + [5] = USB3_PORT_DEFAULT(OC_SKIP), + [6] = USB3_PORT_DEFAULT(OC_SKIP), + [7] = USB3_PORT_DEFAULT(OC_SKIP), + }" + end + + device ref shared_sram on end + + # TODO: SATA doesn't work. EDK2 returns "Unsupported", not sure how to fix (yet). + device ref sata on end + + # TODO: PCI-E ClkReq/ClkSrc - power management. PCI-E passtrough currently crashes the platform. + device ref pcie_rp1 on + register "pch_pcie_rp[PCH_RP(1)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + end # I226-V: 1 + + device ref pcie_rp2 on + register "pch_pcie_rp[PCH_RP(2)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + end # I226-V: 2 + + device ref pcie_rp3 on + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + end # I226-V: 3 + + device ref pcie_rp7 on + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + end # I226-V: 4 + + device ref pcie_rp9 on + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_CLK_REQ_UNUSED, + .pcie_rp_aspm = ASPM_DISABLE, + }" + end # M.2 (x2) + + device ref pch_espi on + chip superio/ite/it8625e + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 0x4 + irq 0xf0 = 0x1 + end + end + end + + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/topton/adl/dsdt.asl b/src/mainboard/topton/adl/dsdt.asl new file mode 100644 index 0000000..132ed37 --- /dev/null +++ b/src/mainboard/topton/adl/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/topton/adl/gpio.h b/src/mainboard/topton/adl/gpio.h new file mode 100644 index 0000000..6b990c2 --- /dev/null +++ b/src/mainboard/topton/adl/gpio.h @@ -0,0 +1,321 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* CORE_VID0 */ + _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* CORE_VID1 */ + _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* VRALERT# */ + PAD_NC(GPP_B3, NONE), /* GPIO */ + PAD_NC(GPP_B4, NONE), /* GPIO */ + PAD_NC(GPP_B5, NONE), /* GPIO */ + PAD_NC(GPP_B6, NONE), /* GPIO */ + PAD_NC(GPP_B7, NONE), /* GPIO */ + PAD_NC(GPP_B8, NONE), /* GPIO */ + PAD_NC(GPP_B9, NONE), /* GPIO */ + PAD_NC(GPP_B10, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PMCALERT# */ + _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* SLP_S0# */ + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* PLTRST# */ + _PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SPKR */ + PAD_NC(GPP_B15, NONE), /* GPIO */ + PAD_NC(GPP_B16, NONE), /* GPIO */ + PAD_NC(GPP_B17, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_B19, NONE), /* GPIO */ + PAD_NC(GPP_B20, NONE), /* GPIO */ + PAD_NC(GPP_B21, NONE), /* GPIO */ + PAD_NC(GPP_B22, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B24, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* GSPI0_CLK_LOOPBK */ + _PAD_CFG_STRUCT(GPP_B25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* GSPI1_CLK_LOOPBK */ + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T0, NONE), /* GPIO */ + PAD_NC(GPP_T1, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_T2, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), /* FUSA_DIAGTEST_EN */ + _PAD_CFG_STRUCT(GPP_T3, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), /* FUSA_DIAGTEST_MODE */ + PAD_NC(GPP_T4, NONE), /* GPIO */ + PAD_NC(GPP_T5, NONE), /* GPIO */ + PAD_NC(GPP_T6, NONE), /* GPIO */ + PAD_NC(GPP_T7, NONE), /* GPIO */ + PAD_NC(GPP_T8, NONE), /* GPIO */ + PAD_NC(GPP_T9, NONE), /* GPIO */ + PAD_NC(GPP_T10, NONE), /* GPIO */ + PAD_NC(GPP_T11, NONE), /* GPIO */ + PAD_NC(GPP_T12, NONE), /* GPIO */ + PAD_NC(GPP_T13, NONE), /* GPIO */ + PAD_NC(GPP_T14, NONE), /* GPIO */ + PAD_NC(GPP_T15, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_A ------- */ + _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_IO0 */ + _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_IO1 */ + _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_IO2 */ + _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_IO3 */ + _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_CS0# */ + _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* ESPI_ALERT0# */ + _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* ESPI_ALERT1# */ + PAD_CFG_GPO(GPP_A7, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_A8, 0, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), /* ESPI_CLK */ + _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* ESPI_RESET# */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_A12, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* USB_OC1# */ + _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* USB_OC3# */ + PAD_NC(GPP_A17, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(TxDRxE)), /* DDSP_HPDB */ + _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPD1 */ + PAD_NC(GPP_A20, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_A22, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), /* ESPI_CS1# */ + _PAD_CFG_STRUCT(GPP_ESPI_CLK_LOOPBK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* GPP_ESPI_CLK_LOOPBK */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), /* GPIO */ + PAD_NC(GPP_S1, NONE), /* GPIO */ + PAD_NC(GPP_S2, NONE), /* GPIO */ + PAD_NC(GPP_S3, NONE), /* GPIO */ + PAD_NC(GPP_S4, NONE), /* GPIO */ + PAD_NC(GPP_S5, NONE), /* GPIO */ + PAD_NC(GPP_S6, NONE), /* GPIO */ + PAD_NC(GPP_S7, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), /* GPIO */ + PAD_NC(GPP_I1, NONE), /* GPIO */ + PAD_NC(GPP_I2, NONE), /* GPIO */ + PAD_NC(GPP_I3, NONE), /* GPIO */ + PAD_NC(GPP_I4, NONE), /* GPIO */ + PAD_NC(GPP_I5, NONE), /* GPIO */ + PAD_NC(GPP_I6, NONE), /* GPIO */ + PAD_NC(GPP_I7, NONE), /* GPIO */ + PAD_NC(GPP_I8, NONE), /* GPIO */ + PAD_NC(GPP_I9, NONE), /* GPIO */ + PAD_NC(GPP_I10, NONE), /* GPIO */ + PAD_NC(GPP_I11, NONE), /* GPIO */ + PAD_NC(GPP_I12, NONE), /* GPIO */ + PAD_NC(GPP_I13, NONE), /* GPIO */ + PAD_NC(GPP_I14, NONE), /* GPIO */ + PAD_NC(GPP_I15, NONE), /* GPIO */ + PAD_NC(GPP_I16, NONE), /* GPIO */ + PAD_NC(GPP_I17, NONE), /* GPIO */ + PAD_NC(GPP_I18, NONE), /* GPIO */ + PAD_NC(GPP_I19, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H2, 1, RSMRST), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_NC(GPP_H4, NONE), /* GPIO */ + PAD_NC(GPP_H5, NONE), /* GPIO */ + PAD_NC(GPP_H6, NONE), /* GPIO */ + PAD_NC(GPP_H7, NONE), /* GPIO */ + PAD_NC(GPP_H8, NONE), /* GPIO */ + PAD_NC(GPP_H9, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), /* UART0_RXD */ + _PAD_CFG_STRUCT(GPP_H11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSTERM(DISPUPD)), /* UART0_TXD */ + PAD_NC(GPP_H12, NONE), /* GPIO */ + PAD_NC(GPP_H13, NONE), /* GPIO */ + PAD_NC(GPP_H14, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* DDPB_CTRLCLK */ + PAD_NC(GPP_H16, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* DDPB_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_H18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* PROC_C10_GATE# */ + _PAD_CFG_STRUCT(GPP_H19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ4# */ + PAD_NC(GPP_H20, NONE), /* GPIO */ + PAD_NC(GPP_H21, NONE), /* GPIO */ + PAD_NC(GPP_H22, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H23, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ5# */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), /* GPIO */ + PAD_NC(GPP_D1, NONE), /* GPIO */ + PAD_NC(GPP_D2, NONE), /* GPIO */ + PAD_NC(GPP_D3, NONE), /* GPIO */ + PAD_NC(GPP_D4, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ0# */ + _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ1# */ + _PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ2# */ + _PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SRCCLKREQ3# */ + _PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* BSSB_LS2_RX */ + _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NATIVE)), /* BSSB_LS2_TX */ + _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NATIVE)), /* BSSB_LS3_TX */ + _PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_NC(GPP_D15, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_D17, NONE), /* GPIO */ + PAD_NC(GPP_D18, NONE), /* GPIO */ + PAD_NC(GPP_D19, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_GSPI2_CLK_LOOPBK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* GPP_GSPI2_CLK_LOOPBK */ + + /* ------- GPIO Group vGPIO ------- */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_VGPIO_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_VGPIO_5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | (1 << 1) | 1, 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_VGPIO_6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), /* GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), /* GPP_VGPIO_8 */ + _PAD_CFG_STRUCT(GPP_VGPIO_9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_9 */ + _PAD_CFG_STRUCT(GPP_VGPIO_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), /* GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), /* GPP_VGPIO_12 */ + _PAD_CFG_STRUCT(GPP_VGPIO_13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_13 */ + _PAD_CFG_STRUCT(GPP_VGPIO_18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), /* GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), /* GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), /* GPP_VGPIO_21 */ + _PAD_CFG_STRUCT(GPP_VGPIO_22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), /* GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), /* GPP_VGPIO_24 */ + _PAD_CFG_STRUCT(GPP_VGPIO_25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), /* GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), /* GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), /* GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), /* GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), /* GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* GPP_VGPIO_37 */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + _PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* BATLOW# */ + _PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), /* ACPRESENT */ + _PAD_CFG_STRUCT(GPD2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* PWRBTN# */ + _PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_S3# */ + _PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_S4# */ + _PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_A# */ + PAD_CFG_GPO(GPD7, 1, PLTRST), /* GPIO */ + _PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SUSCLK */ + _PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_WLAN# */ + _PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 0, PWROK), /* GPIO */ + _PAD_CFG_STRUCT(GPD_INPUT3VSEL, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE), 0), /* GPD_INPUT3VSEL */ + _PAD_CFG_STRUCT(GPD_SLP_LANB, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE), 0), /* GPD_SLP_LANB */ + _PAD_CFG_STRUCT(GPD_SLP_SUSB, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE), 0), /* GPD_SLP_SUSB */ + _PAD_CFG_STRUCT(GPD_WAKEB, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* GPD_WAKEB */ + _PAD_CFG_STRUCT(GPD_DRAM_RESETB, PAD_FUNC(NF1) | PAD_BUF(TX_RX_DISABLE), 0), /* GPD_DRAM_RESETB */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* SMBCLK */ + _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* SMBDATA */ + PAD_CFG_GPO(GPP_C2, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0CLK */ + _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0DATA */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C6, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML1CLK */ + _PAD_CFG_STRUCT(GPP_C7, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML1DATA */ + PAD_NC(GPP_C8, NONE), /* GPIO */ + PAD_NC(GPP_C9, NONE), /* GPIO */ + PAD_NC(GPP_C10, NONE), /* GPIO */ + PAD_NC(GPP_C11, NONE), /* GPIO */ + PAD_NC(GPP_C12, NONE), /* GPIO */ + PAD_NC(GPP_C13, NONE), /* GPIO */ + PAD_NC(GPP_C14, NONE), /* GPIO */ + PAD_NC(GPP_C15, NONE), /* GPIO */ + PAD_NC(GPP_C16, NONE), /* GPIO */ + PAD_NC(GPP_C17, NONE), /* GPIO */ + PAD_NC(GPP_C18, NONE), /* GPIO */ + PAD_NC(GPP_C19, NONE), /* GPIO */ + PAD_NC(GPP_C20, NONE), /* GPIO */ + PAD_NC(GPP_C21, NONE), /* GPIO */ + PAD_NC(GPP_C22, NONE), /* GPIO */ + PAD_NC(GPP_C23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_F ------- */ + _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_BRI_DT */ + _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_BRI_RSP */ + _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_RGI_DT */ + _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_RGI_RSP */ + _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_RF_RESET# */ + _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* MODEM_CLKREQ */ + PAD_NC(GPP_F6, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), /* GPIO */ + PAD_NC(GPP_F8, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* BOOTMPC */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_F11, NONE), /* GPIO */ + PAD_NC(GPP_F12, NONE), /* GPIO */ + PAD_NC(GPP_F13, NONE), /* GPIO */ + PAD_NC(GPP_F14, NONE), /* GPIO */ + PAD_NC(GPP_F15, NONE), /* GPIO */ + PAD_NC(GPP_F16, NONE), /* GPIO */ + PAD_NC(GPP_F17, NONE), /* GPIO */ + PAD_NC(GPP_F18, NONE), /* GPIO */ + PAD_NC(GPP_F19, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* Reserved */ + _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* Reserved */ + PAD_NC(GPP_F22, NONE), /* GPIO */ + PAD_NC(GPP_F23, NONE), /* GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_HVCMOS ------- */ + _PAD_CFG_STRUCT(GPP_L_BKLTEN, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + _PAD_CFG_STRUCT(GPP_L_BKLTCTL, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + _PAD_CFG_STRUCT(GPP_L_VDDEN, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + _PAD_CFG_STRUCT(GPP_SYS_PWROK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* n/a */ + _PAD_CFG_STRUCT(GPP_SYS_RESETB, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* n/a */ + _PAD_CFG_STRUCT(GPP_MLK_RSTB, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */ + + /* ------- GPIO Group GPP_E ------- */ + _PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_NC(GPP_E1, NONE), /* GPIO */ + PAD_NC(GPP_E2, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_E5, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), /* GPIO */ + PAD_NC(GPP_E8, NONE), /* GPIO */ + PAD_NC(GPP_E9, NONE), /* GPIO */ + PAD_NC(GPP_E10, NONE), /* GPIO */ + PAD_NC(GPP_E11, NONE), /* GPIO */ + PAD_NC(GPP_E12, NONE), /* GPIO */ + PAD_NC(GPP_E13, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(TxDRxE)), /* DDSP_HPDA */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_E16, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_E17, NONE), /* GPIO */ + PAD_NC(GPP_E18, NATIVE), /* GPIO */ + PAD_NC(GPP_E19, NATIVE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | 1, 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* DDPA_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), /* DDPA_CTRLDATA */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + _PAD_CFG_STRUCT(GPP_R0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* HDA_BCLK */ + _PAD_CFG_STRUCT(GPP_R1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), /* HDA_SYNC */ + _PAD_CFG_STRUCT(GPP_R2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), /* HDA_SDO */ + _PAD_CFG_STRUCT(GPP_R3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), /* HDA_SDI0 */ + _PAD_CFG_STRUCT(GPP_R4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), /* HDA_RST# */ + PAD_NC(GPP_R5, NONE), /* GPIO */ + PAD_NC(GPP_R6, NONE), /* GPIO */ + PAD_NC(GPP_R7, NONE), /* GPIO */ +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/topton/adl/mainboard.c b/src/mainboard/topton/adl/mainboard.c new file mode 100644 index 0000000..5a1fef7 --- /dev/null +++ b/src/mainboard/topton/adl/mainboard.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ramstage.h> +#include "gpio.h" + +static void mainboard_init(void *chip_info) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* Disable DMI ASPM for debugging purposes. */ + params->PchLegacyIoLowLatency = 1; + params->PchDmiAspmCtrl = 0; +} diff --git a/src/mainboard/topton/adl/romstage_fsp_params.c b/src/mainboard/topton/adl/romstage_fsp_params.c new file mode 100644 index 0000000..4a7f803 --- /dev/null +++ b/src/mainboard/topton/adl/romstage_fsp_params.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fsp/api.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + static const struct mb_cfg ddr5_mem_config = { + .UserBd = BOARD_TYPE_MOBILE, + .type = MEM_TYPE_DDR5, + .ect = true, + .LpDdrDqDqsReTraining = 1, + }; + + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + }, + }; + + const bool half_populated = false; + + memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5cd2060c1635b79cb28ffe294220b63ad2bab65 Gerrit-Change-Number: 84175 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Cliff Huang (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Subrata Banik. Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84104?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... soc/intel/common/block/pmc: Add GPE1 functions - Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag. - The existing static gpe functions has been renamed with gpe0. - Add gpe1 functions. - Remove functions that enables GPE events. This is not used and should not be used during boot. BUG=362310295 TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag, boot DUT, and check if GPE1 sts bits have been printed during boot. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 72 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Cliff Huang (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 7: (9 comments) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/05ddc183_befa9a8d?us… : PS3, Line 406: pmc_clear_gpi_gpe0_status > > gpi_gpe0 means the general GPI event in GPE0. GPE1 only contains Intel's std events. […] Subrata, pmc_disable_all_gpe() is called in smm_southbridge_enable function in src/soc/intel/common/block/smm/smm.c. from SOC cpu.c, we have MP OPS: .pre_mp_smm_init = smm_initialize, <- NOTE: GPE STS bits are cleared here .post_mp_init = post_mp_init, <- NOTE: GPE EN bits are cleared here This should still be earlier enough. File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/7fa9afc6_43c665c0?us… : PS7, Line 306: 0 > this should be NULL ? as you are returning `char *` Done https://review.coreboot.org/c/coreboot/+/84104/comment/096aedda_cd23f62a?us… : PS7, Line 341: pmc_clear_gpi_gpe0_status > sure. working on this. I do a search and only the existing gpe event disabling functions need to cover GPE1 EN bits if _HAVE_GPE1. By doing this, no _gpe_function needs to be renamed outside of pmclib.c. In addition, I delete the GPE event enable functions since not used. CB should not enable these events during boot, anyways. https://review.coreboot.org/c/coreboot/+/84104/comment/93761458_c330ea5c?us… : PS7, Line 379: gpe_sts > check the NULL pointer at line 381 Done https://review.coreboot.org/c/coreboot/+/84104/comment/73efea28_9331eb8f?us… : PS7, Line 381: int i; > drop Done https://review.coreboot.org/c/coreboot/+/84104/comment/4c6fabb1_8d2596be?us… : PS7, Line 383: i > ```int i``` Done https://review.coreboot.org/c/coreboot/+/84104/comment/78107c0a_bf24424a?us… : PS7, Line 393: int i; > same Done https://review.coreboot.org/c/coreboot/+/84104/comment/caaee312_6089af7c?us… : PS7, Line 396: sts_arr = > missing NULL check ? Done https://review.coreboot.org/c/coreboot/+/84104/comment/18023c22_27025b52?us… : PS7, Line 406: if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_USE_GPE1)) { > WDYT […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 19:18:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Jamie Ryu <jamie.m.ryu(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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