coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/brox/variants/brox: remove PL4 value modification
by Sowmya Aralguppe (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Karthik Ramasubramanian, Shelley Chen, Subrata Banik, Sumeet R.P.. Sowmya Aralguppe has posted comments on this change by Sumeet R.P.. ( https://review.coreboot.org/c/coreboot/+/83662?usp=email ) Change subject: mb/google/brox/variants/brox: remove PL4 value modification ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7fbc6386769aa9f76a8665a742c97dfd790fd1d Gerrit-Change-Number: 83662 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R.P. <sumeet4linux(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sumeet R.P. <sumeet4linux(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 17:27:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox/variants/brox: update pl1_min
by Sowmya Aralguppe (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Karthik Ramasubramanian, Shelley Chen, Subrata Banik, Sumeet R.P.. Sowmya Aralguppe has posted comments on this change by Sumeet R.P.. ( https://review.coreboot.org/c/coreboot/+/83661?usp=email ) Change subject: mb/google/brox/variants/brox: update pl1_min ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I266a78806e065bf7af0d5fcad9b22ab63aa892e2 Gerrit-Change-Number: 83661 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R.P. <sumeet4linux(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sumeet R.P. <sumeet4linux(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 17:27:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Paul Menzel, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84103?usp=email ) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... Patch Set 13: (2 comments) File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/84103/comment/fd1c579d_697640df?us… : PS13, Line 144: * > drop this new line Done https://review.coreboot.org/c/coreboot/+/84103/comment/941b4e30_51b9bccd?us… : PS13, Line 146: > drop this new line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 13 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 01 Sep 2024 17:26:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
by Cliff Huang (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Paul Menzel. Hello Anil Kumar K, Bora Guvendik, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84103?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table ...................................................................... soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to enable GPE1 block. This will include GPE1 blocks to FADT with their info. BUG=362310295 TEST=boot to OS and check that FADT table include GPE1. FADT should have: GPE1 Block Address : 00001810 GPE1 Block Length : 18 GPE1 Base Offset : 80 Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/pmclib.h 3 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/84103/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/84103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6928c35b86f4a2243d58597b17b2a3a5f54271e Gerrit-Change-Number: 84103 Gerrit-PatchSet: 14 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Sowmya Aralguppe (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 19: (1 comment) File src/mainboard/google/brox/romstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/09170686_22d4ca66?us… : PS19, Line 27: MAX_NONTURBO_PERFORMANCE > Please raise a partner issue regarding this if Boot needs to be always in HFM because by default Boo […] at which stage, you are seeing "CPU brown out" ? romstage or ramstage ? I assume you are seeing Bootfrequency=2? -It happens in ramstage ( FspMultiPhaseSiInit) who is setting TurboModeDisable ? I assume croeboot can always override this. - FSP - in function VOID SetBootFrequency ( IN SI_POLICY_PPI *SiPolicyPpi ) If bootfreq is set 2 - I believe the boot will start in HPM and then switch to turbo mode (by looking at the code and logs) ..If this is not the expected behavior then we should follow it up a separate bug -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 19 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 17:23:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Sowmya Aralguppe (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 19: (3 comments) File src/mainboard/google/brox/romstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/b3065711_20e8f99f?us… : PS19, Line 27: MAX_NONTURBO_PERFORMANCE > > Yes Subrata […] Please raise a partner issue regarding this if Boot needs to be always in HFM because by default Bootfreq is set to 2 File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/6c9df5ce_595c36aa?us… : PS19, Line 57: * PL4 calculations - For USB C charger (Max Power): > > For PL4 writeback to work on all 3 different chargers it is required to change pl4 based on adapte […] I am referring PL4 writeback in depthcharge not in the kernel. are you seeing any feature gap or issue with the functionality in this implementation ? File src/mainboard/google/brox/variants/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/8ca2c032_f498eb21?us… : PS19, Line 19: .pl1_min_power = 15000, > > We had discussed that changes reverting psys calculations https://review.coreboot. […] >>>>Unable to follow what is the relation between some psys revert CL This is the CL where the PL1 limit was changed ACK - i will raise one more Patch for pl1 value change -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 19 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 17:16:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Subrata Banik (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Sowmya Aralguppe. Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 19: (3 comments) File src/mainboard/google/brox/romstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/e71fb9c6_449aa959?us… : PS19, Line 27: MAX_NONTURBO_PERFORMANCE > Yes Subrata > 1) In normal flow Bootfrequency is set to 2 by default and in ramstage turbo is enabled and I see the typical case of CPU brown out happening. at which stage, you are seeing "CPU brown out" ? romstage or ramstage ? I assume you are seeing Bootfrequency=2? > 2) If bootfrequency is set to 1 then i see TurboMode is enabled but TurboModeDisable (MSR_MISC_ENABLES) is set who is setting `TurboModeDisable` ? I assume croeboot can always override this. > 3) If bootfrequency is set to 2 then i see TurboMode is enabled but TurboModeDisable is not set > 4) In turbo.c we are enabling turbo based on IA32_MISC_ENABLE - 0x1a0 Yes, we are suppose to enable turbo for all cores. > 5) CPUstrap is read only to check if there is a mismatch in bootfreq and P1 and if reset is required My point is always CPU strap and boot freq should be set to P1 unless we plan to override with some lower value to reduce the freq File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/12d63b80_20739062?us… : PS19, Line 57: * PL4 calculations - For USB C charger (Max Power): > For PL4 writeback to work on all 3 different chargers it is required to change pl4 based on adapters. can you please explain why kernel overriding PL4 value is dependent on how coreboot calculating USB-PD capacity and overriding the Pl4 limit in low/critical boot case. I'm trying to convey that booting with lower Pl4 is still fine with an assumption that the kernel should be able to override the Pl4 after the system reaches at stable charging state. File src/mainboard/google/brox/variants/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/bf3210a8_db364ac1?us… : PS19, Line 19: .pl1_min_power = 15000, > We had discussed that changes reverting psys calculations https://review.coreboot.org/c/coreboot/+/83087 will be taken up as part this patch. If its an issue to keep it here - i will take it as a separate patch. > Please let me know you are changing the PL1 limit from 6W to 15W and I expect this can be done as part of a separate CL. Unable to follow what is the relation between some psys revert CL. if you wish to make some more clean up then do that in additional CL. I read this CL is to set the lower PL4 to meet the low/critical boot phase. -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 19 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 17:04:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
by Subrata Banik (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email ) Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake ...................................................................... Patch Set 81: (3 comments) File src/soc/intel/pantherlake/acpi/pcie.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/0b227b66_2f7e47d7?us… : PS81, Line 269: Device (RP11) : { : Name (_ADR, 0x00060002) : : OperationRegion (RPCS, PCI_Config, 0x4c, 4) : Field (RPCS, AnyAcc, NoLock, Preserve) : { : , 24, : RPPN, 8, /* Root Port Number */ : } : : Method (_PRT) : { : Return (IRQM (RPPN)) : } : } : : Device (RP12) : { : Name (_ADR, 0x00060003) : : OperationRegion (RPCS, PCI_Config, 0x4c, 4) : Field (RPCS, AnyAcc, NoLock, Preserve) : { : , 24, : RPPN, 8, /* Root Port Number */ : } : : Method (_PRT) : { : Return (IRQM (RPPN)) : } don't you need SoC Kconfig guard for PTL-H that has 10 PCIe RPs? File src/soc/intel/pantherlake/acpi/southbridge.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/c6ce4bc0_2478a6d2?us… : PS81, Line 11: #if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB) can we have a PTL SoC that can decide to drop PCD P2SB support if not then I would default select ioe_pcr.asl. File src/soc/intel/pantherlake/acpi/tcss_xhci.asl: https://review.coreboot.org/c/coreboot/+/83772/comment/8473b0bf_78ba9d01?us… : PS81, Line 37: // D3COLD_SUPPORT use `/* ... */` -- To view, visit https://review.coreboot.org/c/coreboot/+/83772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15 Gerrit-Change-Number: 83772 Gerrit-PatchSet: 81 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 15:04:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Sowmya Aralguppe (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 19: (4 comments) File src/mainboard/google/brox/romstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/0193c6b0_f2ac37c6?us… : PS19, Line 27: MAX_NONTURBO_PERFORMANCE > did you check BootFrequency UPD dump w/o and w/ this CL? […] Yes Subrata 1) In normal flow Bootfrequency is set to 2 by default and in ramstage turbo is enabled and I see the typical case of CPU brown out happening. 2) If bootfrequency is set to 1 then i see TurboMode is enabled but TurboModeDisable (MSR_MISC_ENABLES) is set 3) If bootfrequency is set to 2 then i see TurboMode is enabled but TurboModeDisable is not set 4) In turbo.c we are enabling turbo based on IA32_MISC_ENABLE - 0x1a0 5) CPUstrap is read only to check if there is a mismatch in bootfreq and P1 and if reset is required File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/0ced2c1b_ed133a0d?us… : PS19, Line 57: * PL4 calculations - For USB C charger (Max Power): > if we know that OS can override the PL4 table dynamically and we only need to set a lower P4 when ba […] For PL4 writeback this is required .I tried keeping a single value - it is not working for all 3 adapters. I followed from how shelly had implemented psys for different power ratings .These values have been tested thoroughly for all corner cases . IMO we can keep it like this - if we are unable to write pl4 back in coreboot - then we can make it static i feel. https://review.coreboot.org/c/coreboot/+/83752/comment/fffee419_6939275b?us… : PS19, Line 57: * PL4 calculations - For USB C charger (Max Power): > if we know that OS can override the PL4 table dynamically and we only need to set a lower P4 when ba […] For PL4 writeback to work on all 3 different chargers it is required to change pl4 based on adapters. File src/mainboard/google/brox/variants/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/505acb21_ba75b128?us… : PS19, Line 19: .pl1_min_power = 15000, > this change should be part of separate CL We had discussed that changes reverting psys calculations https://review.coreboot.org/c/coreboot/+/83087 will be taken up as part this patch. If its an issue to keep it here - i will take it as a separate patch. Please let me know -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 19 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 15:03:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 71: (25 comments) File src/soc/intel/pantherlake/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83798/comment/44828877_eab3f450?us… : PS71, Line 48: ramstage-y += soc_info.c can you please follow the order ? File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/cc846f9d_99bd296f?us… : PS71, Line 126: if (!initialized) { why not bail out early ? w/o need to give one extra tab? ``` if (initialized) return map; config_t *config = config_of_soc(); if (config == NULL) { printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); return NULL; } .... .... ``` https://review.coreboot.org/c/coreboot/+/83798/comment/0fcc849f_23c9ff99?us… : PS71, Line 251: I believe it would fit in line above? https://review.coreboot.org/c/coreboot/+/83798/comment/fe5d1e44_facc44f7?us… : PS71, Line 262: why empty line? https://review.coreboot.org/c/coreboot/+/83798/comment/4238e4f3_443b30fe?us… : PS71, Line 280: same https://review.coreboot.org/c/coreboot/+/83798/comment/8e550794_00c0ec63?us… : PS71, Line 286: V_P2SB_CFG_IBDF_FUNC this would fit into line above https://review.coreboot.org/c/coreboot/+/83798/comment/f7e6764d_f7d0d0e2?us… : PS71, Line 287: current += acpi_create_dmar_ds_msi_hpet(current, : 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, : V_P2SB_CFG_HBDF_FUNC); try to reflow the line till 96 char https://review.coreboot.org/c/coreboot/+/83798/comment/8bd14b8a_df8e6460?us… : PS71, Line 296: current += acpi_create_dmar_rmrr(current, 0, : sa_get_gsm_base(), sa_get_tolud_base() - 1); : current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); in all previous code you have given one empty line between `acpi_create_dmar_drhd` and `acpi_create_dmar_ds_pci`. now this line not following the same practice. try to be consistent in you have added one empty line for better code readability then use here too ? https://review.coreboot.org/c/coreboot/+/83798/comment/9f552263_021753b0?us… : PS71, Line 303: why empty line https://review.coreboot.org/c/coreboot/+/83798/comment/ee610d4e_c6ade57f?us… : PS71, Line 305: : current += acpi_create_dmar_satc(current, ATC_REQUIRED, 0); : current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); same feedback as above File src/soc/intel/pantherlake/chip.h: https://review.coreboot.org/c/coreboot/+/83798/comment/2408a0ec_67ccdd13?us… : PS71, Line 60: TDP_45W = 45 nit ``` TDP_45W = 45, ``` File src/soc/intel/pantherlake/chip.c: https://review.coreboot.org/c/coreboot/+/83798/comment/15af1fdb_f98bf372?us… : PS71, Line 80: please use consistent tab https://review.coreboot.org/c/coreboot/+/83798/comment/8360cfeb_09153f97?us… : PS71, Line 202: if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) || : CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) { I hope it would fit within char < 96 File src/soc/intel/pantherlake/elog.c: https://review.coreboot.org/c/coreboot/+/83798/comment/a009a3db_05d6844d?us… : PS71, Line 140: should we be adding GPE1 as well here? @cliff.huang@intel.com File src/soc/intel/pantherlake/include/soc/cpu.h: https://review.coreboot.org/c/coreboot/+/83798/comment/ba53ae8a_e9d06ba8?us… : PS71, Line 7: #define C1_LATENCY 1 : #define C6_LATENCY 127 : #define C7_LATENCY 253 : #define C8_LATENCY 260 : #define C9_LATENCY 487 : #define C10_LATENCY 1048 same https://review.coreboot.org/c/coreboot/+/83798/comment/23f33192_b191c1d0?us… : PS71, Line 15: #define C1_POWER 0x3e8 : #define C6_POWER 0x15e : #define C7_POWER 0xc8 : #define C8_POWER 0xc8 : #define C9_POWER 0xc8 : #define C10_POWER 0xc8 please confirm the applicability and authenticity of these values for PTL SoC. File src/soc/intel/pantherlake/include/soc/dptf.h: https://review.coreboot.org/c/coreboot/+/83798/comment/fbc3d7a2_b31c1bfa?us… : PS71, Line 6: drop one empty line File src/soc/intel/pantherlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/83798/comment/724201d4_ad698da1?us… : PS71, Line 23: DMI ``` /* Add Dummy Entry to cater common/block/acpi/acpi/northbridge.asl */ ``` File src/soc/intel/pantherlake/pmc.c: https://review.coreboot.org/c/coreboot/+/83798/comment/878a5db3_c392c15e?us… : PS71, Line 29: reg can you please check if the `reg` is non-zero ? File src/soc/intel/pantherlake/pmutil.c: https://review.coreboot.org/c/coreboot/+/83798/comment/8602614e_08b1dbf2?us… : PS71, Line 110: should we add GPE1 as well here @cliff.huang@intel.com https://review.coreboot.org/c/coreboot/+/83798/comment/b557beab_73ba2c5b?us… : PS71, Line 152: please add a NULL check File src/soc/intel/pantherlake/retimer.c: https://review.coreboot.org/c/coreboot/+/83798/comment/2dc4699b_bf1b3e66?us… : PS71, Line 19: : for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) { ``` for (uint8_t i = 0, int ec_port = 0; i < MAX_TYPE_C_PORTS; i++) { ``` File src/soc/intel/pantherlake/soundwire.c: https://review.coreboot.org/c/coreboot/+/83798/comment/b070fb08_eb02ef6b?us… : PS71, Line 38: 0x40000000, can we use a macro ? if this is PCI device (like audio controller), then try to use pre-defined macro File src/soc/intel/pantherlake/systemagent.c: https://review.coreboot.org/c/coreboot/+/83798/comment/5e65de34_d2e146b5?us… : PS71, Line 33: // PCH_PRESERVERD covers: : // TraceHub SW BAR, PMC MBAR, SPI BAR0, SerialIo BAR in ACPI mode : // eSPI LGMR BAR, eSPI2 SEGMR BAR, TraceHub MTB BAR, TraceHub FW BAR : // IOE PMC BAR, Tracehub RTIT BAR (SOC), HECI{1,2,3} BAR0 : // see fsp/ClientOneSiliconPkg/Fru/MtlSoc/Include/PchReservedResources.h I understand that you are concerned about the accessibility of this code. I will remove the comment so that it is no longer visible to everyone. File src/soc/intel/pantherlake/tcss.c: https://review.coreboot.org/c/coreboot/+/83798/comment/892df576_4a3257fc?us… : PS48, Line 6: const struct soc_tcss_ops tcss_ops = { > Hi Subrata,we will be requiring this, since TCSS I/O Manager is above 4GB. > > const struct soc_tcss_ops tcss_ops = { > .configure_aux_bias_pads = ioe_tcss_configure_aux_bias_pads_sbi, > .valid_tbt_auth = ioe_tcss_valid_tbt_auth, > }; if you need this then please try to implement it w/o keeping skeleton code ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 71 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 15:01:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com>

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coreboot-gerrit September 2024