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Hello Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Rishika Raj, Ronak Kanabar, Shelley Chen, Subrata Banik, build bot (Jenkins),
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
mb/google/brox: Fix booting to kernel without battery
When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/mainboard/google/brox/romstage.c
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/brox/ramstage.c
M src/soc/intel/alderlake/chip.h
4 files changed, 81 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83752/20
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Change subject: soc/intel/common/block/acpi: Add GPE1 blocks to ACPI FADT table
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS14:
Please take care of below comments below as part of PTL ramstage CLs
1. https://review.coreboot.org/c/coreboot/+/83798/comment/a009a3db_05d6844d/
2. https://review.coreboot.org/c/coreboot/+/83798/comment/8602614e_08b1dbf2/
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 19:
(1 comment)
File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/f036d90c_544ffc50?us… :
PS19, Line 57: * PL4 calculations - For USB C charger (Max Power):
> > I am referring PL4 writeback in depthcharge not in the kernel. […]
I was able to write it in depthcharge for an older version of the kernel .
Writing in the OS will add complexity since we need to pass the info that the pl4 has been reduced and based on that it should increase .
The problem statement and ARs were discussed in the Brox call and a partner bug was raised - https://partnerissuetracker.corp.google.com/issues/362371596
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Change subject: mb/google/brox/variants/brox: remove PL4 value modification
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83662/comment/6503c3c3_b9c09ed5?us… :
PS1, Line 8:
: Remove PL4 value modification based on PsysPL3 valuei.
:
the motivation not clear? can you please give a reason why it existed before and why you are not removing this code ?
trying to understand if this code ever intended to solve any problem ?
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 19:
(2 comments)
File src/mainboard/google/brox/romstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/8b21c153_184572f6?us… :
PS19, Line 27: MAX_NONTURBO_PERFORMANCE
> at which stage, you are seeing "CPU brown out" ? romstage or ramstage ? I assume you are seeing Bootfrequency=2?
> -It happens in ramstage ( FspMultiPhaseSiInit)
The BSP always boots at the HFM, or P1 frequency, which is aligned with the CPU soft strap. I don't believe we need to file a bug to align with this expectation. You can dump the perf MSR to check the current frequency and compare it to the HFM.
Later, during the ramstage, when we enable Turbo and try to configure Turbo for all APs, we need to draw more power to switch to the supported turbo max.
Since the battery is unable to draw enough power, the CPU browns out.
The best solution to this situation would be to ensure that the BIOS is not enabling Turbo or the BSP frequency is limited to HFM/P1 max.
What I am saying is that the boot frequency override only makes sense at the ramstage and not at the romstage because we are already booting using P1/HFM until the romstage. This UPD is used to prevent the BSP from switching to the Turbo frequency, knowing that the power envelope is not sufficient to keep Turbo enabled.
> who is setting TurboModeDisable ? I assume croeboot can always override this.
> - FSP - in function VOID SetBootFrequency (
> IN SI_POLICY_PPI *SiPolicyPpi
> )
> If bootfreq is set 2 - I believe the boot will start in HPM and then switch to turbo mode (by looking at the code and logs) ..If this is not the expected behavior then we should follow it up a separate bug
Please read my explanation above, I'm insisting this UPD is more like ramstage specific UPD rather getting used in romstage. Because turbo freq is what ideally we wish to avoid to switch for BSP unless we have ample supply.
File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/d8a25daf_9ce1efd7?us… :
PS19, Line 57: * PL4 calculations - For USB C charger (Max Power):
> I am referring PL4 writeback in depthcharge not in the kernel. are you seeing any feature gap or issue with the functionality in this implementation ?
I am repeating my questions. Why do you believe that overriding the PL4 at depthcharge would be sufficient to restore the original PL4 limit? Our boot time is less than or equal to 1 second, which is far too brief for the system to reach a stable charged state and restore the original PL4 limit.
I would prefer to avoid overriding PL4 from DC and rely on the kernel to restore the PL4's original value after we have reached a stable charge state.
Overriding PL4 from depthcharge may cause the same CPI brownout problem if there is insufficient fuel (which I would like to avoid). I believe I mentioned this during the call as well.
```
Low battery - Working fine with power button press
Able to write back PL4 after exiting depthcharge (needs to validated on different boards) - seems to be sporadic
```
this is what you have mentioned during the previous call that overriding PL4 from depthcharge has a corner case as well.
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Change subject: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support
......................................................................
Patch Set 2:
(4 comments)
Patchset:
PS2:
Hi!
File src/mainboard/hardkernel/odroid-h4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/83979/comment/3776b072_e1583d73?us… :
PS2, Line 17: register "s0ix_enable" = "1"
It's unlikely that you'll get s0ix working with IT8613E unfortunately. Worth giving it a try though 😜
https://review.coreboot.org/c/coreboot/+/83979/comment/1e015a21_34d9d0e1?us… :
PS2, Line 84: # .clk_src = 2,
On most ADL-N systems, M.2 NVME is connected to Clock Source 0.
It's the same for firewall I'm currently porting (Topton N100).
Hopefully this will help you get NVME working 😊
https://www.pollin.de/productdownloads/D811684D.PDFhttps://review.coreboot.org/c/coreboot/+/83979/comment/b427c1b2_cec9c256?us… :
PS2, Line 141: device pnp 2e.6 on end # Mouse
From what I can see, this board doesn't have PS/2 ports. It's safe to disable LDN5 and LDN6
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