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Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email )
Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 55:
(11 comments)
File src/soc/intel/pantherlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/83789/comment/faa6851c_d3b6a6cc?us… :
PS17, Line 55:
: Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
> Subrata, […]
Acknowledged
File src/soc/intel/pantherlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/83789/comment/a6296c6b_5a379ed9?us… :
PS55, Line 18: {
one space
https://review.coreboot.org/c/coreboot/+/83789/comment/9be5a82c_12828168?us… :
PS55, Line 20: // Interrupt IRQ_EN
remove this comment
https://review.coreboot.org/c/coreboot/+/83789/comment/e44a6de2_c839a5de?us… :
PS55, Line 28: //
use `/* ... */` comment style
https://review.coreboot.org/c/coreboot/+/83789/comment/73e8a168_03cf9ed5?us… :
PS55, Line 58: //
remove this comment
https://review.coreboot.org/c/coreboot/+/83789/comment/afcd4425_c0e055f1?us… :
PS55, Line 60: /* Device Properties for _DSD */,
don't need this. if you would like to explain what is special about this GUID, then please use the comment section to specify here.
Commenting for one GPIO comm is enough IMO
https://review.coreboot.org/c/coreboot/+/83789/comment/e457806b_ffb08404?us… :
PS55, Line 84: 0x10
can you please help me to understand what this field actually implies to ?
https://review.coreboot.org/c/coreboot/+/83789/comment/9f9012f1_c77546e2?us… :
PS55, Line 135: GPPV
may be worth adding a comment saying, this section explains each GPIO bank, for example: GPIO_0 COMM has two GPIO bank like GPP_V and GPP_C.
File src/soc/intel/pantherlake/include/soc/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/83789/comment/98686cb9_d222aec7?us… :
PS55, Line 256:
no need to have an empty line
https://review.coreboot.org/c/coreboot/+/83789/comment/47873f07_bab4e366?us… :
PS55, Line 257: GPP_V
can you use `_start_` in between to make it clear?
for example:
`GPP_V_START_OFFSET`
File src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/83789/comment/c251470b_e67cc33e?us… :
PS55, Line 36: Community0
is there any specific syntax to follow here?
if not then can you please use `Community 0`
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 19:
(3 comments)
File src/mainboard/google/brox/romstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/143c35ab_b854d321?us… :
PS19, Line 27: MAX_NONTURBO_PERFORMANCE
did you check BootFrequency UPD dump w/o and w/ this CL?
If Cpu Strap already has boot with P1 freq set then I don't follow how this UPD is helpful. Ideally this UPD only comes to the picture if Cpu strap is not set to P1 freq and you wish to override it with P1 freq. Otherwise we always want BIOS to boot with P1 aka HFM and then switch to Turbo after booted to OS.
File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/6a4abf9b_1b746769?us… :
PS19, Line 57: * PL4 calculations - For USB C charger (Max Power):
if we know that OS can override the PL4 table dynamically and we only need to set a lower P4 when battery is not present. Then, it would be good to boot with a static configuration which is safest and generically applicable.
Adding logic to configure PL4 based on USB-PD capacity seems overdoing for BIOS.
File src/mainboard/google/brox/variants/brox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/c6fc25bd_dbb7d884?us… :
PS19, Line 19: .pl1_min_power = 15000,
this change should be part of separate CL
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Change subject: drivers/efi/uefi_capsules.c: coalesce and store UEFI capsules
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Nice work. Please paste the new log lines in here for the record.
Here's the log after posting a capsule:
```
...
[INFO ] capsules: capsule block #0 at 0x7f52fa18.
[SPEW ] EFIVARS: UEFI FV with size 262144 found
[SPEW ] EFIVARS: UEFI variable store with size 65464 found
[SPEW ] Found variable with state 3f and GUID: d9bee56e-75dc-49d9-b4d7b534210f637a
...
[INFO ] capsules: processing 1 capsule block(s).
[SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa18.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa20.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x0000001c bytes at 0x7d35b018.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa28.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa30.
[SPEW ] capsules: no need to map anything.
[DEBUG] capsules: chained capsule blocks.
[SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa18.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa20.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa28.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa30.
[SPEW ] capsules: no need to map anything.
[DEBUG] capsules: reserved capsule blocks.
[DEBUG] capsules: coalescing capsules data @ 0x7ed15000.
[SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa18.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa20.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x0000001c bytes at 0x7d35b018.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00200000 bytes at 0x7d35b018.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00200000 bytes at 0x7d55b018.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00200000 bytes at 0x7d75b018.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00200000 bytes at 0x7d95b018.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00019dfb bytes at 0x7db5b018.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa28.
[SPEW ] capsules: no need to map anything.
[SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa30.
[SPEW ] capsules: no need to map anything.
[INFO ] capsules: found 1 capsule(s).
[DEBUG] BS: BS_DEV_INIT exit times (exec / console): 1 / 36 ms
[INFO ] Enabled capsule update SMI handler
[INFO ] Finalize devices...
[INFO ] Devices finalized
...
[DEBUG] Writing coreboot table at 0x7fd66000
[INFO ] capsules: reserving capsules data @ 0x7ed15000.
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
[DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG] 3. 0000000000100000-000000007ed14fff: RAM
[DEBUG] 4. 000000007ed15000-000000007f52efff: RESERVED
[DEBUG] 5. 000000007f52f000-000000007fd25fff: RAM
[DEBUG] 6. 000000007fd26000-000000007fd7efff: CONFIGURATION TABLES
[DEBUG] 7. 000000007fd7f000-000000007feccfff: RAMSTAGE
[DEBUG] 8. 000000007fecd000-000000007fefffff: CONFIGURATION TABLES
[DEBUG] 9. 000000007ff00000-000000007fffffff: RESERVED
[DEBUG] 10. 00000000b0000000-00000000bfffffff: RESERVED
[DEBUG] 11. 0000000100000000-000000017fffffff: RAM
[INFO ] capsules: publishing a capsule @ 0x7ed15000.
...
```
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Hello Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Rishika Raj, Ronak Kanabar, Shelley Chen, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83752?usp=email
to look at the new patch set (#19).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
mb/google/brox: Fix booting to kernel without battery
When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance. For boot with battery
increase PL1 min value to 15 watts.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/mainboard/google/brox/romstage.c
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/brox/ramstage.c
M src/soc/intel/alderlake/chip.h
4 files changed, 83 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83752/19
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Change subject: src/include/cpu/x86: Add Extended Feature Enable Register Macro
......................................................................
Patch Set 5:
(1 comment)
File src/include/cpu/x86/msr.h:
https://review.coreboot.org/c/coreboot/+/84174/comment/5eb5a9b7_0c2faa2a?us… :
PS4, Line 64:
> Hi, these bits belogs to (POWER_CTL) – Offset 1fc
> Indent w/ one space will align with Offset 0x1F8.
if these bits belong to offset 0x1fc then you should have moved those bit-definitions inside https://github.com/coreboot/coreboot/blob/main/src/soc/intel/common/block/i…
what motivates you to define 0x1fc bit-fields into x84/MSR.h when the same definition exists into intelblock?
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