coreboot-gerrit September 2024

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 71: (25 comments) File src/soc/intel/pantherlake/Makefile.mk: https://review.coreboot.org/c/coreboot/+/83798/comment/44828877_eab3f450?us… : PS71, Line 48: ramstage-y += soc_info.c can you please follow the order ? File src/soc/intel/pantherlake/acpi.c: https://review.coreboot.org/c/coreboot/+/83798/comment/cc846f9d_99bd296f?us… : PS71, Line 126: if (!initialized) { why not bail out early ? w/o need to give one extra tab? ``` if (initialized) return map; config_t *config = config_of_soc(); if (config == NULL) { printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); return NULL; } .... .... ``` https://review.coreboot.org/c/coreboot/+/83798/comment/0fcc849f_23c9ff99?us… : PS71, Line 251: I believe it would fit in line above? https://review.coreboot.org/c/coreboot/+/83798/comment/fe5d1e44_facc44f7?us… : PS71, Line 262: why empty line? https://review.coreboot.org/c/coreboot/+/83798/comment/4238e4f3_443b30fe?us… : PS71, Line 280: same https://review.coreboot.org/c/coreboot/+/83798/comment/8e550794_00c0ec63?us… : PS71, Line 286: V_P2SB_CFG_IBDF_FUNC this would fit into line above https://review.coreboot.org/c/coreboot/+/83798/comment/f7e6764d_f7d0d0e2?us… : PS71, Line 287: current += acpi_create_dmar_ds_msi_hpet(current, : 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, : V_P2SB_CFG_HBDF_FUNC); try to reflow the line till 96 char https://review.coreboot.org/c/coreboot/+/83798/comment/8bd14b8a_df8e6460?us… : PS71, Line 296: current += acpi_create_dmar_rmrr(current, 0, : sa_get_gsm_base(), sa_get_tolud_base() - 1); : current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); in all previous code you have given one empty line between `acpi_create_dmar_drhd` and `acpi_create_dmar_ds_pci`. now this line not following the same practice. try to be consistent in you have added one empty line for better code readability then use here too ? https://review.coreboot.org/c/coreboot/+/83798/comment/9f552263_021753b0?us… : PS71, Line 303: why empty line https://review.coreboot.org/c/coreboot/+/83798/comment/ee610d4e_c6ade57f?us… : PS71, Line 305: : current += acpi_create_dmar_satc(current, ATC_REQUIRED, 0); : current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); same feedback as above File src/soc/intel/pantherlake/chip.h: https://review.coreboot.org/c/coreboot/+/83798/comment/2408a0ec_67ccdd13?us… : PS71, Line 60: TDP_45W = 45 nit ``` TDP_45W = 45, ``` File src/soc/intel/pantherlake/chip.c: https://review.coreboot.org/c/coreboot/+/83798/comment/15af1fdb_f98bf372?us… : PS71, Line 80: please use consistent tab https://review.coreboot.org/c/coreboot/+/83798/comment/8360cfeb_09153f97?us… : PS71, Line 202: if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) || : CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) { I hope it would fit within char < 96 File src/soc/intel/pantherlake/elog.c: https://review.coreboot.org/c/coreboot/+/83798/comment/a009a3db_05d6844d?us… : PS71, Line 140: should we be adding GPE1 as well here? @cliff.huang@intel.com File src/soc/intel/pantherlake/include/soc/cpu.h: https://review.coreboot.org/c/coreboot/+/83798/comment/ba53ae8a_e9d06ba8?us… : PS71, Line 7: #define C1_LATENCY 1 : #define C6_LATENCY 127 : #define C7_LATENCY 253 : #define C8_LATENCY 260 : #define C9_LATENCY 487 : #define C10_LATENCY 1048 same https://review.coreboot.org/c/coreboot/+/83798/comment/23f33192_b191c1d0?us… : PS71, Line 15: #define C1_POWER 0x3e8 : #define C6_POWER 0x15e : #define C7_POWER 0xc8 : #define C8_POWER 0xc8 : #define C9_POWER 0xc8 : #define C10_POWER 0xc8 please confirm the applicability and authenticity of these values for PTL SoC. File src/soc/intel/pantherlake/include/soc/dptf.h: https://review.coreboot.org/c/coreboot/+/83798/comment/fbc3d7a2_b31c1bfa?us… : PS71, Line 6: drop one empty line File src/soc/intel/pantherlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/83798/comment/724201d4_ad698da1?us… : PS71, Line 23: DMI ``` /* Add Dummy Entry to cater common/block/acpi/acpi/northbridge.asl */ ``` File src/soc/intel/pantherlake/pmc.c: https://review.coreboot.org/c/coreboot/+/83798/comment/878a5db3_c392c15e?us… : PS71, Line 29: reg can you please check if the `reg` is non-zero ? File src/soc/intel/pantherlake/pmutil.c: https://review.coreboot.org/c/coreboot/+/83798/comment/8602614e_08b1dbf2?us… : PS71, Line 110: should we add GPE1 as well here @cliff.huang@intel.com https://review.coreboot.org/c/coreboot/+/83798/comment/b557beab_73ba2c5b?us… : PS71, Line 152: please add a NULL check File src/soc/intel/pantherlake/retimer.c: https://review.coreboot.org/c/coreboot/+/83798/comment/2dc4699b_bf1b3e66?us… : PS71, Line 19: : for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) { ``` for (uint8_t i = 0, int ec_port = 0; i < MAX_TYPE_C_PORTS; i++) { ``` File src/soc/intel/pantherlake/soundwire.c: https://review.coreboot.org/c/coreboot/+/83798/comment/b070fb08_eb02ef6b?us… : PS71, Line 38: 0x40000000, can we use a macro ? if this is PCI device (like audio controller), then try to use pre-defined macro File src/soc/intel/pantherlake/systemagent.c: https://review.coreboot.org/c/coreboot/+/83798/comment/5e65de34_d2e146b5?us… : PS71, Line 33: // PCH_PRESERVERD covers: : // TraceHub SW BAR, PMC MBAR, SPI BAR0, SerialIo BAR in ACPI mode : // eSPI LGMR BAR, eSPI2 SEGMR BAR, TraceHub MTB BAR, TraceHub FW BAR : // IOE PMC BAR, Tracehub RTIT BAR (SOC), HECI{1,2,3} BAR0 : // see fsp/ClientOneSiliconPkg/Fru/MtlSoc/Include/PchReservedResources.h I understand that you are concerned about the accessibility of this code. I will remove the comment so that it is no longer visible to everyone. File src/soc/intel/pantherlake/tcss.c: https://review.coreboot.org/c/coreboot/+/83798/comment/892df576_4a3257fc?us… : PS48, Line 6: const struct soc_tcss_ops tcss_ops = { > Hi Subrata,we will be requiring this, since TCSS I/O Manager is above 4GB. > > const struct soc_tcss_ops tcss_ops = { > .configure_aux_bias_pads = ioe_tcss_configure_aux_bias_pads_sbi, > .valid_tbt_auth = ioe_tcss_valid_tbt_auth, > }; if you need this then please try to implement it w/o keeping skeleton code ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 71 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 15:01:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Subrata Banik (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email ) Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... Patch Set 55: (11 comments) File src/soc/intel/pantherlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/83789/comment/faa6851c_d3b6a6cc?us… : PS17, Line 55: : Name (_DSD, Package (0x04) // _DSD: Device-Specific Data > Subrata, […] Acknowledged File src/soc/intel/pantherlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/83789/comment/a6296c6b_5a379ed9?us… : PS55, Line 18: { one space https://review.coreboot.org/c/coreboot/+/83789/comment/9be5a82c_12828168?us… : PS55, Line 20: // Interrupt IRQ_EN remove this comment https://review.coreboot.org/c/coreboot/+/83789/comment/e44a6de2_c839a5de?us… : PS55, Line 28: // use `/* ... */` comment style https://review.coreboot.org/c/coreboot/+/83789/comment/73e8a168_03cf9ed5?us… : PS55, Line 58: // remove this comment https://review.coreboot.org/c/coreboot/+/83789/comment/afcd4425_c0e055f1?us… : PS55, Line 60: /* Device Properties for _DSD */, don't need this. if you would like to explain what is special about this GUID, then please use the comment section to specify here. Commenting for one GPIO comm is enough IMO https://review.coreboot.org/c/coreboot/+/83789/comment/e457806b_ffb08404?us… : PS55, Line 84: 0x10 can you please help me to understand what this field actually implies to ? https://review.coreboot.org/c/coreboot/+/83789/comment/9f9012f1_c77546e2?us… : PS55, Line 135: GPPV may be worth adding a comment saying, this section explains each GPIO bank, for example: GPIO_0 COMM has two GPIO bank like GPP_V and GPP_C. File src/soc/intel/pantherlake/include/soc/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/83789/comment/98686cb9_d222aec7?us… : PS55, Line 256: no need to have an empty line https://review.coreboot.org/c/coreboot/+/83789/comment/47873f07_bab4e366?us… : PS55, Line 257: GPP_V can you use `_start_` in between to make it clear? for example: `GPP_V_START_OFFSET` File src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h: https://review.coreboot.org/c/coreboot/+/83789/comment/c251470b_e67cc33e?us… : PS55, Line 36: Community0 is there any specific syntax to follow here? if not then can you please use `Community 0` -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 55 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 01 Sep 2024 14:21:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Subrata Banik (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Sowmya Aralguppe. Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 19: (3 comments) File src/mainboard/google/brox/romstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/143c35ab_b854d321?us… : PS19, Line 27: MAX_NONTURBO_PERFORMANCE did you check BootFrequency UPD dump w/o and w/ this CL? If Cpu Strap already has boot with P1 freq set then I don't follow how this UPD is helpful. Ideally this UPD only comes to the picture if Cpu strap is not set to P1 freq and you wish to override it with P1 freq. Otherwise we always want BIOS to boot with P1 aka HFM and then switch to Turbo after booted to OS. File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/6a4abf9b_1b746769?us… : PS19, Line 57: * PL4 calculations - For USB C charger (Max Power): if we know that OS can override the PL4 table dynamically and we only need to set a lower P4 when battery is not present. Then, it would be good to boot with a static configuration which is safest and generically applicable. Adding logic to configure PL4 based on USB-PD capacity seems overdoing for BIOS. File src/mainboard/google/brox/variants/brox/ramstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/c6fc25bd_dbb7d884?us… : PS19, Line 19: .pl1_min_power = 15000, this change should be part of separate CL -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 19 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 13:56:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: drivers/efi/uefi_capsules.c: coalesce and store UEFI capsules
by Sergii Dmytruk (Code Review) 01 Sep '24

01 Sep '24

Sergii Dmytruk has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83422?usp=email ) Change subject: drivers/efi/uefi_capsules.c: coalesce and store UEFI capsules ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > Nice work. Please paste the new log lines in here for the record. Here's the log after posting a capsule: ``` ... [INFO ] capsules: capsule block #0 at 0x7f52fa18. [SPEW ] EFIVARS: UEFI FV with size 262144 found [SPEW ] EFIVARS: UEFI variable store with size 65464 found [SPEW ] Found variable with state 3f and GUID: d9bee56e-75dc-49d9-b4d7b534210f637a ... [INFO ] capsules: processing 1 capsule block(s). [SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa18. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa20. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x0000001c bytes at 0x7d35b018. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa28. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa30. [SPEW ] capsules: no need to map anything. [DEBUG] capsules: chained capsule blocks. [SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa18. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa20. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa28. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa30. [SPEW ] capsules: no need to map anything. [DEBUG] capsules: reserved capsule blocks. [DEBUG] capsules: coalescing capsules data @ 0x7ed15000. [SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa18. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa20. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x0000001c bytes at 0x7d35b018. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00200000 bytes at 0x7d35b018. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00200000 bytes at 0x7d55b018. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00200000 bytes at 0x7d75b018. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00200000 bytes at 0x7d95b018. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00019dfb bytes at 0x7db5b018. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa28. [SPEW ] capsules: no need to map anything. [SPEW ] capsules: mapping 0x00000008 bytes at 0x7f52fa30. [SPEW ] capsules: no need to map anything. [INFO ] capsules: found 1 capsule(s). [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 1 / 36 ms [INFO ] Enabled capsule update SMI handler [INFO ] Finalize devices... [INFO ] Devices finalized ... [DEBUG] Writing coreboot table at 0x7fd66000 [INFO ] capsules: reserving capsules data @ 0x7ed15000. [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES [DEBUG] 1. 0000000000001000-000000000009ffff: RAM [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED [DEBUG] 3. 0000000000100000-000000007ed14fff: RAM [DEBUG] 4. 000000007ed15000-000000007f52efff: RESERVED [DEBUG] 5. 000000007f52f000-000000007fd25fff: RAM [DEBUG] 6. 000000007fd26000-000000007fd7efff: CONFIGURATION TABLES [DEBUG] 7. 000000007fd7f000-000000007feccfff: RAMSTAGE [DEBUG] 8. 000000007fecd000-000000007fefffff: CONFIGURATION TABLES [DEBUG] 9. 000000007ff00000-000000007fffffff: RESERVED [DEBUG] 10. 00000000b0000000-00000000bfffffff: RESERVED [DEBUG] 11. 0000000100000000-000000017fffffff: RAM [INFO ] capsules: publishing a capsule @ 0x7ed15000. ... ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/83422?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I162d678ae5c504906084b59c1a8d8c26dadb9433 Gerrit-Change-Number: 83422 Gerrit-PatchSet: 6 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sun, 01 Sep 2024 12:56:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Sowmya Aralguppe (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email ) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... Patch Set 19: (2 comments) File src/mainboard/google/brox/romstage.c: https://review.coreboot.org/c/coreboot/+/83752/comment/ae554d68_6e6feda9?us… : PS17, Line 26: (!google_chromeec_is_battery_present_and_above_critical_threshold())) { > We dont need the extra parentheses here. Done https://review.coreboot.org/c/coreboot/+/83752/comment/adfec120_0f3140c9?us… : PS17, Line 28: printk(BIOS_DEBUG, "Boot Frequency is set to %d\n", mem_cfg->BootFrequency); > BootFrequency is unsigned int. Please use %u instead of %d format specifier. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 19 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 12:51:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com>

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[M] Change in coreboot[main]: mb/google/brox: Fix booting to kernel without battery
by Sowmya Aralguppe (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Rishika Raj, Ronak Kanabar, Shelley Chen, Sowmya Aralguppe, Sowmya Aralguppe, Subrata Banik. Hello Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Krishna P Bhat D, Nick Vaccaro, Rishika Raj, Ronak Kanabar, Shelley Chen, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83752?usp=email to look at the new patch set (#19). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/brox: Fix booting to kernel without battery ...................................................................... mb/google/brox: Fix booting to kernel without battery When battery is disconnected and only adaptor is connected higher PL2 power draw causes cpu brown out and system does not boot to kernel. To avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome power spikes from SoC during boot. Remove Psys implementation as it impacts active state platform performance. For boot with battery increase PL1 min value to 15 watts. BUG=b:335046538,b:329722827 BRANCH=None TEST=Able to successfully boot on 3 different Brox proto2 SKU1 and SKU2 boards with 65W, 45W and 30W adaptors for 3 iterations of cold boot. Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> --- M src/mainboard/google/brox/romstage.c M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c M src/mainboard/google/brox/variants/brox/ramstage.c M src/soc/intel/alderlake/chip.h 4 files changed, 83 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83752/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/83752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433 Gerrit-Change-Number: 83752 Gerrit-PatchSet: 19 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com>

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[XS] Change in coreboot[main]: src/include/cpu/x86: Add Extended Feature Enable Register Macro
by Subrata Banik (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Jérémy Compostella, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84174?usp=email ) Change subject: src/include/cpu/x86: Add Extended Feature Enable Register Macro ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: same feedback why this CL is not at main tot and inside PTL recipe ? -- To view, visit https://review.coreboot.org/c/coreboot/+/84174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Gerrit-Change-Number: 84174 Gerrit-PatchSet: 5 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 09:04:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: src/include/cpu/x86: Add Extended Feature Enable Register Macro
by Subrata Banik (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Jérémy Compostella, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84174?usp=email ) Change subject: src/include/cpu/x86: Add Extended Feature Enable Register Macro ...................................................................... Patch Set 5: (1 comment) File src/include/cpu/x86/msr.h: https://review.coreboot.org/c/coreboot/+/84174/comment/5eb5a9b7_0c2faa2a?us… : PS4, Line 64: > Hi, these bits belogs to (POWER_CTL) – Offset 1fc > Indent w/ one space will align with Offset 0x1F8. if these bits belong to offset 0x1fc then you should have moved those bit-definitions inside https://github.com/coreboot/coreboot/blob/main/src/soc/intel/common/block/i… what motivates you to define 0x1fc bit-fields into x84/MSR.h when the same definition exists into intelblock? -- To view, visit https://review.coreboot.org/c/coreboot/+/84174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Gerrit-Change-Number: 84174 Gerrit-PatchSet: 5 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 09:04:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: src/include/cpu/x86: Add Extended Feature Enable Register Macro
by Saurabh Mishra (Code Review) 01 Sep '24

01 Sep '24

Attention is currently required from: Jérémy Compostella, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84174?usp=email ) Change subject: src/include/cpu/x86: Add Extended Feature Enable Register Macro ...................................................................... Patch Set 5: (1 comment) File src/include/cpu/x86/msr.h: https://review.coreboot.org/c/coreboot/+/84174/comment/ebec659a_1d3b28fd?us… : PS4, Line 64: > align with one more tab Hi, these bits belogs to (POWER_CTL) – Offset 1fc Indent w/ one space will align with Offset 0x1F8. -- To view, visit https://review.coreboot.org/c/coreboot/+/84174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Gerrit-Change-Number: 84174 Gerrit-PatchSet: 5 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Sun, 01 Sep 2024 08:57:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: [only build test] tree: add -fsanitize=undefined
by Elyes Haouas (Code Review) 01 Sep '24

01 Sep '24

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84167?usp=email ) Change subject: [only build test] tree: add -fsanitize=undefined ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4002ba18ebddb87f177b27048d8ade2df8016362 Gerrit-Change-Number: 84167 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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