coreboot-gerrit September 2024

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[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC
by Saurabh Mishra (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim. Saurabh Mishra has uploaded a new patch set (#56) to the change originally created by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email ) Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC ...................................................................... soc/intel/ptl: Add GPIOs for Panther Lake SOC Add definitions for the GPIO pins on Panther Lake SoC, as well as GPIO IRQ routing information and supporting ACPI ASL. For now, add the following GPIO communities and GPIO groups: Comm. 0: GPP_V, GPP_C Comm. 1: GPP_F, GPP_E Comm. 3: CPUJTAG, GPP_H, GPP_A, VGPIO3 Comm. 4: GPP_S Comm. 5: GPP_B, GPP_D, VGPIO BUG=b:348678529 TEST=Verified on Intel Silicon platform for PTL using google/fatcat mainboard. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b --- M src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/acpi/gpio.asl A src/soc/intel/pantherlake/gpio.c A src/soc/intel/pantherlake/include/soc/gpio.h A src/soc/intel/pantherlake/include/soc/gpio_defs.h A src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h 6 files changed, 2,005 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/83789/56 -- To view, visit https://review.coreboot.org/c/coreboot/+/83789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b Gerrit-Change-Number: 83789 Gerrit-PatchSet: 56 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: src/{incl/cpu, soc/intel/cmn}: Add Extended Feature Enable Register M...
by Saurabh Mishra (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Jérémy Compostella, Saurabh Mishra. Hello Jérémy Compostella, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84174?usp=email to look at the new patch set (#6). Change subject: src/{incl/cpu, soc/intel/cmn}: Add Extended Feature Enable Register Macro ...................................................................... src/{incl/cpu, soc/intel/cmn}: Add Extended Feature Enable Register Macro Details: - Add (POWER_CTL) – Offset 1fc required bits. - Add (IA32_PACKAGE_THERM_INTERRUPT) – Offset 1b2 required bits Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/include/intelblocks/msr.h 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84174/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7be9a43a51bc52300e66cbf736c3e3275714b13b Gerrit-Change-Number: 84174 Gerrit-PatchSet: 6 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: src/include/: Introducing a new BIT_32(x) macro.
by Subrata Banik (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Martin Roth, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include/: Introducing a new BIT_32(x) macro. ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File src/include/types.h: https://review.coreboot.org/c/coreboot/+/84142/comment/ee81a38e_e163d66a?us… : PS5, Line 27: In file included from src/vendorcode/amd/opensil/genoa_poc/acpi.c:5: src/vendorcode/amd/opensil/genoa_poc/opensil/xUSL/Include/SilCommon.h:26:9: error: 'BIT_32' macro redefined [-Werror,-Wmacro-redefined] 26 | #define BIT_32(X) (uint32_t)(1ul << (X)) | ^ src/include/types.h:25:9: note: previous definition is here 25 | #define BIT_32(x) (1u << (x)) | ^ 1 error generated. Adding @arthur@aheymans.xyz and @martin.roth@amd.corp-partner.google.com to see if a CPP guard can be applied for OpenSIL code (xUSL/Include/SilCommon.h:26:9) ``` #define BIT_64(X) (uint64_t)(1ull << (X)) #define BIT_32(X) (uint32_t)(1ul << (X)) #define BIT_16(X) (uint16_t)(1 << (X)) #define BIT_8(X) (uint8_t)(1 << (X)) ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 5 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 05:26:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brox/var/jubilant: Remove STORAGE_UNKNOWN fw_config option
by Ren Kuo (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Bob Moragues, Eran Mitrani, Karthik Ramasubramanian, Nick Vaccaro, Ren Kuo, Subrata Banik. Ren Kuo has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/84095?usp=email ) Change subject: mb/google/brox/var/jubilant: Remove STORAGE_UNKNOWN fw_config option ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f6ace4b39a1ee0b63486d3872b20c8da719ae4a Gerrit-Change-Number: 84095 Gerrit-PatchSet: 8 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quantatw.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quantatw.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 04:20:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/common/gpio: support 16-bit CPU Port ID
by Subrata Banik (Code Review) 02 Sep '24

02 Sep '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email ) ( 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID ...................................................................... soc/intel/common/gpio: support 16-bit CPU Port ID - Add Kconfig: SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID. - Change cpu_port field to 16-bit width if the Kconfig is set. BUG=none TEST=boot to OS and use iotools to read the registers that use 16-bit port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group ID field. The bit 15:8 of the returned port ID value should be 0xF2 instead of zero. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83981 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/include/intelblocks/gpio.h 2 files changed, 15 insertions(+), 1 deletion(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index de0546c..60a5967 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -63,4 +63,14 @@ SoC user to select this config if Pad Mode (PMODE) width of PAD_CFG_DW0 regiser is 4 bits to support Native Function 1 to 15. +config SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID + bool + default n + help + Enable support for 16-bit CPU Port IDs. + Intel SoCs (starting with Panther Lake) have extended the CPU Port ID field + to 16 bits. + Enable this option if your platform requires the GPIO driver to + accommodate this larger Port ID value. + endif diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index 8e60a16..39d17a1 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -136,7 +136,11 @@ uint8_t gpi_status_offset; /* specifies offset in struct gpi_status */ uint8_t port; /* PCR Port ID */ - uint8_t cpu_port; /* CPU Port ID */ +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID) + uint16_t cpu_port; /* Use 16-bit CPU Port ID */ +#else + uint8_t cpu_port; /* Use 8-bit CPU Port ID */ +#endif const struct reset_mapping *reset_map; /* PADRSTCFG logical to chipset mapping */ size_t num_reset_vals; -- To view, visit https://review.coreboot.org/c/coreboot/+/83981?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c1a48d587bd41178b0c6bb0144fda93e292423d Gerrit-Change-Number: 83981 Gerrit-PatchSet: 12 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Subrata Banik (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/5f145c9b_d89b27ac?us… : PS3, Line 406: pmc_clear_gpi_gpe0_status > Subrata, > > pmc_disable_all_gpe() is called in smm_southbridge_enable function in src/soc/intel/common/block/smm/smm.c. > > from SOC cpu.c, we have MP OPS: > > .pre_mp_smm_init = smm_initialize, <- NOTE: GPE STS bits are cleared here > > .post_mp_init = post_mp_init, <- NOTE: GPE EN bits are cleared here > > This should still be earlier enough. we wish to call the API to clear all pending GPE as part of the shutdown flow so,it can be leveraged by both payload and kernel shutdown handler. I don't see any reason to pull that elsewhere. -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 03:53:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Jamie Ryu <jamie.m.ryu(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/brya: Add romstage early graphics for trulo baseboard
by Subrata Banik (Code Review) 02 Sep '24

02 Sep '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84128?usp=email ) Change subject: mb/google/brya: Add romstage early graphics for trulo baseboard ...................................................................... mb/google/brya: Add romstage early graphics for trulo baseboard 1) Add all required changes for eSOL support. 2) Select MAINBOARD_USE_EARLY_LIBGFXINIT for Trulo. The CSOT (MNC207QS1-1) panel is used for the devicetree. BUG=b:362895813 TEST=On-screen text message seen during MRC training on Trulo SKU1. MRC: no data in 'RW_MRC_CACHE' bootmode is set to: 0 DP PHY mode status not complete DP PHY mode status not complete DP PHY mode status not complete ... Informing user on-display of memory training Change-Id: Ic34a8601b3084aa5f780d358fb0b15b7e820d375 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84128 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb A src/mainboard/google/brya/variants/baseboard/trulo/gma-mainboard.ads 4 files changed, 46 insertions(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Amanda Hwang: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index f4c6f7c..b54b0db 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -113,6 +113,7 @@ select DRIVERS_AUDIO_SOF select DRIVERS_INTEL_ISH select MAINBOARD_DISABLE_STAGE_CACHE + select MAINBOARD_HAS_EARLY_LIBGFXINIT select MEMORY_SOLDERDOWN select SOC_INTEL_COMMON_MMC_OVERRIDE select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk b/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk index be05cd4..cc62f1d 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk +++ b/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk @@ -1,3 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only +romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads romstage-y += memory.c diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb index 5ce75c9..dc0d480 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb @@ -45,7 +45,37 @@ register "pch_hda_sdi_enable[1]" = "true" device domain 0 on - device ref igpu on end + # The timing values can be derived from datasheet of display panel + # You can use EDID string to identify the type of display on the board + # use below command to get display info from EDID + # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid + + # refer to display PRM document (Volume 2b: Command Reference: Registers) + # for more info on display control registers + # https://01.org/linuxgraphics/documentation/hardware-specification-prms + #+-----------------------------+---------------------------------------+-----+ + #| Intel docs | devicetree.cb | eDP | + #+-----------------------------+---------------------------------------+-----+ + #| Power up delay | `gpu_panel_power_up_delay` | T3 | + #+-----------------------------+---------------------------------------+-----+ + #| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Down delay | `gpu_panel_power_down_delay` | T10 | + #+-----------------------------+---------------------------------------+-----+ + #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 | + #+-----------------------------+---------------------------------------+-----+ + device ref igpu on + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + end device ref dtt on end device ref tcss_xhci on end device ref ish on diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/gma-mainboard.ads b/src/mainboard/google/brya/variants/baseboard/trulo/gma-mainboard.ads new file mode 100644 index 0000000..3b02f14 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/trulo/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + ports : constant Port_List := + (eDP, + others => Disabled); +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/84128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic34a8601b3084aa5f780d358fb0b15b7e820d375 Gerrit-Change-Number: 84128 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: Documentation/mb/asus/p8z77-m: Document latest test results
by Keith Hui (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Angel Pons, Kevin Keijzer, Nicholas Chin, Paul Menzel. Hello Angel Pons, Nicholas Chin, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78204?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+2 by Nicholas Chin, Verified+1 by build bot (Jenkins) Change subject: Documentation/mb/asus/p8z77-m: Document latest test results ...................................................................... Documentation/mb/asus/p8z77-m: Document latest test results Change-Id: I4f4c9268cd272caa83267be3f71d4a2022c26a1c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M Documentation/mainboard/asus/p8z77-m.md 1 file changed, 49 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/78204/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f4c9268cd272caa83267be3f71d4a2022c26a1c Gerrit-Change-Number: 78204 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/brya: Add romstage early graphics for trulo baseboard
by Subrata Banik (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84128?usp=email ) Change subject: mb/google/brya: Add romstage early graphics for trulo baseboard ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > I can get eSOL screen with this CL on Orisa. thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/84128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic34a8601b3084aa5f780d358fb0b15b7e820d375 Gerrit-Change-Number: 84128 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 02 Sep 2024 03:37:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Prevent overlapping boot screens
by Subrata Banik (Code Review) 02 Sep '24

02 Sep '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84144?usp=email ) Change subject: soc/intel/alderlake: Prevent overlapping boot screens ...................................................................... soc/intel/alderlake: Prevent overlapping boot screens Previously, `early_graphics_stop()` was skipped unconditionally if `CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` was enabled. This led to overlapping screens when CSE sync was not triggered in ramstage, as both the eSOL message and the firmware splash screen would be displayed. This change refactors the condition for calling `early_graphics_stop()` to ensure it is only skipped if a CSE firmware update is actually required *and* `CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)` is set. This allows eSOL to display its message during CSE sync, but tears down early graphics programming in other cases to prevent overlapping screens. Additionally, this change ensures that `early_graphics_stop()` is the last function called by the romstage to guarantee proper cleanup. BUG=b:362895813 TEST=Able to boot google/tivviks_ufs without overlapping screens. Change-Id: Idc01bfc8963d65fcb0441300e7c9267eaaefefb9 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84144 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 8 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Amanda Hwang: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index b577e32..ff600db 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -215,16 +215,18 @@ if (!s3wake) save_dimm_info(); + if (CONFIG(ENABLE_EARLY_DMA_PROTECTION)) + vtd_enable_dma_protection(); + + /* Keep eSOL active if CSE sync is pending at ramstage */ + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()) + return; + /* * Turn-off early graphics configuration with two purposes: * - Clear any potentially still on-screen message * - Allow PEIM graphics driver to smoothly execute in ramstage if * RUN_FSP_GOP is selected */ - if (!CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)) - /* Keep eSOL active if CSE sync in ramstage config is enabled */ - early_graphics_stop(); - - if (CONFIG(ENABLE_EARLY_DMA_PROTECTION)) - vtd_enable_dma_protection(); + early_graphics_stop(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84144?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc01bfc8963d65fcb0441300e7c9267eaaefefb9 Gerrit-Change-Number: 84144 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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