coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: src/include: Introduce a new BIT_FLAG_32(x) macro
by Subrata Banik (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Julius Werner, Jérémy Compostella, Karthik Ramasubramanian, Martin Roth, Pratikkumar V Prajapati, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include: Introduce a new BIT_FLAG_32(x) macro ...................................................................... Patch Set 19: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 19 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 16:23:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Subrata Banik (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 8: (2 comments) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/43bf1b12_dc6d87f1?us… : PS7, Line 341: pmc_clear_gpi_gpe0_status > Okay. let me know if I can remove these two or keep them with the GPE1 support. I would say, please keep those as TODO item for b/357011633 and we can revisit later File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/56bf8a5f_20097068?us… : PS8, Line 321: soc_pmc_disable_std_gpe1(mask); > The only thing left is that if the EN bit(s) have been set prior to going to suspend. I had the impression that BIOS can always set EN bit for all GPE0/GPE1 (as part of GPIO programming aka gpi_enable_gpe) and status is what will be handled by HW event. -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 16:22:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions
by Cliff Huang (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Hannah Williams, Jamie Ryu, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email ) Change subject: soc/intel/common/block/pmc: Add GPE1 functions ...................................................................... Patch Set 8: (2 comments) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/dfa8f207_9d261492?us… : PS7, Line 341: pmc_clear_gpi_gpe0_status > > Subrata, […] Okay. let me know if I can remove these two or keep them with the GPE1 support. File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/84104/comment/63687ad2_fab993d9?us… : PS8, Line 321: soc_pmc_disable_std_gpe1(mask); > > Subrata, […] The only thing left is that if the EN bit(s) have been set prior to going to suspend. -- To view, visit https://review.coreboot.org/c/coreboot/+/84104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d Gerrit-Change-Number: 84104 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 16:10:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: src/include: Introduce a new BIT_FLAG_32(x) macro
by Jérémy Compostella (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Julius Werner, Karthik Ramasubramanian, Martin Roth, Pratikkumar V Prajapati, Saurabh Mishra, Subrata Banik. Jérémy Compostella has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include: Introduce a new BIT_FLAG_32(x) macro ...................................................................... Patch Set 19: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 19 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 16:05:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: Cezanne: Add an option to enable A/B recovery scheme
by Marshall Dawson (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Marshall Dawson has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84195?usp=email ) Change subject: Cezanne: Add an option to enable A/B recovery scheme ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84195/comment/c1e9027a_ffc5e36d?us… : PS1, Line 9: Non A/B recovery > Done Wow, thank you for the additional detail. But please also mention the NDA spec #56995. Commit Message: https://review.coreboot.org/c/coreboot/+/84195/comment/f8055c1e_eda98b05?us… : PS2, Line 7: Cezanne: Add an option to enable A/B recovery scheme : One more nit, please begin this with "soc/amd/cezanne". If needed for shortness, you can simplify the remaining part down to "add option for A/B recovery". File src/soc/amd/cezanne/Kconfig: https://review.coreboot.org/c/coreboot/+/84195/comment/c440c6a9_323ad592?us… : PS1, Line 415: Recovery A/B > I dont know much about vboot's role in A/B recovery. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6 Gerrit-Change-Number: 84195 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Sep 2024 15:44:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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[XS] Change in coreboot[main]: amdfwtool: Set L2 table size as 0x400
by Marshall Dawson (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Anand Vaikar, Bao Zheng, Felix Held, Zheng Bao, ritul guru. Marshall Dawson has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84194?usp=email ) Change subject: amdfwtool: Set L2 table size as 0x400 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84194?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb Gerrit-Change-Number: 84194 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Sep 2024 15:43:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: FIXME remove asserts for mt8186 code
by Arthur Heymans (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84208?usp=email ) Change subject: FIXME remove asserts for mt8186 code ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/mt8186/mt6366.c: https://review.coreboot.org/c/coreboot/+/84208/comment/22de2236_5cfa5e8d?us… : PS3, Line 594: assert(vddq_uv <= 680000); > Actually, after looking into this, all the callers are passing valid values here. The minimum upper bound to successfully build GOOGLE_STEELIX with LTO is `assert(vddq_uv <= 1031250)`. It seems that the value 1031250 comes from the `mainboard_set_regulator_voltage(MTK_REGULATOR_VPROC12, 1031250)` call. However, that function call isn't related to the code here at all, because the regulator id is different (`VPROC12` vs `VDDQ`). Therefore, I think this is a false positive reported by the linker. Yes sorry for this. It looks like the compiler is indeed the root cause of this. I vaguely suspect that the implementation of assert does not work well with LTO. Another possibility is that GCC LTO is simply not there yet. It looks like it has other issues as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/84208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e Gerrit-Change-Number: 84208 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 14:38:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/intel: Add PCI DID for ADL-N (ID-6)
by David Milosevic (Code Review) 04 Sep '24

04 Sep '24

David Milosevic has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84215?usp=email ) Change subject: soc/intel: Add PCI DID for ADL-N (ID-6) ...................................................................... soc/intel: Add PCI DID for ADL-N (ID-6) This change is required for the ODROID H4 board. Change-Id: Idb87a5f2d28cb90b3c1cdcd50816bad6d873dddb Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/84215/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 481bf20..6e90de4 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4394,6 +4394,7 @@ #define PCI_DID_INTEL_ADL_N_ID_3 0x461c #define PCI_DID_INTEL_ADL_N_ID_4 0x4614 #define PCI_DID_INTEL_ADL_N_ID_5 0x4618 +#define PCI_DID_INTEL_ADL_N_ID_6 0x4678 #define PCI_DID_INTEL_MTL_M_ID 0x7D00 #define PCI_DID_INTEL_MTL_P_ID_1 0x7D01 #define PCI_DID_INTEL_MTL_P_ID_2 0x7D02 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 5d9ac15..07ece3e 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -520,6 +520,7 @@ PCI_DID_INTEL_ADL_N_ID_3, PCI_DID_INTEL_ADL_N_ID_4, PCI_DID_INTEL_ADL_N_ID_5, + PCI_DID_INTEL_ADL_N_ID_6, PCI_DID_INTEL_RPL_HX_ID_1, PCI_DID_INTEL_RPL_HX_ID_2, PCI_DID_INTEL_RPL_HX_ID_3, -- To view, visit https://review.coreboot.org/c/coreboot/+/84215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb87a5f2d28cb90b3c1cdcd50816bad6d873dddb Gerrit-Change-Number: 84215 Gerrit-PatchSet: 1 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com>

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[L] Change in coreboot[main]: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support
by David Milosevic (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Alicja Michalska, David Milosevic, Felix Singer. Hello Angel Pons, Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83979?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support ...................................................................... [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support This patch adds support for the odroid-h4 board. Note, that this is still a work in progress and was not yet properly tested on real hardware. Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- A src/mainboard/hardkernel/Kconfig A src/mainboard/hardkernel/Kconfig.name A src/mainboard/hardkernel/odroid-h4/Kconfig A src/mainboard/hardkernel/odroid-h4/Kconfig.name A src/mainboard/hardkernel/odroid-h4/Makefile.mk A src/mainboard/hardkernel/odroid-h4/board_info.txt A src/mainboard/hardkernel/odroid-h4/bootblock.c A src/mainboard/hardkernel/odroid-h4/data.vbt A src/mainboard/hardkernel/odroid-h4/devicetree.cb A src/mainboard/hardkernel/odroid-h4/dsdt.asl A src/mainboard/hardkernel/odroid-h4/gpio.h A src/mainboard/hardkernel/odroid-h4/mainboard.c A src/mainboard/hardkernel/odroid-h4/ramstage_fsp_params.c A src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c 14 files changed, 540 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/83979/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Gerrit-Change-Number: 83979 Gerrit-PatchSet: 4 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Subrata Banik (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 81: (1 comment) Patchset: PS81: @mishra.saurabh@intel.com, can you please ensure you are following CB:84182 and CB:84183 while creating ramstage CL for panther lake? -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 81 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 12:56:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit September 2024