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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
soc/intel/common/block/pmc: Add GPE1 functions
- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag.
- The existing static gpe functions has been renamed with gpe0.
- Add gpe1 functions.
BUG=362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag, boot DUT,
and check if GPE1 sts bits have been printed during boot.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 96 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/9
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Change subject: soc/mediatek/mt8196: Add EINT support
......................................................................
Patch Set 18:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84026/comment/7c51b905_843c96c9?us… :
PS18, Line 8:
Can you please elaborate?
https://review.coreboot.org/c/coreboot/+/84026/comment/2c90282d_d9dc6383?us… :
PS18, Line 10: EINT works in Rauru
How can this be verified? Please give a command.
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Change subject: drivers/i2c/generic: Remove erroneous acpigen_pop_len
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84197/comment/ed54060f_a8c70b85?us… :
PS3, Line 10: an EMERG warning
> Paste the warning?
Done
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Hello Martin L Roth, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: drivers/i2c/generic: Remove erroneous acpigen_pop_len
......................................................................
drivers/i2c/generic: Remove erroneous acpigen_pop_len
There are one too many acpigen_pop_len calls in the code
to generate the ROTM; remove one to fix an EMERG warning:
[EMERG] ASSERTION_ERROR: file `src/acpi/acpigen.c`, line 38
The extra acpigen_pop_len() call was added commit
45d2c3d5436e ("i2c/drivers/generic: Return ROTM in a package").
Change-Id: I913022144813f7f65eac1bcb7c97656f2c513c0b
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/drivers/i2c/generic/generic.c
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84197/4
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/84104/comment/7de06a29_35681c71?us… :
PS7, Line 341: pmc_clear_gpi_gpe0_status
> > Okay. let me know if I can remove these two or keep them with the GPE1 support. […]
sure. Let me put them back.
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Hello Elyes Haouas, Krystian Hebel, Martin L Roth, Michał Żygowski, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#41).
Change subject: Makefile.mk: compile ECC tools and inject ECC to final image
......................................................................
Makefile.mk: compile ECC tools and inject ECC to final image
$ build/cbfstool build/coreboot.rom print
FMAP REGION: COREBOOT
Name Offset Type Size Comp
cbfs_master_header 0x0 cbfs header 32 none
fallback/romstage 0x80 stage 18495 LZ4 (30096 decompressed)
fallback/ramstage 0x4940 stage 24288 LZMA (61240 decompressed)
config 0xa880 raw 1324 LZMA (3308 decompressed)
revision 0xae00 raw 726 none
build_info 0xb100 raw 122 none
(empty) 0xb1c0 null 347108 none
header_pointer 0x5fdc0 cbfs header 4 none
Change-Id: I8541aa6f1429ed6143830ed11c47c150183ddf0d
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M Makefile.mk
M src/soc/ibm/power9/Makefile.mk
2 files changed, 14 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/67064/41
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email )
Change subject: src/include: Introduce a new BIT_FLAG_32(x) macro
......................................................................
src/include: Introduce a new BIT_FLAG_32(x) macro
Introduces the BIT_FLAG_32(x) macro to create a 32-bit mask with the
designated bit set. This ensures compatibility with the 32-bit
'GEN_PMCON_A' register on 64-bit systems, where 1ul is 64 bits wide and
could potentially cause an overflow when shifted beyond 31 bits.
Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84142
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com>
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Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/include/types.h
1 file changed, 9 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Pratikkumar V Prajapati: Looks good to me, approved
Subrata Banik: Looks good to me, approved
Jérémy Compostella: Looks good to me, approved
Paul Menzel: Looks good to me, but someone else must approve
diff --git a/src/include/types.h b/src/include/types.h
index ca45717..df5e7ae 100644
--- a/src/include/types.h
+++ b/src/include/types.h
@@ -21,6 +21,15 @@
#define BIT(x) (1ul << (x))
#endif
+/*
+ * This macro declares a bit as a 32-bits unsigned integer. The common BIT_32(x)
+ * macro is already used by some external header file. To avoid any conflicts, we
+ * use a different name.
+ */
+#ifndef BIT_FLAG_32
+#define BIT_FLAG_32(x) (1u << (x))
+#endif
+
#define BITS_PER_BYTE 8
#endif /* __TYPES_H */
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Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84216?usp=email )
Change subject: soc/intel/pantherlake: Hardcode IOM_BASE_ADDR_MAX value
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Please rebase this CL on top of the tree so, we can merge it tomorrow
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