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Change subject: mb/google/brox/variants/brox: Update PL1 Min
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> please consider this patch to be abandoned and review this patch instead https://review.coreboot. […]
I would request to keep this original patch to take it forward and merge, instead of this one https://review.coreboot.org/c/coreboot/+/84185
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Change subject: mb/google/brox/variants/brox: remove PL4 value modification
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> please consider this patch to be abandoned and review this patch instead https://review.coreboot. […]
I would request to keep this original patch to take it forward and merge, instead of this one https://review.coreboot.org/c/coreboot/+/84185
Commit Message:
https://review.coreboot.org/c/coreboot/+/83662/comment/4c262888_b24a3ec9?us… :
PS1, Line 8:
: Remove PL4 value modification based on PsysPL3 valuei.
:
> the motivation not clear? can you please give a reason why it existed before and why you are not rem […]
PL4 value should not be configure/modify based on PsysPL3.
It was showing wrong PL4 value on the system with earlier patch [https://review.coreboot.org/c/coreboot/+/83087/6/src/mainboard/google/brox/… line#160].
This patch corrects it by removing this code.
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Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim.
Cliff Huang has uploaded a new patch set (#93) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake-up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
4. PTL replaces DMI3 with SAF to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE guard check is added in northbridge.asl
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
---
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
M src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
A src/soc/intel/pantherlake/acpi/hda.asl
A src/soc/intel/pantherlake/acpi/pcie.asl
A src/soc/intel/pantherlake/acpi/serialio.asl
A src/soc/intel/pantherlake/acpi/southbridge.asl
A src/soc/intel/pantherlake/acpi/tcss.asl
A src/soc/intel/pantherlake/acpi/tcss_dma.asl
A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
A src/soc/intel/pantherlake/acpi/tcss_xhci.asl
A src/soc/intel/pantherlake/acpi/xhci.asl
12 files changed, 1,999 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/93
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Sumeet R.P. has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/84185?usp=email )
Change subject: mb/google/brox: Increase PL1 Min and remove PL4 modification
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
This patch is the same of earlier patches submitted for review https://review.coreboot.org/c/coreboot/+/83661 and https://review.coreboot.org/c/coreboot/+/83662
I would request to consider these above two patches to consider and take it forward for merge instead of this patch.
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Attention is currently required from: Jérémy Compostella.
Hello Jérémy Compostella,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/84216?usp=email
to review the following change.
Change subject: soc/intel/pantherlake: Hardcode IOM_BASE_ADDR_MAX value
......................................................................
soc/intel/pantherlake: Hardcode IOM_BASE_ADDR_MAX value
iasl refuses to perform an arithmetic computation in a QWordMemory
parameter and fails with the following error.
dsdt.asl 2149: 0x4010800000, ((0x4010800000 + 0x10000) - 1), 0x0,
Error 6051 - ^ Address Min is greater than Address Max
This commit replaces the arithmetic with the result to define
IOM_BASE_ADDR_MAX.
BUG=b:348678529
TEST=Build for google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f16
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/soc/intel/pantherlake/include/soc/iomap.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/84216/1
diff --git a/src/soc/intel/pantherlake/include/soc/iomap.h b/src/soc/intel/pantherlake/include/soc/iomap.h
index a98d550..86e5ec1 100644
--- a/src/soc/intel/pantherlake/include/soc/iomap.h
+++ b/src/soc/intel/pantherlake/include/soc/iomap.h
@@ -85,7 +85,7 @@
*/
#define IOM_BASE_ADDR 0x4010800000
#define IOM_BASE_SIZE 0x10000
-#define IOM_BASE_ADDR_MAX ((IOM_BASE_ADDR + IOM_BASE_SIZE) - 1)
+#define IOM_BASE_ADDR_MAX 0x401080ffff
/* I/O port address space */
#define ACPI_BASE_ADDRESS 0x1800
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