coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

1 participants
3342 discussions

[XL] Change in coreboot[main]: mainboard/hardkernel: Add ODROID H4+ initial support
by Michał Żygowski (Code Review) 04 Sep '24

04 Sep '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84213?usp=email ) Change subject: mainboard/hardkernel: Add ODROID H4+ initial support ...................................................................... mainboard/hardkernel: Add ODROID H4+ initial support TEST=Boots to Ubuntu 23.04 from NVMe using MrChromebox UEFIPayload. Change-Id: Iee066cb0da27e3bf7ce52fc199396185912893aa Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- A configs/config.hardkernel_odroid_h4plus A src/mainboard/hardkernel/Kconfig A src/mainboard/hardkernel/Kconfig.name A src/mainboard/hardkernel/odroid_h4/Kconfig A src/mainboard/hardkernel/odroid_h4/Kconfig.name A src/mainboard/hardkernel/odroid_h4/Makefile.mk A src/mainboard/hardkernel/odroid_h4/board_info.txt A src/mainboard/hardkernel/odroid_h4/bootblock.c A src/mainboard/hardkernel/odroid_h4/data.vbt A src/mainboard/hardkernel/odroid_h4/devicetree.cb A src/mainboard/hardkernel/odroid_h4/die.c A src/mainboard/hardkernel/odroid_h4/dsdt.asl A src/mainboard/hardkernel/odroid_h4/gpio.c A src/mainboard/hardkernel/odroid_h4/gpio.h A src/mainboard/hardkernel/odroid_h4/hda_verb.c A src/mainboard/hardkernel/odroid_h4/mainboard.c A src/mainboard/hardkernel/odroid_h4/romstage_fsp_params.c A src/mainboard/hardkernel/odroid_h4/vboot-rwa.fmd 18 files changed, 1,064 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/84213/1 diff --git a/configs/config.hardkernel_odroid_h4plus b/configs/config.hardkernel_odroid_h4plus new file mode 100644 index 0000000..64da3b7 --- /dev/null +++ b/configs/config.hardkernel_odroid_h4plus @@ -0,0 +1,15 @@ +CONFIG_VENDOR_HARDKERNEL=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VBOOT=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_TPM2=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="-D VARIABLE_SUPPORT=SMMSTORE" diff --git a/src/mainboard/hardkernel/Kconfig b/src/mainboard/hardkernel/Kconfig new file mode 100644 index 0000000..eff82b2 --- /dev/null +++ b/src/mainboard/hardkernel/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_HARDKERNEL + +choice + prompt "Mainboard model" + +source "src/mainboard/hardkernel/*/Kconfig.name" + +endchoice + +source "src/mainboard/hardkernel/*/Kconfig" + +config MAINBOARD_VENDOR + default "Hardkernel" + +endif # VENDOR_HARDKERNEL diff --git a/src/mainboard/hardkernel/Kconfig.name b/src/mainboard/hardkernel/Kconfig.name new file mode 100644 index 0000000..ff0f70d --- /dev/null +++ b/src/mainboard/hardkernel/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_HARDKERNEL + bool "Hardkernel" diff --git a/src/mainboard/hardkernel/odroid_h4/Kconfig b/src/mainboard/hardkernel/odroid_h4/Kconfig new file mode 100644 index 0000000..3894378 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/Kconfig @@ -0,0 +1,61 @@ +if BOARD_HARDKERNEL_ODROID_H4PLUS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_ALDERLAKE_PCH_N + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SUPERIO_ITE_IT8613E + select CRB_TPM + select DRIVERS_UART_8250IO + select FSP_TYPE_IOT + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_INTEL_PTT + select INTEL_GMA_HAVE_VBT + select USE_DDR5 + +config MAINBOARD_DIR + default "hardkernel/odroid_h4" + +config MAINBOARD_PART_NUMBER + default "ODROID-H4" + +config MAINBOARD_VENDOR + default "HARDKERNEL" + +config MAINBOARD_FAMILY + default "Default String" + +config DIMM_SPD_SIZE + default 1024 + +config UART_FOR_CONSOLE + default 0 + +config USE_PM_ACPI_TIMER + default n + +config CBFS_SIZE + default 0xa00000 + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_NO_BOARD_SUPPORT + select HAS_RECOVERY_MRC_CACHE + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + +config VBOOT_SLOTS_RW_A + default y if VBOOT + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + +endif diff --git a/src/mainboard/hardkernel/odroid_h4/Kconfig.name b/src/mainboard/hardkernel/odroid_h4/Kconfig.name new file mode 100644 index 0000000..f9d3656 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HARDKERNEL_ODROID_H4PLUS + bool "ODROID H4+" diff --git a/src/mainboard/hardkernel/odroid_h4/Makefile.mk b/src/mainboard/hardkernel/odroid_h4/Makefile.mk new file mode 100644 index 0000000..f2bc230 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/Makefile.mk @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += gpio.c +romstage-y += romstage_fsp_params.c + +ramstage-y += mainboard.c +ramstage-y += gpio.c + +bootblock-y += die.c +romstage-y += die.c diff --git a/src/mainboard/hardkernel/odroid_h4/board_info.txt b/src/mainboard/hardkernel/odroid_h4/board_info.txt new file mode 100644 index 0000000..23c4523 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/board_info.txt @@ -0,0 +1,7 @@ +Category: sbc +Board URL: https://www.hardkernel.com/shop/odroid-h4-plus/ +ROM IC: Winbond W25Q128FW +ROM package: SOIC8-8 +ROM socketed: no +Flashrom support: yes +Release year: 2023 diff --git a/src/mainboard/hardkernel/odroid_h4/bootblock.c b/src/mainboard/hardkernel/odroid_h4/bootblock.c new file mode 100644 index 0000000..31f2897 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/bootblock.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/common/ite_gpio.h> +#include <superio/ite/it8613e/it8613e.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +#define ITE_GPIO_BASE 0xa00 +#define ITE_GPIO_PIN(x) (1 << ((x) % 10)) +#define ITE_GPIO_SET(x) (((x) / 10) - 1) +#define ITE_GPIO_IO_ADDR(x) (ITE_GPIO_BASE + ITE_GPIO_SET(x)) + +static void ite_set_gpio_iobase(u16 iobase) +{ + pnp_enter_conf_state(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_set_iobase(GPIO_DEV, PNP_IDX_IO1, iobase); + pnp_exit_conf_state(GPIO_DEV); +} + +void bootblock_mainboard_early_init(void) +{ + /* Internal VCC_OK */ + ite_reg_write(GPIO_DEV, 0x23, 0x40); + /* Pin7 as GP23 - USB2_EN */ + ite_reg_write(GPIO_DEV, 0x26, 0xfb); + /* Pin24 as GPO50 (value of 0 on bit0 is reserved, JP1 strapping)*/ + ite_reg_write(GPIO_DEV, 0x29, 0x01); + /* K8 power sequence sofyware disabled */ + ite_reg_write(GPIO_DEV, 0x2c, 0x41); + /* PCICLK 25MHz */ + ite_reg_write(GPIO_DEV, 0x2d, 0x02); + ite_kill_watchdog(GPIO_DEV); + /* GP21 - USB3_EN, VBUS power gate for the USB3.x ports */ + ite_gpio_setup(GPIO_DEV, 21, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, + ITE_GPIO_CONTROL_DEFAULT); + /* GP23 - USB2_EN, VBUS power gate for the USB2.x ports */ + ite_gpio_setup(GPIO_DEV, 23, ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, + ITE_GPIO_CONTROL_DEFAULT); + + ite_set_gpio_iobase(ITE_GPIO_BASE); + /* GP21 and GP23 to low to enable USB ports VBUS */ + outb(inb(ITE_GPIO_IO_ADDR(21)) & ~ITE_GPIO_PIN(21), ITE_GPIO_IO_ADDR(21)); + outb(inb(ITE_GPIO_IO_ADDR(23)) & ~ITE_GPIO_PIN(23), ITE_GPIO_IO_ADDR(23)); + + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/hardkernel/odroid_h4/data.vbt b/src/mainboard/hardkernel/odroid_h4/data.vbt new file mode 100644 index 0000000..a3c168f --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/data.vbt Binary files differ diff --git a/src/mainboard/hardkernel/odroid_h4/devicetree.cb b/src/mainboard/hardkernel/odroid_h4/devicetree.cb new file mode 100644 index 0000000..52c0d74 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/devicetree.cb @@ -0,0 +1,223 @@ +chip soc/intel/alderlake + # FSP configuration + + register "eist_enable" = "1" + + # Sagv Configuration + register "sagv" = "SaGv_Enabled" + register "RMT" = "0" + register "enable_c6dram" = "1" + + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + register "tcc_offset" = "10" # TCC of 90C + + device cpu_cluster 0 on end + device domain 0 on + subsystemid 0x8086 0x7270 inherit + device ref igpu on + register "ddi_portA_config" = "1" # HDMI on port A + register "ddi_portB_config" = "1" # DP on port B + # Fixed DP in TCP0 + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + end + + device ref xhci on + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 3.0 front + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 3.0 front + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # EXT_HEAD1 + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # EXT_HEAD1 + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 2.0 front + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # EXT_HEAD1 + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 2.0 front + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_EMPTY" + register "usb2_ports[10]" = "USB2_PORT_EMPTY" + register "usb2_ports[11]" = "USB2_PORT_EMPTY" + register "usb2_ports[12]" = "USB2_PORT_EMPTY" + register "usb2_ports[13]" = "USB2_PORT_EMPTY" + register "usb2_ports[14]" = "USB2_PORT_EMPTY" + register "usb2_ports[15]" = "USB2_PORT_EMPTY" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A 3.0 front + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A 3.0 front + register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb3_ports[3]" = "USB3_PORT_EMPTY" + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + register "usb3_ports[6]" = "USB3_PORT_EMPTY" + register "usb3_ports[7]" = "USB3_PORT_EMPTY" + register "usb3_ports[8]" = "USB3_PORT_EMPTY" + register "usb3_ports[9]" = "USB3_PORT_EMPTY" + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 2 (USB3_LAN1)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1 (USB3_LAN1)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Port 3 (EXT_HEAD1)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Port 4 (EXT_HEAD1)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 5 (USBLAN1)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Port 6 (EXT_HEAD1)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 7 (USBLAN1)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 2))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref usb2_port7 on end + end + end + end + end + + device ref i2c0 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + end + device ref i2c1 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref heci1 on end + device ref sata on + register "sata_salp_support" = "1" + + register "sata_ports_enable" = "{ + [0] = 0, + [1] = 1, + }" + end + + device ref emmc on + register "emmc_enable_hs400_mode" = "true" + end + + # LAN1 Intel i226 + device ref pcie_rp3 on + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 1, + .clk_req = 1, + }" + end + # LAN2 Intel i226 + device ref pcie_rp4 on + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 2, + .clk_req = 2, + }" + end + # ASMedia PCie to 4xSATA + device ref pcie_rp7 on + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 3, + .clk_req = 3, + }" + end + + # NVMe x4 link + device ref pcie_rp9 on + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 0, + .clk_req = 0, + }" + end + + device ref pch_espi on + # LPC generic I/O ranges + register "gen1_dec" = "0x003c0a01" + register "gen2_dec" = "0x000c0081" + register "gen3_dec" = "0x00fc0201" + + chip superio/ite/it8613e + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + irq 0xf1 = 0x52 # IRQ low level + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa20 + io 0x62 = 0xa10 + irq 0x70 = 0 # Don't use IRQ + irq 0xf4 = 0x20 # PSON_N is inverted SUSB_N + irq 0xfa = 0x20 # Enable WDT output through PWRGD + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 on # GPIO + io 0x60 = 0xa08 + io 0x62 = 0xa00 + end + device pnp 2e.a off end # CIR + end + end + device ref p2sb hidden end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + end + device ref hda on + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "true" + register "pch_hda_sdi_enable[0]" = "1" + end + device ref smbus on end + + chip drivers/crb + device mmio 0xfed40000 on end + end + end +end diff --git a/src/mainboard/hardkernel/odroid_h4/die.c b/src/mainboard/hardkernel/odroid_h4/die.c new file mode 100644 index 0000000..85fe229 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/die.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/gpio.h> +#include <delay.h> +#include <gpio.h> + +void die_notify(void) +{ + static uint8_t blink = 0; + + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink */ + gpio_output(GPP_B14, 0); + + while (1) { + gpio_set(GPP_B14, blink); + blink ^= 1; + mdelay(500); + } +} diff --git a/src/mainboard/hardkernel/odroid_h4/dsdt.asl b/src/mainboard/hardkernel/odroid_h4/dsdt.asl new file mode 100644 index 0000000..584f330 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/hardkernel/odroid_h4/gpio.c b/src/mainboard/hardkernel/odroid_h4/gpio.c new file mode 100644 index 0000000..7d1687c --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/gpio.c @@ -0,0 +1,453 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> + +#include "gpio.h" + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* GPP_B2 - VRALERT# */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + /* GPP_B8 - GPIO EMMC_DET# */ + PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 - SATA_LED# */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF4), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_NC(GPP_B23, NONE), + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_T ------- */ + + PAD_NC(GPP_T0, NONE), + PAD_NC(GPP_T1, NONE), + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), + PAD_NC(GPP_T4, NONE), + PAD_NC(GPP_T5, NONE), + PAD_NC(GPP_T6, NONE), + PAD_NC(GPP_T7, NONE), + PAD_NC(GPP_T8, NONE), + PAD_NC(GPP_T9, NONE), + PAD_NC(GPP_T10, NONE), + PAD_NC(GPP_T11, NONE), + PAD_NC(GPP_T12, NONE), + PAD_NC(GPP_T13, NONE), + PAD_NC(GPP_T14, NONE), + PAD_NC(GPP_T15, NONE), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + /* GPP_A4 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + /* GPP_A5 - ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + /* GPP_A8 - LAN_DISABLE# */ + PAD_CFG_GPO(GPP_VGPIO_0, 1, DEEP), + /* GPP_A9 - ESPI_CLK */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + /* GPP_A10 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_NC(GPP_A11, NONE), + /* GPP_A12 - SATAXPCIE1 */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + PAD_NC(GPP_A13, NONE), + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* GPP_A19 - DDSP_HPD1 */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_I ------- */ + + PAD_NC(GPP_I5, NONE), + /* GPP_I7 - EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + /* GPP_I8 - EMMC_DATA0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + /* GPP_I9 - EMMC_DATA1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + /* GPP_I10 - EMMC_DATA2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + /* GPP_I11 - EMMC_DATA3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + /* GPP_I12 - EMMC_DATA4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + /* GPP_I13 - EMMC_DATA5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + /* GPP_I14 - EMMC_DATA6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + /* GPP_I15 - EMMC_DATA7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + /* GPP_I16 - EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + /* GPP_I17 - EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + /* GPP_I18 - EMMC_RESET# */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_H ------- */ + + PAD_NC(GPP_H0, NONE), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + /* GPP_H4 - I2C0_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* GPP_H5 - I2C0_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* GPP_H6 - I2C1_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* GPP_H7 - I2C1_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + /* GPP_H15 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + PAD_NC(GPP_H16, NONE), + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H18 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + /* GPP_D5 - SRCCLKREQ0# to PCIE RP 9 (NVMe) */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D6 - SRCCLKREQ1# to PCIE RP 3 (LAN1) */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* GPP_D7 - SRCCLKREQ2# to PCIE RP 4 (LAN2) */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* GPP_D8 - SRCCLKREQ3# presumably for PCIE RP7, but permanently grounded? */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D9, NATIVE), + PAD_NC(GPP_D10, NATIVE), + PAD_NC(GPP_D11, NATIVE), + PAD_NC(GPP_D12, NATIVE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group vGPIO ------- */ + + /* GPP_VGPIO_0 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + /* GPP_VGPIO_4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO_5 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + /* GPP_VGPIO_THC0 - GPP_VGPIO_THC0 */ + PAD_CFG_NF(GPP_VGPIO_THC0, NONE, DEEP, NF1), + /* GPP_VGPIO_THC1 - GPP_VGPIO_THC1 */ + PAD_CFG_NF(GPP_VGPIO_THC1, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + PAD_NC(GPD2, NONE), + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + /* GPD8 - SUS_CLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_NC(GPD11, NONE), + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + /* GPD_SLP_LANB - GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + /* GPD_WAKEB - GPD_WAKEB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_NC(GPP_C2, NONE), + PAD_NC(GPP_C3, NONE), + PAD_NC(GPP_C4, NONE), + PAD_NC(GPP_C5, NONE), + PAD_NC(GPP_C6, NONE), + PAD_NC(GPP_C7, NONE), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_NC(GPP_F7, NONE), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + + /* GPP_L_BKLTEN - n/a */ + PAD_NC(GPP_L_BKLTEN, NONE), + /* GPP_L_BKLTCTL - n/a */ + PAD_NC(GPP_L_BKLTCTL, NONE), + /* GPP_L_VDDEN - n/a */ + PAD_NC(GPP_L_VDDEN, NONE), + /* GPP_SYS_PWROK - n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + /* GPP_SYS_RESETB - n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + /* GPP_MLK_RSTB - n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* GPP_E15 - Reserved */ + PAD_NC(GPP_E15, NONE ), + /* GPP_E16 - Connetced to pad 67 in M.2 NVMe slot */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + PAD_NC(GPP_E17, NONE), + /* GPP_E18 - DDP1_CTRLCLK */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + /* GPP_E19 - DDP1_CTRLDATA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + PAD_NC(GPP_E20, NATIVE), + PAD_NC(GPP_E21, NATIVE), + /* GPP_E22 - DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), + /* GPP_E23 - DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + /* GPP_E_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* GPP_R1 - HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + /* GPP_R3 - HDA_SDI0 */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + /* GPP_R4 - HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE) +}; + +const struct pad_config *board_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/hardkernel/odroid_h4/gpio.h b/src/mainboard/hardkernel/odroid_h4/gpio.h new file mode 100644 index 0000000..e2c63ae --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +const struct pad_config *board_gpio_table(size_t *num); + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/hardkernel/odroid_h4/hda_verb.c b/src/mainboard/hardkernel/odroid_h4/hda_verb.c new file mode 100644 index 0000000..86e9f29 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/hda_verb.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek ALC897 */ + 0x10ec0897, /* Vendor ID */ + 0x10ec0000, /* Subsystem ID */ + 16, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x10ec0000), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01214010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40210201), + AZALIA_PIN_CFG(0, 0x1e, 0x01441120), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + /* Alderlake-P HDMI */ + 0x8086281c, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 13, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_RESET(1), + 0x00278111, + 0x00278111, + 0x00278111, + 0x00278111, + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), + 0x00278100, + 0x00278100, + 0x00278100, + 0x00278100 +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hardkernel/odroid_h4/mainboard.c b/src/mainboard/hardkernel/odroid_h4/mainboard.c new file mode 100644 index 0000000..edbf623 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/mainboard.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/ramstage.h> +#include <soc/gpio.h> +#include <gpio.h> +#include <string.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm)); + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + + params->PcieRpEnableCpm[2] = 1; // LAN1 + params->PcieRpEnableCpm[3] = 1; // LAN2 + params->PcieRpEnableCpm[6] = 1; // ASMedia PCIe to SATA + params->PcieRpEnableCpm[8] = 1; // NVMe + + // Max payload 256B + memset(params->PcieRpMaxPayload, 1, sizeof(params->PcieRpMaxPayload)); + + // I2C + params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6 + params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7 + + params->CnviRfResetPinMux = 0; + params->CnviClkreqPinMux = 0; + + /* GPP_B8 is EMMC_DET#, active low */ + gpio_input_pullup(GPP_B8); + params->ScsEmmcEnabled = !gpio_get(GPP_B8); + + +} diff --git a/src/mainboard/hardkernel/odroid_h4/romstage_fsp_params.c b/src/mainboard/hardkernel/odroid_h4/romstage_fsp_params.c new file mode 100644 index 0000000..2fb790d --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/romstage_fsp_params.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <soc/meminit.h> +#include <soc/gpio.h> + +#include "gpio.h" + +static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + .ect = true, /* Early Command Training */ + .UserBd = BOARD_TYPE_MOBILE, + .LpDdrDqDqsReTraining = 1, +}; + +static const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x52, + }, + }, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct pad_config *pads; + size_t num; + + memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false); + + pads = board_gpio_table(&num); + gpio_configure_pads(pads, num); + + memupd->FspmConfig.DmiMaxLinkSpeed = 4; +} diff --git a/src/mainboard/hardkernel/odroid_h4/vboot-rwa.fmd b/src/mainboard/hardkernel/odroid_h4/vboot-rwa.fmd new file mode 100644 index 0000000..c0956c5 --- /dev/null +++ b/src/mainboard/hardkernel/odroid_h4/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff000000 16M { + SI_ALL 6M { + SI_DESC 4K + SI_ME 0x413000 + SI_DEVICEEXT2 + } + SI_BIOS 10M { + SMMSTORE(PRESERVE) 256K + + RW_MISC 260K { + UNIFIED_MRC_CACHE(PRESERVE) { + RECOVERY_MRC_CACHE 128K + RW_MRC_CACHE 128K + } + RW_NVRAM(PRESERVE) 4K + } + + RW_SECTION_A { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + + WP_RO 5M { + RO_SECTION { + FMAP 2K + RO_FRID 0x100 + RO_FRID_PAD 0x700 + GBB 12K + COREBOOT(CBFS) + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84213?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee066cb0da27e3bf7ce52fc199396185912893aa Gerrit-Change-Number: 84213 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

1 0

[M] Change in coreboot[main]: soc/intel/{common,alderlake}: Add missing ADL-N SKUs
by Michał Żygowski (Code Review) 04 Sep '24

04 Sep '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84212?usp=email ) Change subject: soc/intel/{common,alderlake}: Add missing ADL-N SKUs ...................................................................... soc/intel/{common,alderlake}: Add missing ADL-N SKUs Based on DOC #767454 (public) version 1.2. Allows to boot the HARDKERNEL ODROID H4+ with N97 SoC. Withotu this patch the MCH ID was not recognized and the SA driver did not pick up the stolen ranges, causing the PCI MMIO allocation to be placed in the stolen areas. TEST=Boot HARDKERNEL ODROID H4+ with N97 SoC to Ubuntu 23.04. Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/vr_config.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 111 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/84212/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 481bf20..54fe0c1 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4394,6 +4394,10 @@ #define PCI_DID_INTEL_ADL_N_ID_3 0x461c #define PCI_DID_INTEL_ADL_N_ID_4 0x4614 #define PCI_DID_INTEL_ADL_N_ID_5 0x4618 +#define PCI_DID_INTEL_ADL_N_ID_6 0x4678 +#define PCI_DID_INTEL_ADL_N_ID_7 0x4679 +#define PCI_DID_INTEL_ADL_N_ID_8 0x467C +#define PCI_DID_INTEL_ADL_N_ID_9 0x4677 #define PCI_DID_INTEL_MTL_M_ID 0x7D00 #define PCI_DID_INTEL_MTL_P_ID_1 0x7D01 #define PCI_DID_INTEL_MTL_P_ID_2 0x7D02 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 6372cd6..57e4f52 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -63,6 +63,10 @@ { PCI_DID_INTEL_ADL_N_ID_3, "Alderlake-N" }, { PCI_DID_INTEL_ADL_N_ID_4, "Alderlake-N" }, { PCI_DID_INTEL_ADL_N_ID_5, "Alderlake-N" }, + { PCI_DID_INTEL_ADL_N_ID_6, "Alderlake-N" }, + { PCI_DID_INTEL_ADL_N_ID_7, "Alderlake-N" }, + { PCI_DID_INTEL_ADL_N_ID_8, "Alderlake-N" }, + { PCI_DID_INTEL_ADL_N_ID_9, "Alderlake-N" }, { PCI_DID_INTEL_ADL_S_ID_1, "Alderlake-S (8+8)" }, { PCI_DID_INTEL_ADL_S_ID_2, "Alderlake-S" }, { PCI_DID_INTEL_ADL_S_ID_3, "Alderlake-S (8+4)" }, diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index c8005de..67d83b4 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -54,9 +54,13 @@ ADL_M_242_CORE, ADL_P_442_45W_CORE, ADL_N_081_7W_CORE, + ADL_N_081_9W_CORE, ADL_N_081_15W_CORE, ADL_N_041_6W_CORE, + ADL_N_041_12W_CORE, + ADL_N_041_15W_CORE, ADL_N_021_6W_CORE, + ADL_N_021_10W_CORE, ADL_S_882_35W_CORE, ADL_S_882_65W_CORE, ADL_S_882_125W_CORE, @@ -111,6 +115,7 @@ TDP_6W = 6, TDP_7W = 7, TDP_9W = 9, + TDP_10W = 10, TDP_12W = 12, TDP_15W = 15, TDP_28W = 28, @@ -148,12 +153,16 @@ { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, - { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_7W_CORE, TDP_7W }, { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W }, { PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W }, { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_6W_CORE, TDP_6W }, + { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_15W_CORE, TDP_15W }, + { PCI_DID_INTEL_ADL_N_ID_6, ADL_N_041_12W_CORE, TDP_12W }, + { PCI_DID_INTEL_ADL_N_ID_7, ADL_N_041_12W_CORE, TDP_12W }, + { PCI_DID_INTEL_ADL_N_ID_8, ADL_N_021_6W_CORE, TDP_6W }, + { PCI_DID_INTEL_ADL_N_ID_9, ADL_N_021_10W_CORE, TDP_10W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_65W_CORE, TDP_65W }, { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W }, diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 0ab7c8a..7ae1990 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -54,6 +54,12 @@ .tdp_pl4 = 78, }" + register "power_limits_config[ADL_N_081_9W_CORE]" = "{ + .tdp_pl1_override = 9, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" + register "power_limits_config[ADL_N_081_15W_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 35, @@ -66,12 +72,30 @@ .tdp_pl4 = 78, }" + register "power_limits_config[ADL_N_041_12W_CORE]" = "{ + .tdp_pl1_override = 12, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + + register "power_limits_config[ADL_N_041_15W_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" + register "power_limits_config[ADL_N_021_6W_CORE]" = "{ .tdp_pl1_override = 6, .tdp_pl2_override = 25, .tdp_pl4 = 78, }" + register "power_limits_config[ADL_N_021_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + register "power_limits_config[RPL_P_682_642_482_45W_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 92b2532..255082f 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -242,6 +242,10 @@ PCI_DID_INTEL_ADL_N_ID_3, PCI_DID_INTEL_ADL_N_ID_4, PCI_DID_INTEL_ADL_N_ID_5, + PCI_DID_INTEL_ADL_N_ID_6, + PCI_DID_INTEL_ADL_N_ID_7, + PCI_DID_INTEL_ADL_N_ID_8, + PCI_DID_INTEL_ADL_N_ID_9, }; const uint16_t rpl_hx_mch_ids[] = { diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8dca5b0..8c4c291 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -596,6 +596,10 @@ case PCI_DID_INTEL_ADL_N_ID_3: case PCI_DID_INTEL_ADL_N_ID_4: case PCI_DID_INTEL_ADL_N_ID_5: + case PCI_DID_INTEL_ADL_N_ID_6: + case PCI_DID_INTEL_ADL_N_ID_7: + case PCI_DID_INTEL_ADL_N_ID_8: + case PCI_DID_INTEL_ADL_N_ID_9: return config->vccin_aux_imon_iccmax ? config->vccin_aux_imon_iccmax : ICC_MAX_ID_ADL_N_MA; case PCI_DID_INTEL_ADL_S_ID_1: diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index c3584ba..95dba9f 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -123,11 +123,17 @@ { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) }, - { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, - { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, - { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, - { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, - { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_1, 9, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_5, 15, VR_CFG_ALL_DOMAINS_LOADLINE(4.7, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_6, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, @@ -187,11 +193,17 @@ { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_ICC(53, 29) }, - { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, - { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, - { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) }, - { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, - { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, + { PCI_DID_INTEL_ADL_N_ID_1, 9, VR_CFG_ALL_DOMAINS_ICC(53, 29) }, + { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_ICC(37, 26) }, + { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, + { PCI_DID_INTEL_ADL_N_ID_5, 15, VR_CFG_ALL_DOMAINS_ICC(53, 29) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, + { PCI_DID_INTEL_ADL_N_ID_6, 12, VR_CFG_ALL_DOMAINS_ICC(37, 29) }, + { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_ICC(37, 23) }, + { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, + { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, @@ -251,11 +263,17 @@ { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, - { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, - { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, - { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, - { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, - { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_1, 9, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_6, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, @@ -314,12 +332,18 @@ { PCI_DID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, { PCI_DID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, { PCI_DID_INTEL_ADL_P_ID_10, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, - { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, - { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(14, 14) }, - { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, - { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, - { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) }, - { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, + { PCI_DID_INTEL_ADL_N_ID_1, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 20) }, + { PCI_DID_INTEL_ADL_N_ID_1, 9, VR_CFG_ALL_DOMAINS_TDC_CURRENT(17, 16) }, + { PCI_DID_INTEL_ADL_N_ID_1, 7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(14, 14) }, + { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) }, + { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) }, + { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) }, + { PCI_DID_INTEL_ADL_N_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 20) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 20) }, + { PCI_DID_INTEL_ADL_N_ID_6, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) }, + { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) }, + { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) }, + { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, @@ -404,8 +428,10 @@ s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit; } else { uint8_t tdp = get_cpu_tdp(); - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - uint16_t mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *gt = pcidev_path_on_root(SA_DEVFN_IGD); + uint16_t mch_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xffff; + uint16_t gt_id = gt ? pci_read_config16(gt, PCI_DEVICE_ID) : 0xffff; s_cfg->AcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll), domain, mch_id, tdp); @@ -419,6 +445,14 @@ s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit, ARRAY_SIZE(vr_config_tdc_currentlimit), domain, mch_id, tdp); + + /* Exception: following ADL-N SKUs may have different GT TDC based on GT ID */ + if (mch_id == PCI_DID_INTEL_ADL_N_ID_2 || mch_id == PCI_DID_INTEL_ADL_N_ID_3) { + if (gt_id == PCI_DID_INTEL_ADL_N_GT1) + s_cfg->TdcCurrentLimit[VR_DOMAIN_GT] = VR_CFG_AMP(20); + else if (gt_id == PCI_DID_INTEL_ADL_N_GT2) + s_cfg->TdcCurrentLimit[VR_DOMAIN_GT] = VR_CFG_AMP(19); + } } fill_vr_fast_vmode(s_cfg, domain, chip_cfg); diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e8d7432..fca2d67 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -531,6 +531,10 @@ PCI_DID_INTEL_ADL_N_ID_3, PCI_DID_INTEL_ADL_N_ID_4, PCI_DID_INTEL_ADL_N_ID_5, + PCI_DID_INTEL_ADL_N_ID_6, + PCI_DID_INTEL_ADL_N_ID_7, + PCI_DID_INTEL_ADL_N_ID_8, + PCI_DID_INTEL_ADL_N_ID_9, PCI_DID_INTEL_RPL_HX_ID_1, PCI_DID_INTEL_RPL_HX_ID_2, PCI_DID_INTEL_RPL_HX_ID_3, -- To view, visit https://review.coreboot.org/c/coreboot/+/84212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9 Gerrit-Change-Number: 84212 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

1 0

[S] Change in coreboot[main]: soc/intel/common/systemagent: Fixup systemagent address
by Shuo Liu (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent: Fixup systemagent address ...................................................................... Patch Set 18: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83318/comment/1e511e65_ff3adea4?us… : PS15, Line 14: soc_systemagent_fixup_address() to improve it. > to improve it -> to handle the special cases. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 18 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Sep 2024 09:40:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/yavilla: Add 1.2V enable pin in VCM
by Chen Wisley (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/84211?usp=email to review the following change. Change subject: mb/google/nissa/var/yavilla: Add 1.2V enable pin in VCM ...................................................................... mb/google/nissa/var/yavilla: Add 1.2V enable pin in VCM Add control for the 1.2V enable pin in VCM to comply the mipi camera power sequence. 2.8V enable --> 1.2V enable --> reset BUG=b:362386165 TEST=Run ITS test Change-Id: I495b2e266ee3d24ed3334bb9c173b3993d095e8e Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/yavilla/overridetree.cb 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/84211/1 diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb index ee5a3b6..973a16b 100644 --- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb +++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb @@ -404,17 +404,20 @@ #Controls register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X - register "gpio_panel.gpio[1].gpio_num" = "GPP_D3" # WCAM_RST_L + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L #_ON - register "on_seq.ops_cnt" = "2" + register "on_seq.ops_cnt" = "3" register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" #_OFF - register "off_seq.ops_cnt" = "2" + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" - register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" device i2c 0C on probe WFC WFC_MIPI_OVTI8856 -- To view, visit https://review.coreboot.org/c/coreboot/+/84211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I495b2e266ee3d24ed3334bb9c173b3993d095e8e Gerrit-Change-Number: 84211 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com>

1 0

[M] Change in coreboot[main]: include/spd_bin.h: Add SPD IO layer
by Shuo Liu (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/84201?usp=email ) Change subject: include/spd_bin.h: Add SPD IO layer ...................................................................... Patch Set 4: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84201/comment/0ab9b950_23fcdfb8?us… : PS2, Line 10: default implementation is to forward to SMBus IO functions directly. > revise as? By default, PCH SMBus codes will be called to retrieve SPD data. […] Done Commit Message: https://review.coreboot.org/c/coreboot/+/84201/comment/8dd09d9d_3c7ac92d?us… : PS3, Line 9: By default, PCH SMBus code will be called to retrieve SPD data. This > codes Done https://review.coreboot.org/c/coreboot/+/84201/comment/f7e2406b_9c3f883f?us… : PS3, Line 10: patch add a SPD IO layer so that SoC could implement its specific SPD > adds Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84201?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917 Gerrit-Change-Number: 84201 Gerrit-PatchSet: 4 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Comment-Date: Wed, 04 Sep 2024 09:40:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

1 0

[S] Change in coreboot[main]: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER
by Name of user not set (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Shuo Liu, yuchi.chen(a)intel.com. Hello Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84200?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified-1 by build bot (Jenkins) Change subject: soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER ...................................................................... soc/intel/common/systemagent: Add Kconfig item HAVE_TSEG_LIMIT_REGISTER System agent assumes GSM region is next to TSEG region, but some SoC may not have GSM region, see patch https://review.coreboot.org/c/coreboot/+/84108. On such platforms, TSEG limit is defined by a dedicated TSEG limit register, and the default offset for that limit register is (TSEG Base + 4). Change-Id: I6cb4fbecc1dbafc770d3809a75d05917a141a9af Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent_early.c 2 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/84200/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6cb4fbecc1dbafc770d3809a75d05917a141a9af Gerrit-Change-Number: 84200 Gerrit-PatchSet: 3 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>

1 0

[M] Change in coreboot[main]: include/spd_bin.h: Add SPD IO layer
by Name of user not set (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Shuo Liu, yuchi.chen(a)intel.com. Hello Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84201?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: include/spd_bin.h: Add SPD IO layer ...................................................................... include/spd_bin.h: Add SPD IO layer By default, PCH SMBus codes will be called to retrieve SPD data. This patch adds a SPD IO layer so that SoC could implement its specific SPD IO layer functions such as using Integrated Memory Controller to get SPD data. Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/include/spd_bin.h M src/soc/intel/common/block/smbus/Makefile.mk M src/soc/intel/common/block/smbus/smbuslib.c A src/soc/intel/common/block/smbus/spd_access.c 4 files changed, 40 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/84201/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84201?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917 Gerrit-Change-Number: 84201 Gerrit-PatchSet: 4 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>

1 0

[S] Change in coreboot[main]: soc/intel/common/systemagent: Fixup systemagent address
by Name of user not set (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Shuo Liu, yuchi.chen(a)intel.com. Hello Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83318?usp=email to look at the new patch set (#18). The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/systemagent: Fixup systemagent address ...................................................................... soc/intel/common/systemagent: Fixup systemagent address System agent in Intel common block (1) assumes TOLUD and TOUUD registers hold the max available address plus 1, but on some SoC like Snow Ridge, it holds the max available address; (2) aligns TOLUD, TOUUD and TSEG registers to 1 MiB default, but some SoC may have different alignments. This patch add a new function soc_systemagent_fixup_address() to handle this special cases. Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_early.c 4 files changed, 38 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83318/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 18 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[S] Change in coreboot[main]: soc/intel/{adl,mtl}: Don't set up SPD on LPDDRx
by Subrata Banik (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Arthur Heymans, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Rishika Raj, Tarun. Subrata Banik has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84205?usp=email ) Change subject: soc/intel/{adl,mtl}: Don't set up SPD on LPDDRx ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/meteorlake/meminit.c: https://review.coreboot.org/c/coreboot/+/84205/comment/81058612_674e34a1?us… : PS2, Line 209: has_spd = true; > > > > > > Can you help me understand the purpose of `has_spd`? Does it mean the mainboard has an SPD chip and we'll read the hex file using SMBUS? > > > > > > > > > > would need_spd be a better name? LPDDRx DRAM technology does not use SPD and the code for SPD in soc/intel/common is doing doing undefined behavior like overflowing an array. > > > > > > > > Yes, that name sounds better. I'd like to suggest adding a comment that explains the purpose of this variable. People often confuse the SPD chip with the SPD hex data file. The code should make it clear that the SPD chip isn't required to read the SPD hex file (need_spd). > > > > > > No actually it's about SPD data and this code is wrong. The soc/intel/common code is simply wrong for LPDDRx. The loop over channels and dimms per channel is overflowing. There are no DIMMs in LPDDRx which is what need to be addressed. > > > > okay, so when you set `has_spd` or `need_spd`, are you saying that we will read SPD data over SMBUS and for lpddrx, we shall pass SPD hex file ? > > No that's not the issue. CONFIG_DIMM_MAX is 4 which is how large the array is for containing SPD pointers. LPDDRx has 16 bit per channel, so the code thinks there are 8 channels in total. CONFIG_DIMM_PER_CHANNEL is set to 2. The common code loops over channels and dimms per channel so it's overflowing. What is the appropriate fix? do you think. > > https://qa.coreboot.org/job/coreboot-gerrit/263746/testReport/junit/(root)/… is the compilation error with LTO which can detect the buffer overflow. will this work ? ``` git diff diff --git a/src/soc/intel/common/block/memory/meminit.c b/src/soc/intel/common/block/memory/meminit.c index f583213254..cf12aff803 100644 --- a/src/soc/intel/common/block/memory/meminit.c +++ b/src/soc/intel/common/block/memory/meminit.c @@ -189,12 +189,13 @@ void mem_populate_channel_data(FSPM_UPD *memupd, const struct soc_mem_cfg *soc_m struct mem_channel_data *data) { size_t spd_md_len = 0, spd_dimm_len = 0; - bool have_dimms; + bool have_dimms = 0; memset(data, 0, sizeof(*data)); read_spd_md(soc_mem_cfg, spd_info, half_populated, data, &spd_md_len); - have_dimms = read_spd_dimm(memupd, soc_mem_cfg, spd_info, half_populated, data, + if ((info->topo & MEM_TOPO_DIMM_MODULE) + have_dimms = read_spd_dimm(memupd, soc_mem_cfg, spd_info, half_populated, data, &spd_dimm_len); if (data->ch_population_flags == NO_CHANNEL_POPULATED) ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84205?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3d4ed8032bb06b6d08fbc2dc4b697df88745243 Gerrit-Change-Number: 84205 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 08:57:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

[M] Change in coreboot[main]: soc/intel: Refactor ITSS macros
by Jayvik Desai (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Arthur Heymans, Christian Walter, Eran Mitrani, Jakub Czapiga, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nick Vaccaro, Patrick Rudolph, Rishika Raj, Subrata Banik, Tarun, Tim Chu, Werner Zeh. Jayvik Desai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84183?usp=email ) Change subject: soc/intel: Refactor ITSS macros ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84183?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6461dc93b0d21bec5429075bc26435bae3754d74 Gerrit-Change-Number: 84183 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 08:56:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2024